1 Introduction

Mem-elements (memristor, meminductor, and memcapacitor) are now being used in a variety of applications including brain-inspired neuromorphic computing [1, 2], secure communications [3], artificial intelligence circuits [4], neural networks [5], non-volatile memories [6], in-memory computation [7], etc. Their wide range of applications is possible due to the unique features offered such as non-linear behaviour, and the inherent memory properties that open a window for in-memory computation. These two unique characteristics of mem-elements make them superior to the conventional circuit elements i.e., resistors, capacitors, and inductors. The properties offered by mem-elements cannot be replicated by combining the properties of the conventional circuit elements. Due to this fact, mem-elements are now treated as specific elements that are dominating many areas of science and engineering including electronics and communication, electrical, computer science, biological sciences, etc. All credit goes to Prof. Leon Chua who envisaged the memristor long back in 1971 in his seminal paper [8]. Later, Prof. Chua and Prof. S. M. Kang generalized the idea of memristive systems in 1976 [9]. In current scenarios, memristive systems are viewed as the future of electronics [10]. The constraints of CMOS technology have become a bottleneck to advancing the performance of systems in terms of speed, area, and power dissipation. These limitations are due to the adverse effects of CMOS technology which became dominating when the size of CMOS is reduced beyond the limit and no further improvement is possible. Memristor (memory-resistor) has paved the way as an alternative of CMOS technology due to its inherent ability of tininess and very low power consumption. Due to above-mentioned facts, the coming era of electronics and computer engineering belong to memristors and the two other members of the mem-elements namely memcapacitors and meminductors. A lot has already been done on memristor and it is presently available as an off-the-shelf component in the market. However, the same cannot be said for memcapacitor and meminductor. Consequently, the goal of this paper is to realize a simple meminductor emulator configuration. Mem-elements possess almost similar characteristics when a periodic signal is applied across their terminals. Pinched hysteresis loops (PHLs) are observed that indicate the existence of memory inside them. These PHLs have been observed between charge (q) and flux (ɸ) for memristor (MR), whereas it is observed between charge (q) and voltage (v), and flux (ɸ) and current (i), for memcapacitor (MC) and meminductor (ML) respectively. The inter-relations among these mem-elements are given in Fig. 1 [11]. The following equations serve as a definition of meminductive systems.

$$\rho \left( {\text{t}} \right) \, = \mathop \smallint \limits_{ - \infty }^t \phi (t)dt$$
(1)
$$q(t) - \mathop \smallint \limits_{ - \infty }^t i\left( t \right)dt$$
(2)
$$d\rho = M_L dq$$
(3)

where ML represents the meminductance of the emulator. From Eqs. (1), (2), and (3), the relation between flux (ɸ) and current (i) is deduced as:

$$\phi \left(t\right)={M}_{L}i\left(t\right)$$
(4)

where i(t) and ɸ(t) are the meminductive current and induced flux respectively. The flux ɸ(t) of meminductor is defined as:

$$\phi \left( t \right) \mathop \smallint \limits_{ - \infty }^t V_{in } \left( t \right)dt$$
(5)

where Vin(t) is the periodic signal applied across the meminductor.

Fig. 1
figure 1

Interrelations among mem-elements [11]

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In the literature, a number of meminductor emulators have been reported. The significant meminductors available in open literature have been summarized in Table 1. The objective of the work in this paper is to develop a single active building block (ABB) based floating meminductor emulator. The focus has been on realizing an electronically tunable meminductor with a simple structure, sparse use of passive components, and broad frequency operation.

Table 1 Comparison with the work available in open literature
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The structure of the proposed meminductor is very simple and requires only one modified differential voltage current conveyor transconductance amplifier (MDVCCTA), one resistor, and two capacitors. The incremental and decremental modes of operation can be obtained by adding one switch at the input side. The proposed meminductor has the following characteristics: (i) the circuit is very simple and does not require any multipliers (ii) both incremental and decremental modes can be obtained (iii) flexible to use in both grounded and floating modes (iv) large frequency range (v) does not use any memristor. Various features such as, the number of analog building blocks, operating frequency, multiplier/multiplier-less, electronic tunability, number of passive components, floating/grounded mode, inductor/inductor-less, flux/charge controlled, incremental/decremental configurations, matching conditions, control parameters, and power supply are used to compare the proposed meminductor to previously reported circuits in the literature.

The following conclusions are drawn in view of the comparison shown in Table 1:

  1. 1.

    The proposed circuit uses only one MDVCCTA, whereas previously reported circuits in reference no. [13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35, 38, 39, 41, 42, 44,45,46,47,48, 50, 51, 53, 55,56,57,58, 61,62,63] use more than one building block.

  2. 2.

    The proposed emulator design does not require any memristor, whereas the circuits reported in reference no. [12, 14,15,16, 21, 25, 26, 37, 40, 43, 52, 53, 57] require a memristor for their implementation.

  3. 3.

    The recommended circuit is electronically tunable, but the meminductors reported in reference numbers [12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30, 36, 43, 49, 53, 56,57,58,59, 62] are not electronically tunable.

  4. 4.

    The suggested emulator can be operated in both grounded and floating modes, but the emulators reported in reference no. [12,13,14,15, 18, 22, 23, 27, 32,33,34, 36, 43, 46,47,48,49, 52, 53, 56,57,58, 60, 62] can only be operated in grounded mode.

  5. 5.

    The meminductor emulator of reference numbers [13, 18,19,20, 22,23,24, 27, 28, 31,32,33, 48, 49, 61] use multiplier but in the proposed circuit no multiplier is needed.

  6. 6.

    The meminductor emulators reported in reference numbers [12, 13, 16,17,18,19,20,21,22,23,24, 26,27,28,29, 31, 32, 35,36,37, 40, 43, 48, 48,49,50,51,52,53, 57,58,59] work satisfactorily in the operating frequency between Hz to kHz range but the proposed circuit operates up to MHz range. The operating frequency of the meminductor emulator reported in reference [54] is 50 MHz and in [60] is 25 MHz, whereas the proposed meminductor works up to 80 MHz with some shifting in cross-over point.

  7. 7.

    The limitation of the proposed meminductor emulator is the restricted range of tunability and shifted pinched point at higher frequencies.

  8. 8.

    The meminductor emulator of reference numbers [13, 15, 21,22,23, 32,33,34, 49, 52, 53, 57, 61] use high power supply voltage but in the proposed circuit use only ± 0.9 V.

  9. 9.

    The meminductor reported in the reference numbers [13, 21, 23, 28, 30, 36, 37, 40, 49, 55, 61, 62] are operated on charge-controlled mode whereas the proposed circuit operated on flux-controlled mode.

  10. 10.

    The proposed meminductor is working on both incremental and decremental mode but previously reported circuits in reference no [13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32, 36, 38, 41, 47, 49, 51,52,53, 57,58,59,60,61,62] is working on one mode only.

  11. 11.

    The meminductor reported in the reference numbers [14, 17, 19, 23, 28, 29, 38, 50, 53, 57] use matching conditions but the proposed circuit does not need any matching condition.

The work in the paper has been divided into 7 sections, including the 1st introductory section. Section 2 gives a brief description of the ABB used to design the suggested meminductor emulator. The explanation of the recommended meminductor along with its mathematical analysis has been given in Sect. 3. LTSpice results observed in 0.18 μm technology along with their appropriate discussion have been presented in Sect. 4. Section 5 focuses on the precision analysis and study of non-ideal aspects related to the proposed meminductor emulator. The section delineates variations in its fundamental characteristics concerning changes in temperature, supply voltage, and component parameters. Furthermore, it provides an in-depth exploration of the influence of non-idealities and parasitic components within the MDVCCTA block. Application of the suggested meminductor in implementing chaotic oscillator and adaptive learning circuit has been explained in Sect. 6. Finally, the conclusion summary of the work is given in Sect. 7.

2 Description of MDVCCTA

The differential voltage current conveyor transconductance amplifier (DVCCTA) is a comparatively new ABB proposed by Pandey and Paul in 2011 [64]. It integrates the traits of a transconductance amplifier (TA) and a differential difference current conveyor (DDCC) [65]. The DVCCTA incorporates the adaptable and distinctive characteristics of DDCC, such as the simplicity with which differential and floating input circuits can be implemented, with the flexibility of in-built parameter tuning. The modified differential voltage current conveyor transconductance amplifier (MDVCCTA) is a modified version of a DVCCTA, which possess two transconductance amplifiers. The block diagram representing the input and output terminals of MDVCCTA is shown in Fig. 2. Y1 and Y2 are the differential input voltage terminals. X and Z are intermediate terminals responsible for generating voltage and current proportional to input voltage based on components attached to these terminals. O+ and O- are output current terminals of the transconductance amplifier unit and generate current proportional to the voltage developed at the Z terminal. The two transconductance gains of this unit can be controlled by biasing voltage VB2 and VB3.

Fig. 2
figure 2

Block diagram of MDVCCTA [64]

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The matrix equation depicting the port relations of MDVCCTA is given by Eq. (6).

$$\left[\begin{array}{c}{I}_{Y1} \\ {I}_{Y2} \\ {V}_{X} \\ {I}_{Z1} \\ {I}_{O1\pm }\\ {I}_{O2\pm } \end{array}\right]=\left[\begin{array}{cccc} 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 \\ 1 & -1 & 0 & 0 \\ 0 & 0 & 1 & 0 \\ 0 & 0 & 0 & {\pm G}_{m1} \\ 0 & 0 & 0 & {\pm G}_{m2} \end{array} \right] \left[\begin{array}{c}{V}_{Y1}\\ {V}_{Y2}\\ {I}_{X}\\ {V}_{Z}\end{array}\right]$$
(6)

In Eq. (6), Gm1 and Gm2 represent the transconductance gains of MDVCCTA. Assuming symmetric differential pairs, transconductance for the proposed circuit can be written as:

$${G}_{m\mathrm{1,2}}={K}_{\mathrm{1,2}}\left({V}_{B2,B3}-{V}_{SS}-2{V}_{th}\right)$$
(7)

here, β represents the transconductance parameter of the corresponding MOSFET, VSS is the negative supply voltage and Vth is the threshold voltage of a MOSFET. In addition, VB2 and VB3 are the biasing voltages responsible for controlling the biasing current of first and second transconductance amplifiers respectively. Here, K1 and K2 are the transconductance parameters defined as:

$${K}_{1}=\frac{\sqrt{{\beta }_{13}{\beta }_{14}{\beta }_{16}}}{\sqrt{2}\left(\sqrt{{\beta }_{13}}+\sqrt{{\beta }_{14}}\right)}$$
(8)
$${K}_{2}=\frac{\sqrt{{\beta }_{30}{\beta }_{31}{\beta }_{33}}}{\sqrt{2}\left(\sqrt{{\beta }_{30}}+\sqrt{{\beta }_{31}}\right)}$$
(9)

The MOSFET-based complete circuit of MDVCCTA is illustrated in Fig. 3.

Fig. 3
figure 3

Circuit diagram of MDVCCTA

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3 Proposed MDVCCTA-based electronically tunable floating meminductor

Figure 4 depicts the complete design of meminductor emulator proposed in the paper. In this circuit, the differential input signal is directed between Y1 and Y2 terminals of MDVCCTA. This differential signal is transferred to the “X” terminal, where the resistor R1 generates a current proportional to an input voltage signal. Further, this current is copied at the “Z” terminal of the MDVCCTA block. This current charge the capacitor C1 connected at this node, leading to the generation of a voltage VZ at the “Z” terminal. A current directly proportional to VZ appears at the output terminal (O±), which leads to a similar current to be drawn from the input voltage source. The output terminals are shorted to input Y terminals. These arrangements lead to the inductive behaviour of the circuit depicted in Fig. 4. A capacitor C2 is connected to VB3 and as shown in the circuit, the current flowing through O1- terminal charges this capacitor. This current being proportional to the input voltage (Vin), makes a feedback connection that ensures the meminductive input current to be dependent on the input flux (ϕ). This leads to the meminductive behaviour of the circuit.

Fig. 4
figure 4

MDVCCTA based proposed meminductor emulator

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3.1 Derivation of meminductance of proposed meminductor

The proposed meminductor can be used in incremental configuration (“x” connected to “a” and “y” connected to “b”) as well as decremental configuration (“x” connected to “b” and “y” connected to “a”). Using the terminal equations of MDVCCTA depicted in Eq. 6 and performing basic analysis of the meminductor circuit given in Fig. 4 for incremental configuration, the terminal voltages VX (Voltage at X terminal), VZ (Voltage at Z terminal) and VB3 (Voltage at VB3 terminal) can be represented as:

$${V}_{X}={V}_{Y1}-{V}_{Y2}={\left({V}_{in1}-{V}_{in2}\right)=V}_{in }\left(say\right)$$
(10)
$${V}_{Z}={V}_{C1}=-\frac{1}{{C}_{1}}{\int }_{0}^{t}{I}_{Z}dt=-\frac{1}{{C}_{1}}{\int }_{0}^{t}{I}_{X}dt$$
(11)
$${V}_{Z}=-\frac{1}{{C}_{1}}{\int }_{0}^{t}\frac{{-V}_{X}}{{R}_{1}}dt=\frac{1}{{C}_{1}{R}_{1}}{\int }_{0}^{t}{V}_{in}dt$$
(12)

Applying Kirchoff’s voltage law, VB3 can be derived as:

$${V}_{B3}={V}_{C2}=\frac{1}{{C}_{2}}{\int }_{0}^{t}{I}_{O1-}dt=-\frac{1}{{C}_{2}}{\int }_{0}^{t}{G}_{m1}{V}_{Z}dt$$
(13)

Using the integral relations given by Eqs. (5) and (1), and performing mathematical simplification, Eqs. (9) and (10) can be expressed as:

$${V}_{Z}=\frac{1}{{C}_{1}{R}_{1}}\phi \left(t\right)$$
(14)
$${V}_{B3}=-\frac{{G}_{m1}}{{{C}_{1}C}_{2}{R}_{1}}\rho \left(t\right)$$
(15)

Equations (14) and (15) have been written considering all the capacitances to be initially relaxed. Analysing circuit of MDVCCTA based meminductor shown in Fig. 4, input current (Iin) can be expressed as:

$${I}_{in}=-{I}_{O1+}={-G}_{m2}{V}_{Z}$$
(16)

Here, Gm1 and Gm2 are the two transconductance gains of the MDVCCTA block, that are defined by Eq. (7). Combining Eqs. (14) and (16) and later substituting Gm2 and VB3 from Eqs. (7) and (15) respectively, Iin can be expressed as:

$${I}_{in}=\frac{{K}_{2}}{{C}_{1}{R}_{1}}\left[\frac{{G}_{m1}}{{{C}_{1}C}_{2}{R}_{1}}\rho \left(t\right)+{V}_{SS}+2{V}_{th}\right]\phi \left(t\right)$$
(17)

From Eq. (17) and considering relation (4), ML−1 of the proposed meminductor is given as:

$$\begin{gathered} M_L^{ - 1} = \left[ {\frac{K_2 }{{C_1 R_1 }}\left( {V_{SS} + 2V_{th} } \right) + \frac{{K_2 G_{m1} }}{C_1^2 C_2 R_1^2 }\rho \left( t \right)} \right] \hfill \\ {\text{fixed term}} {\text{variable term}} \hfill \\ \end{gathered}$$
(18)

From Eq. (18), it can be analysed that meminductance of the suggested meminductor comprises of a fixed component and a variable component. The fixed term is dependent on the MOSFET threshold voltage and the circuit's negative supply voltage. However, the variable term depends on input voltage and can be controlled by passive components (C1, C2 and R1) and transconductance of the amplifier.

The suggested meminductor design given in Fig. 4 can be used in decremental mode by connecting “x” node to “b” and “y” node to “a” in the switch shown in Fig. 4. The derivation of meminductance of the proposed circuit in this configuration can be carried out using the steps similar to the incremental mode derivation. In this case, the terminal voltage and current equations can be derived as:

$${V}_{Z}=-\frac{1}{{C}_{1}{R}_{1}}\phi \left(t\right)$$
(19)
$${V}_{B3}=\frac{{G}_{m1}}{{{C}_{1}C}_{2}{R}_{1}}\rho \left(t\right)$$
(20)
$${I}_{in}=-{I}_{O1-}={G}_{m2}{V}_{Z}=\frac{{K}_{2}}{{C}_{1}{R}_{1}}\left[-\frac{{G}_{m1}}{{{C}_{1}C}_{2}{R}_{1}}\rho \left(t\right)+{V}_{SS}+2{V}_{th}\right]\phi \left(t\right)$$
(21)

Using Eq. (21) and Eq. (4), ML−1 of the proposed meminductor in decremental configuration is given as:

$$\begin{gathered} M_L^{ - 1} = \left[ {\frac{K_2 }{{C_1 R_1 }}\left( {V_{SS} + 2V_{th} } \right) - \frac{{K_2 G_{m1} }}{C_1^2 C_2 R_1^2 }\rho \left( t \right)} \right] \hfill \\ {\text{Fixed term}} {\text{Variable term}} \hfill \\ \end{gathered}$$
(22)

In decremental configuration, the fixed term is positive while the variable term of meminductance is negative. However, the magnitude and dependency of both the terms are same as that of the incremental configuration.

In the derivation of the incremental and decremental meminductance relations for the proposed emulator, Gm1 is supposed to be fixed. However, this gain term can be adjusted by regulating the bias voltage applied at VB2 terminal, imparting tunability feature to the proposed emulator.

4 Simulation results and discussion

The simulation results of the meminductor circuit designed in the paper have been shown in this section. These results have been generated in the LTspice tool. The MOSFETs of the CMOS-based MDVCCTA circuit have been implemented with a 0.18 μm model file. Supply voltage of ± 0.9 V, VB1 = 0.1 V and VB2 = 0.4 V have been used for the simulation of the MDVCCTA block. The feature size of the MOSFETs has been listed in Table 2. The basic characteristics of the suggested meminductor emulator have been plotted with C1 = C2 = 5pF and R1 = 1kΩ.

Table 2 Feature size of the MOSFETs of MDVCCTA block
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4.1 Simulation results of proposed floating meminductor when operated in incremental configuration

Initially, the proposed meminductor emulator's characteristics working as an incremental meminductor have been studied. To achieve incremental mode, the switch is connected as “x” to “a” and “y” to “b”. To examine the inductive behaviour of the proposed configuration, its transient response is observed with a bipolar signal of 100 mV amplitude and 10 kHz frequency. The waveforms observed for input current and flux (\(\phi\)) have been shown in Fig. 5. The flux (\(\phi =\int {V}_{in}dt\)) was measured at the input terminal. The phase lag witnessed in flux and current waveforms determine the inductive nature of the proposed circuit.

Fig. 5
figure 5

Transient analysis of proposed meminductor

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Non-volatile behaviour is one of the most important fingerprints for meminductors. When a pulse signal is provided, it anticipates that the meminductance will change correspondingly during the pulse's ON time, while it retains its value during the OFF time of the pulse. To observe the non-volatile behaviour of the circuit, a pulse signal of 25 mV amplitude, with 1 μs ON period and 10 μs OFF period has been applied. The resultant meminductance is depicted in Fig. 6. This meminductance (ML) has been obtained by dividing the flux (ɸ) by the input current.

Fig. 6
figure 6

Waveform showing variations in meminductance caused by the introduction of a pulse signal

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(Iin). From this figure, it is evident that the meminductance remains constant during the OFF period of the input pulse but varies during the ON phase, validating the concept that the proposed meminductor is non-volatile.

Another essential feature of a meminductor is a pinched hysteresis loop (PHL) in flux (ɸ) vs. current (i) plane, when a bipolar signal is applied. A sinusoidal signal of 10 kHz frequency and 100 mV amplitude has been applied to the suggested meminductor and the response observed is plotted in Fig. 7.

Fig. 7
figure 7

Response of the proposed meminductor to a 10 kHz sinusoidal signal

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The dumbbell shape of the PHL curve with zero-crossing, as seen in Fig. 7, further supports the proposed circuit's meminductive behaviour. The PHL curves are seen in the proposed meminductor for a wide range of input frequency signals. These loops for frequencies varying from 40 kHz to15MHz have been drawn in Fig. 8a and b. To obtain the PHL curves with zero-crossing for the specified range of frequencies, the passive components have been adjusted. The decreasing area of the PHL lobes with an increase in frequency is another essential feature of a meminductive device. The PHL curves of Fig. 8 provide a good visual representation of this characteristic.

Fig. 8
figure 8

PHL curves observed for the proposed meminductor for a frequency range (a) 40 kHz to 100 kHz and (b) 5–15 MHz

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Several applications demand capacitive tuning of a circuit. The circuit's capacitance tunability feature is determined by the property of change in PHL shape with changes in capacitance. To investigate this feature in the proposed meminductor, its response in φ vs. i plane for 10 kHz sinusoidal signal with different values of C1 and C2 has been analyzed. The curves obtained for varying C1 and C2 from 5 to 15pF have been plotted in Fig. 9. These curves shown in Fig. 9 depict the capacitance tunability feature of the proposed meminductor.

Fig. 9
figure 9

PHL curves observed for the proposed meminductor for different values of capacitors

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Electronic tunability is a feature that allows variations in key parameters of a circuit with changes in applied bias voltage or bias current. To illustrate the electronic tunability behaviour of the proposed meminductor, its PHL has been plotted in Fig. 10 for different values of VB2. All these cures have been drawn for an input signal of 10 kHz, 100 mV sinusoidal signal.

Fig. 10
figure 10

PHL curves obtained for different values of VB2

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4.2 Simulation results of proposed floating meminductor emulator when operated in decremental configuration:

The curves plotted in Figs. 7, 8, 9, 10 are for incremental configuration of the suggested meminductor emulator. It can be operated in decremental configuration, provided the switch is positioned to get the links between “x” to “b” and “y” to “a”. The transient analysis curve and the PHL curve observed for this configuration for 10 kHz, 100 mV sinusoidal signal have been shown in Fig. 11a and b respectively. These curves for input signal frequency varying from 40 kHz to 15 MHz are shown in Fig. 12. All these curves show that the proposed meminductor operates satisfactorily in decremental configuration for frequencies range of 40 kHz–15 MHz.

Fig. 11
figure 11

(a) Transient analysis and (b) the PHL plotted on ϕ vs. i plane for the decremental configuration of proposed meminductor for a sinusoidal frequency of 10 kHz

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Fig. 12
figure 12

PHL curves observed for the decremental configuration of proposed meminductor for a frequency range of 40 kHz to15MHz

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At higher frequencies, shifting in the pinched point (v = 0, i = 0) is observed in PHL curves. The shifting of pinched point can be mitigated with proper selection of values of capacitors. The PHL curves observed are not deformed up to 80 MHz frequency, as can be seen in Fig. 13a–d.

Fig. 13
figure 13

PHL curves observed for the incremental configuration of proposed meminductor for a frequency range of 20–80 MHz

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5 Precision analysis of proposed meminductor

Practically, a device will be subjected to different environmental and manufacturing conditions leading to variations in its behaviour. To check the tolerance of a device in a practical environment its behaviour must be examined under different values of parameters. The effects of varying the suggested meminductor's parameters have been examined in this section.

5.1 Temperature variation analysis

The proposed meminductor's behaviour with temperature fluctuations ranging from −55 °C to + 125 °C has been investigated. PHL curves obtained for incremental and decremental configuration of the proposed meminductor for the specified range of temperature variations have been shown in Fig. 14a and b. These figures illustrate how the proposed meminductor exhibits minor variations in the PHL curves' shapes, resulting in successful operation as meminductor within the designated temperature range.

Fig. 14
figure 14

PHL curves of proposed meminductor for temperature fluctuations from −55 to 125 °C (a) Incremental (b) Decremental

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5.2 Monte-Carlo analysis

A MOSFET is subjected to variations in aspect ratio and threshold voltage while being manufactured in a real environment. Monte Carlo (MC) analysis has been carried out to assess the effects of variations in the proposed meminductor's properties caused by fabrication limitations experienced by the constituent MOSFETs. The MC analysis has been performed with 5% variations in aspect ratio and the threshold voltage of MOSFETs using the Gaussian distribution function. The MC plots of PHL curves for a sinusoidal signal of 10 kHz frequency have been drawn in Fig. 15a and b for threshold variations for incremental and decremental meminductors respectively. These curves have been plotted for 100 runs. These MC plots illustrate that the shape of PHL curves is maintained while demonstrating only minor alterations because of changes in the MOSFET specifications, supporting the meminductive behaviour of the proposed circuit over the complete mismatch range.

Fig. 15
figure 15

PHL curves observed with Monte Carlo analysis for the proposed meminductor for 5% variations in (a) aspect ratio (b) threshold voltage

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5.3 Corner analysis

Based on fabrication technology and design environment, a MOSFET can undergo variations in design parameters. It has been observed that there is an upper and lower limit to the variations that can appear during a particular fabrication process. In view of this, 4 design corners have been specified for CMOS-based circuits. These design corners are: fast–fast (FF), fast-slow (FS), slow-fast (SF) and slow-slow (SS). In all these corners, the first term signifies the NMOS characteristic, and the second term represents PMOS behaviour. To ensure the robust operation of the proposed circuit, its behaviour at four different corners has been studied. The PHL curves observed for these design corners along with typical curves for a sinusoidal signal of 10 kHz have been shown in Fig. 16. From Fig. 16, it can be analysed that the PHL loops are observed at all the corners, confirming the effective functioning of the suggested design in the entire design space.

Fig. 16
figure 16

PHL curves observed with corner analysis for the proposed meminductor emulator

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5.4 Supply voltage variations

To analyse the effect of supply voltage variations on the behaviour of the proposed meminductor, the MDVCCTA block has been subjected to a variation of ± 10% in supply voltage. The proposed meminductor incorporating this MDVCCTA block is simulated with a sinusoidal signal of 10 kHz frequency and the resultant PHL curve observed in ϕ vs. i plane has been recorded in Fig. 17. These waveforms plot the PHL curves for variations in supply voltage from 0.81 to 0.99 V for VDD and −0.81 to −0.99 V for VSS. PHL curves shown in Fig. 17 confirm that the proposed meminductor operates satisfactorily with minor changes in lobe shape for ± 10% deviations in supply voltage.

Fig. 17
figure 17

PHL curves of the proposed meminductor observed with ± 10% deviations in supply voltage

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5.5 Variations due to resistance tolerance

Precise values of the components can never be achieved at the time of fabrication. There is always some tolerance in the component values, which may sometimes lead to circuit failure. To examine the effect of the variations in resistance values, the proposed meminductor has been simulated for different values of resistors. The PHL curves for the incremental and decremental meminductor, observed with different values of R1 (10kΩ, 20kΩ, and 30kΩ) have been plotted in Fig. 18.

Fig. 18
figure 18

PHL curves of the proposed meminductor observed with ± 10% deviations in R1 (a) Incremental (b) Decremental

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The figures from Figs. 14, 15, 16, 17, 18 show the tolerance of the proposed meminductor to changes in temperature, supply voltage, and component characteristics. All of these figures reveal that the PHL lobe's shape changes slightly while preserving the necessary shape when any of these parameters changes.

5.6 Non-ideal and parasitic analysis

The mathematical analysis and derivations presented in Sect. 3 were based on the assumption that the MDVCCTA depicted in Fig. 4 is ideal. In this analysis, the current and voltage transfers at various ports of the MDVCCTA block were treated as ideal, as indicated by Eq. (6). Additionally, the presence of parasitic elements in the active devices used to implement the block were disregarded. In this section, the meminductance of the proposed block has been derived while considering the impact of these non-ideal parameters and parasitic components. The port matrix of the MDVCCTA, accounting for non-idealities, can be expressed as:

$$\left[\begin{array}{c}\begin{array}{c}\begin{array}{c}{I}_{Y1}\\ {I}_{Y2} \end{array}\\ \begin{array}{c}{V}_{X}\\ {I}_{Z1}\end{array}\end{array}\\ \begin{array}{c}{I}_{O1\pm }\\ {I}_{O2\pm }\end{array}\end{array}\right]=\left[\begin{array}{cccc} 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 \\ \alpha & -\alpha & 0 & 0 \\ 0 & 0 & \beta & 0 \\ 0 & 0 & 0 & {\pm \gamma G}_{m1} \\ 0 & 0 & 0 & {\pm \gamma G}_{m2} \end{array} \right]\left[\begin{array}{c}\begin{array}{c}{V}_{Y1}\\ {V}_{Y2}\end{array}\\ \begin{array}{c}{I}_{X}\\ {V}_{Z}\end{array}\end{array}\right]$$
(23)

In Eq. (23), α and β denote the non-ideal voltage and current gains at terminals 'X' and 'Z' of the MDVCCTA, while γ represents the non-ideal parameter affecting the transconductance gain at port 'O' of the MDVCCTA. These parameters assume a value of unity in the ideal case. The equivalent circuit of the proposed meminductor, accounting for parasitic capacitors and resistors at various terminals of the MDVCCTA block, is illustrated in Fig. 19 [66].

Fig. 19
figure 19

Equivalent circuit of the proposed meminductor including the parasitic capacitors and resistors at different terminals

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To simplify the analysis, one terminal of the input voltage source is grounded. In this circuit, each parasitic component is identified by a superscript corresponding to the terminal at which it is present, while Rs represents the source resistance. Taking into account the non-idealities expressed by Eq. (23) and the parasitic components depicted in Fig. 19, the subsequent section provides the mathematical analysis of the meminductance for the proposed emulator.

Considering the specified non-idealitites and parasitics, port equations of MDVCCTA can be expressed as:

$${V}_{X}=\alpha {V}_{Y1}$$
(24)
$${I}_{X}=-\frac{{V}_{X}}{{R}_{1}+{R}_{X}}$$
(25)
$${I}_{01+}=\gamma {G}_{m1}{V}_{Z}$$
(26)
$${I}_{02+}=\gamma {G}_{m2}{V}_{Z}$$
(27)

Simple analysis of node ‘Z’ reveals:

$${V}_{Z}=-{I}_{Z}\bullet {Z}_{Z}=-\beta \bullet {I}_{X}\bullet {Z}_{Z}$$
(28)

Substituting the value of IX and VX from Eqs. (24) and (25), yields:

$${V}_{Z}=\alpha \beta {Z}_{Z}\bullet \frac{{V}_{Y1}}{\left({R}_{1}+{R}_{X}\right)}$$
(29)

Applying Kirchoff’s current law at node ‘Y1’ gives:

$${I}_{in}={\frac{{V}_{Y1}}{{Z}_{Y1}}-I}_{02+}$$
(30)

Using Eqs. (23) and (29), Iin can be expressed as:

$${I}_{in}=\frac{{V}_{Y1}}{{Z}_{Y1}}-\alpha \beta {\gamma Z}_{Z}\bullet \frac{{G}_{m2}{V}_{Y1}}{\left({R}_{1}+{R}_{X}\right)}$$
(31)

Considering source resistor (Rs), Eq. (31) can be expressed as:

$$\frac{{{V}_{in}-V}_{Y1}}{{R}_{S}}=\frac{{V}_{Y1}}{{Z}_{Y1}}-\alpha \beta {\gamma Z}_{Z}\bullet \frac{{G}_{m2}{V}_{Y1}}{\left({R}_{1}+{R}_{X}\right)}$$
(32)

Simplifying Eq. (32), VY1 can be obtained as:

$${V}_{Y1}=\frac{{Z}_{Y1}\left({R}_{1}+{R}_{X}\right)}{\left({Z}_{Y1}+{R}_{S}\right)\left({R}_{1}+{R}_{X}\right)-\alpha \beta {\gamma {G}_{m2}{R}_{S}Z}_{Z}{Z}_{Y1}}\bullet {V}_{in}$$
(33)

From Eq. (28), it can be analyzed that:

$${V}_{Z}=-\frac{{I}_{Z}}{\frac{1}{{R}_{Z}}+s\left({C}_{1}+{C}_{Z}\right)}$$
(34)

Assuming, 1/RZ<<s(C1+CZ) for the operating frequency range, Eq. (34) can be simplified as:

$${V}_{Z}\approx -\frac{{I}_{Z}}{s\left({C}_{1}+{C}_{Z}\right)}=-\frac{1}{\left({C}_{1}+{C}_{Z}\right)}{\int }_{0}^{t}{I}_{Z}dt$$
(35)

Using Eqs. (23), (24), (25), and (33), along with Eq. (5) that represents flux of meminductor as time integral of input voltage, VZ can be defined as:

$${V}_{Z}=\frac{\alpha \beta }{\left({C}_{1}+{C}_{Z}\right)\left({R}_{1}+{R}_{X}\right)}\bullet \frac{{Z}_{Y1}\left({R}_{1}+{R}_{X}\right)}{\left({Z}_{Y1}+{R}_{S}\right)\left({R}_{1}+{R}_{X}\right)-\alpha \beta {\gamma {G}_{m2}{R}_{S}Z}_{Z}{Z}_{Y1}}\phi \left(t\right)$$
(36)

Simple analysis of Fig. 18 shows that:

$${V}_{B3}={I}_{01-}\bullet \left({Z}_{0}\parallel \frac{1}{s{C}_{2}}\right)={I}_{01-}\bullet \frac{1}{\frac{1}{{R}_{0-}}+\frac{1}{{R}_{B}}+s\left({C}_{0-}+{C}_{B}+{C}_{2}\right)}$$
(37)

Assuming, \(\left(\frac{1}{{R}_{0-}}+\frac{1}{{R}_{B}}\right)\ll\) \(s\left({C}_{0-}+{C}_{B}+{C}_{2}\right)\), and substituting I01- from Eqs. (23), (37) can be simplified as:

$${V}_{B3}=-\frac{\gamma {G}_{m1}{V}_{Z}}{s\left({C}_{0-}+{C}_{B}+{C}_{2}\right)}=-\frac{\gamma {G}_{m1}}{\left({C}_{0-}+{C}_{B}+{C}_{2}\right)}{\int }_{0}^{t}{V}_{Z}$$
(38)

Substituting VZ from Eq. (36) and using flux relation given by Eqs. (1), (38) can be modified as:

$${V}_{B3}=-\frac{\gamma {G}_{m1}}{\left({C}_{0-}+{C}_{B}+{C}_{2}\right)}\frac{\alpha \beta }{\left({C}_{1}+{C}_{Z}\right)\left({R}_{1}+{R}_{X}\right)}\bullet \frac{{Z}_{Y1}\left({R}_{1}+{R}_{X}\right)}{\left({Z}_{Y1}+{R}_{S}\right)\left({R}_{1}+{R}_{X}\right)-\alpha \beta {\gamma {G}_{m2}{R}_{S}Z}_{Z}{Z}_{Y1}}\rho \left(t\right)$$
(39)

Performing routine analysis at node ‘Y1’, it can be analysed that:

$${I}_{O2+}=\frac{{\alpha \beta \gamma G}_{m2}{V}_{Y1}}{{Z}_{Z}}$$
(40)

Carrying out simple mathematical analysis on Eqs. (30) and (40), yields:

$${I}_{in}=-\gamma \frac{\alpha \beta }{\left({C}_{1}+{C}_{Z}\right)\left({R}_{1}+{R}_{X}\right)}\bullet \frac{{Z}_{Y1}\left({R}_{1}+{R}_{X}\right)}{\left({Z}_{Y1}+{R}_{S}\right)\left({R}_{1}+{R}_{X}\right)-\alpha \beta {\gamma {G}_{m2}{R}_{S}Z}_{Z}{Z}_{Y1}}{\left\{1-\frac{1}{\frac{{\alpha \beta \gamma G}_{m2}{Z}_{Y1}}{{Z}_{Z}}}\right\}G}_{m2} \phi \left(t\right)$$
(41)

Using Eq. (7), Iin and ML-1 of proposed meminductor while considering parasitics and non-idealities are expressed by Eq. (42) and (43) respectively.

$${I}_{in}=K\gamma \eta \left\{1-\frac{1}{{\delta Z}_{Y1}}\right\}\left[\frac{{\gamma \eta G}_{m1}}{{C}_{02eq}}\rho \left(t\right)+{V}_{SS}+2{V}_{th}\right] \phi \left(t\right)$$
(42)
$${M}_{L}^{-1}=K\gamma \eta \left\{1-\frac{1}{{\delta Z}_{Y1}}\right\}\left[\frac{{\gamma \eta G}_{m1}}{{C}_{02eq}}\rho \left(t\right)+{V}_{SS}+2{V}_{th}\right]$$
(43)

here,

$$\eta = \frac{{\alpha \beta }}{{\left( {C_1 + C_Z } \right)\left( {R_1 + R_X } \right)}} \cdot \frac{{Z_{Y1} \left( {R_1 + R_X } \right)}}{{\left( {Z_{Y1} + R_S } \right)\left( {R_1 + R_X } \right) - \alpha \beta \gamma G_{m2} R_S Z_Z Z_{Y1} }},\delta = \frac{{\alpha \beta \gamma G_{m2} }}{{Z_Z }},andC_{02eq} = \left( {C_{0 - } + C_B + C_2 } \right)$$
(44)

Analysis of Eqs. (42), (43), and (44) reveals that the parasitic elements, namely RX, CZ, C0, and CB, can be effectively disregarded by consolidating them with R1, C1, and C2, respectively. Additionally, assuming R0+ and RY1 to be significantly large, and CY1 and C0+ to be extremely small, enables the neglect of the minor current IZY1 in comparison to Iin. These considerations collectively contribute to the robust and practically stable behavior of the proposed meminductor.

6 Applications of proposed meminductor

In this section, to demonstrate the viability of the suggested meminductor emulator, two applications—chaotic oscillator and adaptive learning circuit—have been implemented.

6.1 Chaotic oscillator

Since the previous three decades, the chaos phenomena has been extensively explored in a variety of scientific fields, including physics, ecology, biology, optics, etc. An intriguing and straightforward tool for researching and creating chaos in electronic and communication systems is Chua's chaotic oscillator. This circuit exhibits rich dynamics, is simply built, and is tractable mathematically. These features have made Chua's oscillator a popular choice for producing chaotic signals for real-world applications, including: music, secure communications, neural networks, nonlinear waves, and visual sensing [67, 68]. This oscillator's architecture is mostly built around Chua's diode, an active three-segment nonlinear resistor. In Fig. 20, a simple fourth-order chaotic oscillator is displayed [18]. In this circuit, Chua’s diode has been replaced with the proposed meminductor emulator. The negative resistance required in the circuit has been implemented using OPAMP based negative impedance converter (NIC). The four state variables of this circuit are: voltage across capacitor C1 (VC1), voltage across capacitor C2 (VC2), current through inductor L (IL), and current through meminductor ML (IML).

Fig. 20
figure 20

A third-order Chua’s chaotic oscillator

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The state-equations representing first-order dynamics of this circuit are given as:

$${C}_{1}\frac{d{V}_{C1}}{dt}+{I}_{L}=\frac{{V}_{C1}}{{R}_{2}}; {C}_{2}\frac{d{V}_{C2}}{dt}+{I}_{ML}={I}_{L}; L\frac{d{I}_{L}}{dt}+ {I}_{L}\cdot {R}_{1}={V}_{C1}-{V}_{C2}; {M}_{L}\frac{d{I}_{ML}}{dt}={V}_{C2}$$
(45)

here C1, C2, L, ML, R1 and R2 denote the values (capacitance, inductance, meminductance or resistance) of the corresponding element. The suitable values of these component parameters have been chosen in order to obtain chaotic response across state variables of the circuit. For the chaotic circuit depicted in Fig. 20, various projection plots generated in LTspice have been plotted in Fig. 21. These plots have been observed with the parameter’s values chosen as C1 = 65nF, C2 = 10nF, L1 = 60mH, R1 = 100Ω, and R2 = -2kΩ. The required value of R2 has been obtained with Ra = 2kΩ and Rb = 2kΩ. Here, ML has been replaced by proposed MDVCCTA based meminductor.

Fig. 21
figure 21

Projection plots of chaotic oscillator observed between space variables (a) IL & VC1 (b) IML & VC1 (c) VC2 & VC1 (d) VC2 & IL

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6.2 Adaptive learning circuit

The neuromorphic circuit using proposed meminductor emulator is presented in Fig. 22. The meminductors are found to be more suitable for neuromorphic applications as compared to memristors [69]. The proposed meminductor emulator circuit has been used in adaptive learning circuit to demonstrate how it adjusts its meminductance to achieve the appropriate resonance frequency of the circuit according to the applied input voltage (Vin). The response of the circuit mimics the behaviour of amoeba that is one of the simplest creatures on earth having brain-like behaviours in terms of controlling their actions based on the past events. The amoeba's locomotive speed is influenced by its surrounding temperature. Amoeba reduces its locomotive speed when temperature falls. The adaptive learning circuit shown in Fig. 22 behaves the similar way. The input pulse (Vin) represents the surrounding temperature, and the output voltage (Vout) represents the locomotive speed of amoeba. The amplitude of output voltage (amoeba’s locomotive speed) gets reduced when the input voltage (temperature) drops. The pattern of input voltage follows the three cases: drops in voltage (reduced temperature), rise in voltage (increased temperature), and the constant voltage (no change in temperature) as shown in Fig. 23. Initially, voltage is maintained constant, and it gets reduced after some time to a particular level. Thereafter, the voltage is increased to achieve the same level from where it started. The same process is repeated thrice initially and thereafter maintains the constant voltage for a specific time and again follows the same pattern for one period. This pattern is applied to provide all scenarios that amoeba faces in terms of temperature. The amoeba locomotive speed gets reduced, increased, and maintained constant for reduction, increment, and constant temperature, respectively. In the similar way, the output response (Vout) of the circuit closely follows the behaviour of input pulse due to inherent ability of remembrance of meminductor as can be seen from Fig. 23. Therefore, the adaptive learning circuit is made to anticipate the amoeba's behaviour in response to changes temperature in the environment. Three steps can be used to define the amoeba's learning process: storage of previous occurrences, future forecasting, and comprehension of the timing of recurrent events [70, 71]. An element with memory retention capabilities can be employed to simulate an adaptive learning circuit with amoeba-like behavioural responses. Therefore, the proposed meminductor emulator circuit is employed to realize an adaptive learning circuit. This circuit is implemented with the help of a resistor (R), a capacitor (C), and the suggested meminductor (ML).

Fig. 22
figure 22

Electrical model of adaptive learning circuit using proposed meminductor

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Fig. 23
figure 23

Locomotive response against temperature fluctuations as seen by adaptive learning circuit of Fig. 22

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7 Conclusion

The possibility of designing a single active block-based floating meminductor has been explored. The modified differential voltage current conveyor transconductance amplifier has been chosen due to its simple structure along with differential and in-built tuning features. The proposed circuit's appropriate operation has been confirmed by looking at the essential meminductor fingerprints, pinched hysteresis loops with zero-crossing and non-volatility tests. Through a simple switch connected at the input terminals, it has been demonstrated that the suggested circuit can operate in both incremental and decremental modes. The simulation results obtained in LTspice show the workability of the proposed circuit till 80 MHz while consuming 3.82mW power. The pinched hysteresis loops observed with temperature variations from −55 °C to + 125 °C, variations in resistance from 10 to 30kΩ, and ± 10% variations in supply voltage confirm the suitability of the proposed circuit in a practical environment. Additionally, Monte Carlo and corner analyses demonstrate the suggested meminductor's robustness. Furthermore, the successful design of a chaotic oscillator and an adaptive learning circuit utilizing the suggested meminductor has been illustrated.