1 Introduction

Resistors, inductors, and capacitors are the three basic components of electrical engineering. These components have been known for a long time, however, the other three, memristor, memcapacitor, and meminductor, have only recently come to light since last decade. These elements are generally known as mem-elements. Memristors, meminductors, and memcapacitors are therefore thought of as resistors, inductors, and capacitors with memories, respectively. Memristor was introduced by Prof. Leon Chua long back [1] but the device gained popularity after its physical realization in Hewlett-Packard Lab [2]. Memristor offers unique properties that can be utilized in different domains of electrical, electronics, and computer engineering. It is widely used in many areas of engineering and finds numerous fascinating applications [3,4,5,6,7,8]. Memristor has the capability to drive the various fields of engineering and is now accessible as an off-the-shelf component. But, still, there is a scope for the betterment of performance, and practicing engineers are continuously giving feedback about its pros and cons. Therefore, several circuits of emulators have also been developed to mimic the properties of memristors [9,10,11,12,13,14]. A vast amount of research has been done around memristors and the device is now seen as the element of the new era. After a successful journey of more than a decade, researchers are now exploring the extensive applications of other two mem-elements namely memcapacitor and meminductor. Memcapacitors and meminductors are not accessible as off-the-shelf components that paved the way for the designing of various emulator circuits. The realizations of meminductor emulators are quite challenging than memristors and memcapacitors.

In literature, the realizations of meminductor and memcapacitor emulators have been done by employing different prominent analog building blocks namely operational amplifiers (OP-AMPs), second-generation current conveyors (CCIIs), operational transconductance amplifiers (OTAs), current feedback operational amplifiers (CFOAs), current backward transconductance amplifier (CBTA), current differencing transconductance amplifier (CDTA), voltage differencing transconductance amplifier (VDTA), voltage differencing current conveyor (VDCC) and etc. In 2010, the first realization of the meminductor emulator employing OP-AMP, memristor, resistor, and the capacitor was claimed [15]. In the next paper, the mutator circuit that can convert the memristor into a meminductor and memcapacitor has been recommended [16]. It highlights the fact that the implementations of meminductors and memcapacitors are not easily possible as is the case of memristors. Subsequently, emulator circuits for both meminductor and memcapacitor have been suggested using CCIIs, memristor, capacitor, and inductor. To create the memcapacitor emulator from the meminductor emulator, the locations of the resistor, capacitor, and memristor are changed with the memristor, inductor, and resistor, correspondingly [17]. A meminductor emulator employing two CCIIs, one memristor, one capacitor, and one resistor was reported [18]. Four CCIIs, an adder, a multiplier, a buffer, a lossy integrator, a capacitor, and a lossy integrator have been used to design a memristor-less meminductor emulator [19]. With the help of an inductor, a multiplier, three OP-AMP, a number of MOSFETs, and two capacitors, a meminductor emulator controlled through charge was created [20]. Next, a meminductor emulator having both current-controlled and voltage-controlled features has been designed employing three CCIIs, a multiplier, an adder, three resistors, and two capacitors [21]. Subsequently, the memristor emulator circuit was coupled with a mutator circuit to realize a meminductor emulator. The mutator circuit was designed employing two CCIIs, a buffer, and two passive components whereas the memristor emulator was designed using inverting amplifiers, a buffer, a multiplier, and a few passive components [22]. Another meminductor emulator based on the mutation concept employing a mutator and a memristor emulator was published in [23]. A CCII+, a capacitor, three OP-AMPs, and resistors were used to design the mutator, and the same memristor emulator as described in [22] was also used. The performance of the meminductor circuits was proved by realizing parallel and hybrid connections of meminductor emulators [23]. Three CFOAs, a memristor emulator, a few resistors, and capacitors have been employed in designing a universal mutator [24]. Memristor-to-meminductor conversion has been described for an OP-AMP-based gyrator circuit [25]. Mutator-based meminductor emulator has been reported using four AD844s, one op-amp, a varactor diode, several resistors, and a capacitor [26]. Grounded/floating meminductor circuits having both grounded and floating characteristics were realized by employing CCIIs, analog multipliers, several resistors, and capacitors [27]. A CBTA, memristor, and capacitor have been employed in the reported mutator circuit for meminductor and memcapacitor designs. To convert the arrangement of the memcapacitor to the meminductor, the memristor, and capacitor's respective locations have been switched [28]. After altering the Riordan gyrator's circuit, a floating meminductor emulator has been described [29]. Two VDTAs and two capacitors are used in a fully floating meminductor emulator circuit that has been published [30]. The operation of another grounded emulator using VDTA, OTA, and two capacitors was described in [31]. Three OTAs and two capacitors have been used to create an OTA-based grounded meminductor emulator [32]. It has been stated that a different memcapacitor and meminductor emulator uses multi-output OTA and a few passive components [33]. Two CCIIs, one OTA, two resistors, and two capacitors have been employed to implement a flux-controlled meminductor circuit [34]. Six different meminductor circuits have been realized using two OP-AMPs, a memristor, a few resistors, and a capacitor [35]. A memristor, a capacitor, and one VDCC are used in another meminductor/memcapacitor circuit that has been published. To create meminductor and memcapacitor emulators, the memristor and capacitor positions have been switched [36]. It has been stated that a grounded capacitor, current differencing buffered amplifier (CDBA), and VDTA can be used to emulate a memristor-less meminductor [37]. A different memristor-less meminductor emulator employing OTA and CDBA was reported in [38]. The next paper describes a memristor, resistors, and capacitors-based operational amplifier-based meminductor emulator [39]. A meminductor emulator based on OTA and CDTA was reported in [40], whereas a meminductor emulator based on voltage differencing buffered amplifier (VDBA) and CDBA was implemented in [41]. Then, in order to create the meminductor emulator, a voltage differencing gain amplifier (VDGA) and a CDBA were utilized [42]. An adaptive learning circuit has also been realized to show the workability of proposed meminductor emulator. Then, using two OTAs and two grounded capacitors, the meminductor emulator was created [43]. Another meminductor emulator has been proposed in [44] and uses a current follower (CF), a voltage differencing inverted buffered amplifier (VDIBA), a parasitic resistance, and two capacitors. In [45], a meminductor emulator having a single active building block based on a modified voltage differencing voltage transconductance amplifier (MVDVTA) was described. In [46], a CCII-based meminductor emulator has been reported. A VDTA and current-conveyor (CC) based meminductor emulator was implemented in [47].

According to the literature on meminductor emulators, there are two common methods for designing meminductor emulator circuits. In the first approach, a mutator circuit is designed which converts memristor emulator circuits into meminductor and memcapacitor emulators. The second approach aims at memristor-less designs of the meminductor emulators. This paper attempts to highlight the meminductor design using a new approach. The methodology followed in this paper utilizes the concept of converting an active inductor circuit into a meminductor emulator by storing the charge flowing through the circuit in a capacitor. The idea is very similar to the thought of putting memory in an active inductor circuit [48]. While exploring the meminductor emulator circuits described in the literature, it has been witnessed that the majority of them either require the use of complex active blocks that are not readily obtainable as off-the-shelf components, or they demand the use of complex components such as memristors, multipliers, integrators, and adders. The motivation for the work done in this paper is to realize a simple meminductor employing active blocks that can be readily designed using off-the-shelf components available in the market. Additionally, no complex components must be required in its design. In the paper, following the new approach, the meminductor emulator has been designed in which an active inductor circuit formed by OTA and CCII is changed into a meminductor emulator circuit by storing its charge using a capacitor connected to one of the terminals of CDBA. This suggested emulator is free from the need of any complex components and all the employed blocks can be easily designed from the ICs commercially available in the market.

The paper is presented in eight different sections, which include the current introductory section. A basic review of the mem-elements is presented in Sect. 2. The features of the analog building blocks utilized in the suggested circuit architecture are illustrated in Sect. 3. Section 4 gives a thorough discussion of the proposed decremental/incremental grounded meminductor as well as a mathematical analysis of it. In Sect. 5, the simulation results are presented for the proposed meminductor emulator using the LTspice tool. The comparison summary of the suggested emulator circuit with the emulator circuits available in the literature is presented in Sect. 6. Section 7 shows how the suggested emulator is employed to realize a chaotic oscillator.

2 Basic Reviews of Mem-Elements

The mem-elements (memristor, memcapacitor, and mem-inductor) are viewed as conventional circuit elements (resistor, capacitor, and inductor) having memory. After incorporating memory in conventional circuit elements, very interesting results have been obtained that are utilized in several ways in circuit theory during the past decade. In this section, mem-elements are reviewed in order to give a clear understanding of the topic. The two important properties of mem-elements are the presence of memories and the capability of remembering past events. Thus, in order to confirm the behaviour of a device as a mem-element, the formation of pinched hysteresis loops is very important. Pinched hysteresis loops are obtained between voltage and current for the memristor. It is attained between charge and voltage for the memcapacitor whereas for the meminductor, it is obtained between flux and current. Another important testimonial for mem-elements is their state-retaining capability which is verified through the non-volatility test.

The various constitutive relations that correlate the mem-elements are formed with the help of current i, charge q, voltage v, and flux φ. The following relationship describes how a memristor (MR) functions:

$$ d\phi = M_{R} dq $$
(1)

that can be expressed as:

$$ V\left( t \right) = M_{R} I\left( t \right) $$
(2)

where V(t) is the potential across memristor MR and I(t) represents the current flowing through the memristor.

Memcapacitor (MC) relationship of charge q(t) and corresponding voltage V(t) is given by:

$$ q\left( t \right) = M_{c} V\left( t \right) $$
(3)

Meminductance (ML) is governed by the relationship of flux φ(t) and current I(t) flowing through it and is given as:

$$ \phi \left( t \right) = M_{L} I\left( t \right) $$
(4)

The interrelationships of these mem-elements are shown schematically in Fig. 1. The two new variables ρ and σ are time integrals of flux (φ) and charge (q) and are given by the following relations:

$$ \rho = \int\limits_{ - \infty }^{t} {\phi (\tau )} d\tau $$
(5)
$$ \sigma = \int\limits_{ - \infty }^{t} {q(\tau )} d\tau $$
(6)
Fig. 1
figure 1

Interrelation of mem-elements

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3 Analog Active Building Blocks (ABBs) Used in the Work

There are numerous analog active building blocks (ABBs) that are prominently employed for the development of emulator circuits. In this paper, operational transconductance amplifier (OTA), second generation current conveyor (CCII), and current differencing buffered amplifier (CDBA) have been used to present the meminductor emulator circuits. Figs. 2 and 3 show the symbolic representation of OTA and its circuit diagram respectively. An OTA acts as a current source controlled by a voltage that gives an output current (I0) when a differential voltage (VP - VN) is applied. The equation of I0 is expressed as:

$$ I_{o} = g_{m} (V_{p} - V_{n} ) $$
(7)

where gm is the transconductance gain and is directed by a bias voltage (VB) as depicted in Eq. (8).

$${g}_{m}=\frac{k}{\sqrt{2}}\left({V}_{B}-{V}_{SS}-2{V}_{th}\right)$$
(8)

where k is μnCoxW/L and depends on a particular technology.

Fig. 2
figure 2

Symbolic representation of OTA

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Fig. 3
figure 3

Complete OTA circuit

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The current conveyor (CC) is a dominating block of the analog family. It can convey the input current at the different terminals of CCII. The characteristic equation of the second-generation current conveyor of negative type (CCII-) is given in Eq. (9).

$$ I_{Y} = 0,V_{x} = V_{y} ,I_{z} = - I_{x} $$
(9)

The symbolic representation of CCII- and its circuit diagram are presented in Figs. 4 and 5 respectively.

Fig. 4
figure 4

Symbol of CCII-

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Fig. 5
figure 5

Circuit diagram of CCII-

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$${V}_{p}={V}_{N}=0,{I}_{z}={I}_{p}-{I}_{n},{V}_{W}={V}_{Z}$$
(10)

4 Proposed decremental/incremental grounded meminductor emulator

The proposed meminductor emulator is shown in Fig. 8. An active inductor is formed with the help of OTA, CCII-, resistor R, and capacitor C1. The active inductor circuit is converted into a meminductor emulator circuit by storing the charge proportional to input current (Iin) in capacitor C2 that works as a memory element and the voltage developed across the capacitor (C2) has been utilized to change the transconductance (gm) gain of the OTA. The voltage (Vz) developed across the capacitor (C2) is equal to the voltage (Vw). The “W” terminal of CDBA is connected to the controlling terminal (VB) of OTA that controls the transconductance (gm). Transconductance (gm) affects the input current and thus the meminductance of the circuit is controlled by the previous charge stored across capacitor C2. The output current (Io) of OTA charges the capacitor (C1) and the voltage across the capacitor (C1) is “Vy” that is copied to the terminal “Vx” following the property of CCII-. The voltage “Vx” produces the current “Ix” in the resistor (R). The current “Iz” is equal to the current “Ix”. The current (Iz) is determined by the voltage (Vx) that is indirectly dependent on the value of the input current (Iin). The input current (Iin) gets changed according to the previous charge stored across the capacitor (C2). The circuit is having memory and from the input side, it realizes an active inductor. Thus, the proposed circuit behaves as a meminductor. The responses for both decremental and incremental meminductor emulators can be obtained by connecting the “z” terminal of CCII- to “P” and “N” terminals of CDBA, respectively.

The routine analysis of the circuit (Fig. 8) yields the following equations:

Current differencing buffered amplifier (CDBA) is another important ABB used for the realization of current-node circuits. The symbolic representation and circuit diagram of CDBA are depicted in Figs. 6 and 7 respectively. Ip and In represent the two input currents of CDBA. Their difference flows through a high impedance terminal "Z", and equal voltages are obtained at the "W" and "Z" terminals by the internal buffers of CDBA. The characteristic equation of CDBA is expressed as:

$$ I_{o} = g_{m} V_{in} $$
(11)
$${V}_{y}=\frac{1}{{C}_{1}}\int {I}_{o}dt=\frac{1}{{C}_{1}}\int {g}_{m}{V}_{in}dt$$
(12)

where as \(\int {\mathrm{V}}_{\mathrm{in}}\mathrm{dt}=\) \({\mathrm{\varphi }}_{\mathrm{in}}(\mathrm{t})\), Therefore, Eq. (12) can be written as

Fig. 6
figure 6

Symbolic notation of CDBA

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Fig. 7
figure 7

Circuit diagram of CDBA

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$${V}_{y}=\frac{{g}_{m}}{{C}_{1}}{\varphi }_{in}(t)$$
(13)

Terminal “Z-” of CCII- has to be coupled to the “P” or “N” terminal of CDBA for making the meminductor emulator decremental or incremental respectively. When the “Z-” terminal is connected to the “P” terminal, current Iz1 through capacitor C2 connected at the “Z1” terminal of CDBA is given as:

$${I}_{Z1}={I}_{P}={I}_{in}-{I}_{z-}$$
(14)

Therefore, the voltage “Vz1” across capacitor C2 is written as:

$$ V_{Z1} = \frac{1}{{C_{2} }}\int {I_{Z1} } dt = \frac{1}{{C_{2} }}\int {(I_{in} - I_{z - } } )dt $$
(15)

The current “Iz-” at output terminal “Z-” of CCII- is written as:

$$ I_{z - } = \frac{{V_{x} }}{R} = \frac{{V_{y} }}{R} $$
(16)

Replacing Vy in Eq. (13) with the help of Eq. (16), we get

$${I}_{z-}=\frac{{g}_{m}}{R{C}_{1}}{\varphi }_{in}(t)$$
(17)

Using current “Iz-” from Eq. (17) and substituting into Eq. (15), we get:

$${V}_{Z1}=\frac{1}{{C}_{2}}\int {I}_{Z1}dt=\frac{1}{{C}_{2}}\int \left({I}_{in}-\frac{{g}_{m}}{R{C}_{1}}{\varphi }_{in}(t)\right)dt$$
(18)

where \(\int {\mathrm{\varphi }}_{\mathrm{in}}\mathrm{dt}=\) \(\uprho (\mathrm{t})\) and \(\int {\mathrm{I}}_{\mathrm{in}}\mathrm{dt}=\) \(\mathrm{q}(\mathrm{t})\).

Thus, the Eq. (18) can be rewritten as:

$$ V_{Z1} = \frac{q(t)}{{C_{2} }} - \frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) $$
(19)

The voltage “Vw” of CDBA is equal to voltage “Vz” and “W” terminal is connected to controlling voltage “VB”. Thus, we can writec the following equation as:

$$ V_{B} = V_{W} = V_{Z1} = \frac{q(t)}{{C_{2} }} - \frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) $$
(20)

Putting “VB” from Eq. (20) to Eq. (8) results in:

$$ g_{m} = \frac{k}{\sqrt 2 }\left[ {\frac{q(t)}{{C_{2} }} - \frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) - V_{SS} - 2V_{th} } \right] $$
(21)

Replacing the transconductance (gm) in Eq. (17) with the value of gm expressed in Eq. (21) gives:

$$ I_{z - } = \frac{k}{{\sqrt 2 RC_{1} }}\left[ {\frac{q(t)}{{C_{2} }} - \frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) - V_{SS} - 2V_{th} } \right]\varphi_{in} (t) $$
(22)

Current I (t), meminductance (ML), and flux Φ (t) are related in the following way:

$$ \phi \left( t \right) = M_{L} I\left( t \right) $$
(23)

Rearranging the equation (23) results in:

$$ I\left( t \right) = M_{L}^{ - 1} \phi \left( t \right) $$
(24)

After comparing Eq. (22) and Eq. (24) we get:

$$ M_{L}^{ - 1} = \frac{k}{{\sqrt 2 RC_{1} }}\left[ {\frac{q(t)}{{C_{2} }} - \frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) - V_{SS} - 2V_{th} } \right] $$
(25)

The Eq. (25) can be rearranged as:

$$ \begin{aligned} M_{L}^{ - 1} & = - \frac{k}{{\sqrt 2 RC_{1} }}(V_{SS} + 2V_{th} ) - \frac{k}{{\sqrt 2 RC_{1} }}\left[ {\frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) - \frac{q(t)}{{C_{2} }}} \right] \\ & \quad \leftarrow {\text{Fixed term}} \to \quad \quad \leftarrow {\text{Variable term}} \to \\ \end{aligned} $$
(26)

If the terminal “Z-” of CCII- is interchanged from “P” terminal to “N” terminal of CDBA, Eq. (26) modifies to

$$ \begin{aligned} M_{L}^{ - 1} & = \frac{k}{{\sqrt 2 RC_{1} }}(V_{SS} + 2V_{th} ) + \frac{k}{{\sqrt 2 RC_{1} }}\left[ {\frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) - \frac{q(t)}{{C_{2} }}} \right] \\ & \quad \leftarrow {\text{Fixed term}} \to \quad \quad \leftarrow {\text{Variable term}} \to \\ \end{aligned}$$
(27)

Equations (26) and (27) can be merged into single equation (28) in which “+” sign correspond to inverse meminductance of incremental meminductor emulator whereas “-” sign indicates the inverse meminductance of decremental meminductor emulator.

$$ \begin{aligned} M_{L}^{ - 1} & = \pm \frac{k}{{\sqrt 2 RC_{1} }}(V_{SS} + 2V_{th} ) \pm \frac{k}{{\sqrt 2 RC_{1} }}\left[ {\frac{{g_{m} }}{{RC_{1} C_{2} }}\rho (t) - \frac{q(t)}{{C_{2} }}} \right] \\ & \quad \leftarrow {\text{Fixed term}} \to \quad \quad \quad \leftarrow {\text{Variable term}} \to \\ \end{aligned}$$
(28)

5 Simulation Results and Discussions

The suggested meminductor circuit has been modelled with 0.18 μm CMOS parameters using the LTspice simulation tool. Table 1 lists the feature size of the MOSFETs utilized in the implementation of OTA, CCII-, and CDBA. The passive elements values utilized in the suggested meminductor emulator's design are R1 = 1 kΩ, C1 = C2 = 40 pF. The supply voltage is chosen as VDD = − VSS = 0.9V.

Table 1 Feature Size of MOSFETs employed in OTA, CCII- and CDBA
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Fig. 8
figure 8

Proposed decremental/incremental meminductor emulator

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5.1 Meminductive Behaviour

One of the important testimonials of the meminductor is the appearance of a pinched hysteresis loop (PHL) when a bipolar signal is applied. The PHL is observed when the characteristic of the meminductor is plotted on the current (i) versus. flux (φ) plane. To investigate the proposed meminductor behaviour, a sinusoidal signal having 100mV amplitude is applied at its input terminals. The obtained curves for frequency range varying from 100 Hz – 1 MHz have been shown in Fig. 9a–f. These curves show dumb-bell-shaped PHL curves with zero-crossing, verifying the first testimonial of the meminductor. Furthermore, it can be observed from the curves of Fig. 9 that the area enclosed by the lobes reduces with an increase in frequency. This is another important testimonial of a meminductor. The curves depicted in Fig. 9 are plotted when the meminductor is operated in incremental configuration, which is obtained when the “Z-” terminal of CCII- is connected to the “N” terminal of CDBA. The PHL loops for the decremental meminductor design are drawn in Figs. 10a–f. To plot all these curves, the positive terminal of OTA is excited with a 100mV sinusoidal signal. These curves depict that the circuit operates in a decremental configuration from 100 Hz to 1 MHz, further verifying its satisfactory operation for a wide frequency range.

Fig. 9
figure 9

Pinched hysteresis loops observed for proposed incremental meminductor emulator

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Fig. 10
figure 10

PHLs observed for proposed decremental meminductor emulator

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Similar to an inductor, the voltage signal of a meminductor has phase lead in comparison to current and flux signals. To verify this property in the suggested emulator, its transient response has been observed for a 1 kHz sinusoidal signal of 100 mV amplitude. The waveform observed for input voltage (Vin) along with flux and current waveforms are drawn in Fig. 11. The phase lag of current and flux signals compared to the input voltage signal is confirmed by the analysis of this figure. Thereby, justifying the meminductive behaviour of the proposed design.

Fig. 11
figure 11

Transient response of proposed meminductor emulator

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It is expected from a mem-element to remember its current state. This memory characteristic of any mem-element is verified by observing its response to a pulse signal. The mem-element retains the current state during the OFF period of the pulse, while it changes the state during the ON period of the pulse. This is known as a non-volatility test for the mem-inductor. For the proposed incremental meminductor emulator non-volatility test is performed by applying a pulse signal of 100 mV amplitude and “ON” time of 50 ns whereas the total time period is 1000 ns. The output obtained is shown in Fig. 12, which indicates that the proposed meminductor emulator successfully verifies the non-volatility test as it remembers the previous value of meminductance and starts increasing for the next “ON” period.

Fig. 12
figure 12

Non-volatility test of proposed meminductor emulator

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5.2 Capacitive Tuning

The variations in the PHL response of the meminductor with different values of capacitance is a desired feature for the applications that offer capacitive tuning. To investigate the impact of variations in capacitor values, the proposed meminductor is simulated with a sinusoidal signal of 100 mV and 1 kHz. The PHL curves observed for C2 varying from 30pF to 50pF in equal steps of 5pF have been plotted in Fig. 13. The slight variations in the PHL curves confirm the capacitive tuning feature of the suggested meminductor emulator.

Fig. 13
figure 13

PHL curves of proposed meminductor emulator with C2 varying from 30pF to 50pF in equal steps of 5pF

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5.3 Performance and Tolerance Analysis

Practically a device will be subjected to environmental factors leading to changes in its behaviour. To testify the performance and tolerance of the proposed meminductor emulator while facing environmental variations, its response with changes in temperature and supply voltage has been investigated. For these analyses a 1kHz sinusoidal signal of 100mV amplitude is applied at the input terminal of the suggested circuit. Fig. 14 plots the variations observed in PHL curves when the temperature is varied from − 100 °C to 100 °C. These curves follow meminductive behaviour showing zero-crossing dumb bell-shaped PHL curves. However, slight variations in the shape are observed with changes in temperature. The PHL responses observed for variations in supply voltage have been shown in Fig. 15. These plots have been obtained for supply voltage varying from ±0.8V to ±1V.

Fig. 14
figure 14

PHL curves of proposed meminductor emulator with different temperature values: − 5100 °C, − 50 °C, 0 °C, 27 °C, 50 °C, and 100 °C

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Fig. 15
figure 15

PHL curves of proposed meminductor emulator with different supply voltages: i ± 0.8V, ii ± 0.85V, iii ± 0.9V, iv ± 0.95V, and v ± 0.1V

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The simulation results shown in Fig. 9, 10, 11, 12, 13 have been plotted considering the specified aspect ratios given in Table 1. However, any fabrication process is bound to have certain uncertainties. The impact of these uncertainties can be examined with the help of corner analysis. There are 4 corners (i) fast-fast (FF), (ii) fast-slow (FS), (iii) slow-fast (SF), and (iv) slow-slow (SS). These 4 corners act as the complete workspace for the circuit as after being fabricated the characteristics of the circuit are limited by these 4 corners. The suggested circuit's corner analysis has been performed, and the findings are displayed in Fig. 16. From this figure it is perceived that PHL loops are formed with zero-crossing for all 4 corners, confirming the workability of the proposed emulator in complete design space. Here also similar to previous cases PHL curves for different corners are obtained with slight variations in the shape.

Fig. 16
figure 16

PHL curves of proposed meminductor emulator with corner analysis: i FF, ii FS, iii SF, and iv SS

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Figures 14, 15, and 16 testify the robust nature of the suggested meminductor design with variations in environmental and fabrication factors.

6 Comparative Summary of the Proposed Meminductor Emulator with Meminductor Emulators of Literature

In Table 2, the suggested meminductor emulator's performance has been contrasted with that of meminductor emulators currently in use. The following observations have been pointed out:

  1. 1.

    The suggested meminductor design does not employ memristor while the meminductor emulators reported in [15, 17, 18, 23, 24, 28, 29, 35, 36] use memristor in their design.

  2. 2.

    The realized emulator circuit is very simple while the meminductor emulator reported in [20, 22, 24, 27] uses an analog multiplier and several other components that make the design very complex.

  3. 3.

    The meminductor emulator realizations reported in [15, 23, 27,28,29] are simple but have restricted frequency range limited to a few Hz or kHz frequencies while the meminductor proposed in this work to satisfaction up to 3 MHz frequency.

  4. 4.

    The frequency of operation of other meminductor emulators reported recently in [30, 31, 35] is also comparable to the frequency of operation of the proposed emulator.

Table 2 Comparison of proposed meminductor model with existing meminductor model
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7 Chaotic Oscillator using Proposed Meminductor Emulator

The proposed grounded meminductor design is employed in the design of a chaotic oscillator. The chaotic oscillator is a non-periodic oscillator that exhibits classic chaotic behavior. Chua’s circuit is considered to be the simplest electronic circuit that produces chaos. A 4th-order canonical Chua’s oscillator is shown in Fig. 17. In this circuit, the non-linear device (ML) has been implemented by the suggested meminductor emulator. The values of passive components chosen for SPICE simulations are capacitor C1 = C2 = 50pF and inductor L = 25 μH. A negative impedance converter (NIC) has been designed with resistance values Ra = 15 Ω and Rb = 5 Ω. The chaotic oscillator’s 2-D projection plots are shown in Fig. 18.

Fig. 17
figure 17

Chaotic oscillator employing proposed meminductor emulator

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Fig. 18
figure 18

The chaotic oscillator’s 2D projection plots a Vx−Vy b Vx−IL c Vy−IML

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8 Conclusions

This paper presents a new approach to the realization of a meminductor emulator circuit. Using this approach, active inductor circuits can be easily converted into meminductor emulator circuits. This approach is the generalized one and many new circuits of meminductor emulators can be realized using it. Following this approach, an active inductor circuit consisting of an OTA, CCII, resistor, and a capacitor has been transformed into a meminductor emulator circuit using one additional block namely CDBA, and an extra grounded capacitor. The important fingerprints: pinched hysteresis loops and non-volatility tests, confirm the functioning of the proposed emulator as a meminductor emulator. PHL curves have been obtained for both decremental and incremental meminductor emulators for a wide range of frequencies. Additionally, corner analysis and study of the suggested emulator with different environmental parameters indicate its robustness. The proposed meminductor emulator has been used to realize a chaotic oscillator that verifies the workability of the emulator as well as the proposed approach of conversion.