1 Introduction

Quantum-dot Cellular Automata is a technology for presenting data and performing calculations based on the quantum property of charged particles and follows the principle of electrostatic interaction (Lent et al. 1993a). Increasing the density of circuits in QCA technology will be several times higher than conventional CMOS circuits, and the high switching speed and low power consumption have led to this technology being at the forefront of research (Salimzadeh and Heikalabad 2019; Heikalabad 2015). So far, many circuits have been designed based on QCA, and various implementations have been proposed in the construction of QCA cellular structures and their performance has been studied.

Full adder has been widely used as one of the basic components in computing circuits (Barughi and Heikalabad 2017; Ahmadpour et al. 2019; Heikalabad 2018; Shalamzari et al. 2020; Fouad and Radwan 2019; Mousavi et al. 2020; Mosleh 2019; Ahmadpour and Mosleh 2019; Babaie et al. 2019; Asadi et al. 2020). Designing an optimal full adder circuit will have a significant impact on computational circuits (Salimzadeh and Heikalabad 2019; Mohammadi and Mohammadi 2014). Therefore, in this paper, a new and efficient design for the three-input XNOR circuit is presented in order to realize the implementation of the optimal structure for the full adder circuit in QCA technology.

Other sections are organized as follows: An overview of the basic topics related to QCA and related work is presented in Sect. 2. In Sect. 3, a new structure for full adder is introduced by proposing a unique QCA-based XNOR gate. Section 4 simulates the presented structures and investigates their operations. Summarizing the results and proposing future work are described in Sect. 5.

2 Background and related work

In this section, we introduce the basic components and widely used gates in QCA. Next, we review XOR gate and full adder structures presented in previous work.

One of the important features that distinguish QCA from other technologies is the method of applying logic 0 and 1. QCA uses a quantum state of the cell to display these values. A binary QCA cell is a set of four dots where electrons can be stored. These dots are located side by side in a square-like structure. The QCA cell has two additional electrons, which can move freely between the dots. In QCA technology, cells are responsible for communicating and transmitting binary values ​​between circuit components. In this technology, when a polarized cell is placed next to another cell in a line, the force between them causes the second cell to be in the same state as the first cell to minimize electrostatic energy in the cell configuration (Lent et al. 1993a; Lent et al. b; Norouzi et al. 2020; Mohammadi and Eshghi 2008; Norouzi and Heikalabad 2019; Heikalabad and Kamrani 2019; Salimzadeh et al. 2020).

There are two stable and possible arrangements in a cell, which are introduced as cell polarizations P = − 1 and P = + 1. The binary values ​​"0” and “1” are mapped to polarizations − 1 and + 1, respectively (Lent et al. 1993a; Ahmadpour et al. 2020a; Sadoghifar and Heikalabad 2018; Teodósio and Sousa 2007).

Wire is one of the most important elements needed to design circuits in QCA technology. It can be easily made by placing cells in a linear arrangement (Hosseinzadeh et al. 2018; Karkaj and Heikalabad 2017a; Heikalabad and Gadim 2018; Heikalabad and Heikalabad 2021; Kamrani and Heikalabad 2020; Afrooz and Navimipour 2017; Fam and Navimipour 2019; Ahmadpour et al. 2021; Rad and Heikalabad 2017).

Like other technologies, the first widely used gate in QCA is the inverter gate. The function of this gate is easily obtained by diagonally placing a cell to the previous cell (Salimzadeh and Heikalabad 2019; Karkaj and Heikalabad 2017b; Heikalabad et al. 2016; Asfestani and Heikalabad 2017; Abbasizadeh and Mosleh 2020; Ahmadpour and Mosleh 2020; Rahmani et al. 2021).

The majority gate, as a widely used gate, has three inputs and one output. In this gate, the polarization of the output cell is determined by the status of the majority of inputs. Its logical function is as Eq. (1). Using the majority gate, AND and OR gates can be designed. If one of the inputs is fixed and its value is “− 1” or “+ 1”, the two-input AND gate or OR gate is constructed, respectively (Salimzadeh end Heikalabad 2019; Ahmadpour et al. 2020b; Chaharlang et al. 2020; Heikalabad 2016; Raj et al. 2020; Majeed 2020).

$${\mathrm{Maj}}({\mathrm{A}},{\mathrm{B}},{\mathrm{C}}) = {\mathrm{AB}} + {\mathrm{BC}} + {\mathrm{AC}}$$
(1)

The full adder as the basic component in the design of computational circuits has attracted the attention of researchers, so that several different structures have been proposed for it (Salimzadeh and Heikalabad 2019; Barughi and Heikalabad 2017; Ahmadpour et al. 2018, 2019; Heikalabad 2018, 2020; Norouzi et al. 2020; Gadim and Navimipour 2018; Hasani et al. 2021).

Safoev and Jeon (2020) have proposed a new structure for the three-input XOR gate in the form of a unique QCA gate. They then used this XOR gate to design a single-bit full adder. The full adder is single-layer.

Ahmadpour et al. (2018) have proposed a new three-input XOR gate based on interactions among cells. They then used that to design a single-bit full adder. The full adder is single-layer.

3 Proposed structures

In this section, first a new structure for the three-input XNOR gate is presented as a unique gate in QCA, and then a new structure is presented using the proposed XNOR gate for the full adder.

3.1 QCA XNOR

The XNOR Gate is one of the most widely used gates in designing logical structures. The operation of the XNOR gate is to act as an even-count gate. This means that if the even number of inputs has a value of 1, the output is equal to 1. The logical function of three-input XNOR is as Eq. (2).

$${\mathrm{XNOR}} = \left({\mathrm{A}} \oplus {\mathrm{B}} \oplus {\mathrm{C}}\right)^{\prime}$$
(2)

In order to design this structure, a unique gate has been provided based on cellular interaction. Inputs A, B, and C enter the circuit simultaneously in the clock zone 0. Finally, in order to obtain the XNOR output, the output of this gate is created in the clock zone 1. The proposed cellular structure for XNOR, which can be seen in Fig. 1, has been implemented with 9 quantum cells. All the cells used in its design are 90° cell type. This structure is implemented as a single layer and the whole operation related to output production took 0.5 clock zones.

Fig. 1
figure 1

Cellular design of proposed XNOR gate

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3.2 QCA full adder

Full adder, as one of the basic components in computing, is an important structure in QCA. A full adder is a combination circuit that performs a three-bit arithmetic sum. The circuit has three inputs called A, B and C and two outputs called Sum and Carry.

Table 1 shows the truth table to design a new full adder with 3 inputs A, B and C and two outputs Sum and Carry. The input A is most significant bit of full adder, and the third input C is the carry obtained from the previous less valuable location. The Sum output achieves a lower value of the sum, and the Carry output represents the carry of the sum. The values of outputs are determined from the arithmetic sum of the input bits. When all input bits are 0, the output is 0. The Sum output becomes one when only one input is 1 or all three inputs are 1. Carry output is equal to 1 when two or three inputs are equal to 1. The logical function of a full adder is as Eq. (3).

$${\mathrm{Sum}} = {\mathrm{A}} \oplus {\mathrm{B}} \oplus {\mathrm{C}}$$
(3)
$${\mathrm{Carry}} = {\mathrm{AB}} + {\mathrm{BC}} + {\mathrm{AC}} = {\mathrm{MG}} ({\mathrm{A}}, {\mathrm{B}}, {\mathrm{C}})$$
Table 1 Truth table of a full adder
Full size table

Based on the logical function, a proposed unique XNOR gate and a majority gate were used to implement the full adder structure. Inputs A, B, and C enter the circuit simultaneously in clock zone 0. The inputs are applied simultaneously to the three-input XNOR gate and the three-input majority gate to obtain Sum and Carry outputs.

The inverse of the XNOR gate output, which is produced in clock zone 1, is the Sum output. The output of the majority gate, which is produced in clock zone 1, is the Carry output. The proposed cellular structure for full adder can be seen in Fig. 2.

Fig. 2
figure 2

Proposed design for full adder

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4 Simulation results and comparison

In this section, in order to evaluate the performance of the proposed structures, we investigate their operation based on parameters such as the amount of occupied area and the number of cells.

QCADesigner 2.0.3 software is used to simulate the proposed structures in QCA. The simulation is performed with Bistable Approximation engine. Table 2provides a brief description of the parameters used for simulation (Walus et al. 2004).

Table 2 QCADesigner parameters (Walus et al. 2004)
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Figure 3 shows the result of the proposed structure for the three-input XNOR gate. According to the operation table, the XNOR output of the three inputs is 1 when the number of inputs with value 1 is even. This operation can be seen in Fig. 3 with a half-cycle delay.

The implementation result of the proposed structure for the XNOR gate compared to the previous XOR gates is given in Table 3. In order to evaluate the proposed structure, the proposed design is compared with the previous structures in terms of the number of cells and occupied area. The proposed structure shows an improvement of about 10 % in terms of cell count and about 25 % in terms of occupied area compared to the previous best XOR gate.

Table 3 Implementation result for XNOR gates
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Fig. 3
figure 3

Simulation result of the proposed XNOR gate

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Figure 4 shows the result of the proposed structure for full adder. The Sum and Carry outputs are obtained with a half-cycle delay in accordance with what is provided in the operation table.

In order to evaluate the improvement of the proposed structure for full adder in QCA compared to the previous design, the values ​​of the parameters related to the implementation of the structures are presented in Table 4. As the values ​​of the implementation results, the proposed structure shows an improvement of about 5 % in terms of the number of cells, about 25 % in terms of occupied area, and about 33 % in terms of latency compared to the previous design.

Fig. 4
figure 4

Simulation result of the proposed full adder

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Table 4 Implementation for Full adder gates
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5 Conclusions

QCA introduces a new method of computing and transmitting information in nanoscale. This technology is suitable for designing computational circuits due to its high operational speed. As a basic computation component, full adder is widely used in computational combination circuits. The XOR/XNOR gate is one of the main building blocks of a full adder circuit whose performance improvement can lead to an improved full adder. To this end, in this paper, a new and efficient design for the XNOR gate based on QCA technology was presented in order to realize the implementation of the new full adder circuit structure. In order to evaluate the efficiency of designed structures, their performance has been studied by QCADesigner software. The obtained results prove the efficiency of the structures presented in this paper.