1 Introduction

CMOS technology will reach the scaling limit in nanomaterial progress [1]. Consequently, alternative technology became the goal of numerous researchers. QCA is a new Nano technique that offers a new strategy for information transformation and computation. The main building units in QCA circuits are majority gate and inverter; where any QCA circuit can be constructed using only these two blocks with help of binary wire. Many digital circuits in QCA technology have been introduced in the literature, some of them focused on combinational circuits such as [2, 3] others focused on sequential and memory circuits as in [4,5,6,7]. Arithmetic circuits are considered a crucial tool in digital circuits due to their extensive used in many signal processing applications. The addition is one of the basic arithmetic operations. A full adder is the core of any arithmetic unit and is located on its critical path; therefore, its performance directly affects the entire system’s performance. Many researchers have studied full adder by QCA, such as [8,9,10,11,12,13,14,15]. This implies that the performance enhancement of Adder will enhance the whole system’s performance. Therefore, the design of QCA adder circuits with less complexity, shorter delays, and the lowest area, will be significantly required in the future [8, 16]. In this paper, a novel QCA-XOR gate is presented with minimum complexity. To demonstrate the operation of the proposed gate, it was used to design adder circuits, with the results compared to previous designs. Many programs introduced for QCA circuits evaluation such as [17] but QCADesigner tool is more common and it will be used for circuit simulation and evaluation in this work.

This paper will be arranged as follows: Sect. 2 preliminaries. Section 3 exclusive OR gate. The adder circuit is given in Sect. 4. Simulation results with comparisons will be detailed in Sect. 5. Finally, the conclusion is in Sect. 6.

2 Preliminaries

This section will give reviews of QCA basics.

2.1 QCA Basics

2.1.1 QCA Cells

The fundamental QCA cell is illustrated in Fig. 1. QCA cell has a square shape consisting of four dots; where a pair of electrons is occupied within it diagonally, due to columbic repulsion. The injected electrons can transport through the tunnel between the adjacent dots. However, given the high potential between cells, it cannot tunnel between adjacent cells. Therefore, there are two arrangements of the QCA cell, depending on its polarization, as − 1 (logic “0”) and + 1 (logic 1).

Fig. 1
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Primary QCA cell

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2.1.2 QCA Wire

QCA wire is comprised of fundamental cells that carry the input logical value to the output. The electrons interaction forces cells to take the same polarization of the neighbour cell, in other word each cell consider as a driver cell for the next one. This approach is applied in two configurations. The first is normal (or direct mode) while the second is rotated mode [18]. These two types are shown in Fig. 2.

Fig. 2
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QCA wire a direct mode, b rotated mode

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2.1.3 QCA Gates

Three types of inverter presented in QCA are shown in Fig. 3.

Fig. 3
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QCA inverter forms

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Furthermore, a dominant gate in QCA circuits is majority gate; which has attracted the attention of many researchers [19,20,21]. Using this gate, the designer can make AND or OR gates by applying − 1 or + 1, respectively, on one of the majority inputs. Two forms of 3-input majority voters (Maj-3) are presented in Fig. 4. The Boolean equation of Maj-3 gate is given by Eq. 1 [22, 23].

$$M\left( {A,B,C} \right) = AB + BC + AC$$
(1)

The 3-inputs majority gate is expanded to many inputs majority voter with different QCA structures and layouts as in [8, 24, 25].

Fig. 4
figure 4

Three inputs majority gate forms

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2.1.4 QCA Clock

Clocking is an essential part of QCA circuits due to following reasons: synchronization, power compensation, and controlling the direction of data flow. Furthermore, it gives the power to stimulate the circuit. The clock signal controls the potential barriers between dots inside the cell to achieve synchronization. The polarization of the cell is still undetermined; as long as the cell has low potential barriers, the electrons will then easily move between points. The electrons get them localized whenever the potential barriers rise to their highest value. At this point, the polarization of the cell will be determined. The clock signal contains four clock zones and every zone contains four-phases, starting from switch phase then hold, release, and relax (as illustrated in Fig. 5) [26].

Fig. 5
figure 5

Clock zones signal

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3 The Exclusive-OR (XOR) Gate

XOR gate is a logic circuit that gives high at the output when the number of high inputs is odd. The Boolean equation of XOR is illustrated in Eq. 2.

$$XOR_{A, B} = A \cdot \bar{B} + \bar{A} \cdot B$$
(2)

The XOR logic diagram and its symbol are shown in Fig. 6.

Fig. 6
figure 6

XOR gate a logic circuit diagram, b symbol

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3.1 The Proposed XOR Layout

The XOR gate is the brick unit of many digital circuits, such as arithmetic circuits [27] and parity bit generator circuit [28]. There are several XOR layouts presented previously in QCA technology [29,30,31,32,33,34,35] but the goal was to minimize the number of majority gate or inverter used by re-forming the XOR equation. While some of them were design based on the inherent capability of QCA. An example of the conventional XOR structures presented previously is illustrated in Fig. 7a, b; while the proposed XOR layout is illustrated in Fig. 7c.

Fig. 7
figure 7

2-Input XOR gate a presented in [36], b presented in [37], c proposed design

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3.1.1 Physical Verification

The proposed structure verified physically as illustrated in Fig. 11 and Table 1. For the two adjacent cells (i, j), the electrostatic energy \(E_{i, j}^{k}\) can be calculated using Eq. 3.

$$E_{Total} = \mathop \sum \limits_{i,j} \frac{{q_{i} q_{j} }}{{4\pi \varepsilon_{0} \varepsilon_{r} \left| {r_{i, j} } \right|}}$$
(3)

where ɛ0: free space permittivity; ɛr: relative permittivity; q: the charge of electron inside dot; |ri − rj|: the space between the two dots.

Table 1 The proposed gate validation
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The most stable orientation defined by the configuration have lower energy in a certain input.

The electrostatic energy or called “kink energy” \(E_{ }^{k}\) between two cells can be calculated by letting one cell in its original state and switching the other in two contradictory polarization states and then comparing the two results and selecting the smaller one. This was done for many uncertain polarization cells (c1, c2, c3 and c4) as in Fig. 8 before calculating the polarization of the output cell for the proposed gate and the results were the polarization of c1 = 1, c2 = 1, c3 = 0 and c4 = 0. If the input pattern (A, B) = (1, 0), the calculation of the total electrostatic energy at dot p (named Up) for the output cell is shown below:\(\begin{aligned} Up & = \frac{K}{D1} + \frac{K}{D2} + \frac{K}{D3} + \frac{K}{D4} + \frac{K}{D5} + \frac{K}{D6} + \frac{K}{D7} + \frac{K}{D8} + \frac{K}{D9} + \frac{K}{D10} + \frac{K}{D11} + \frac{K}{D12} + \frac{K}{D13} + \frac{K}{D14} + \frac{K}{D15} + \frac{K}{D16} \\ & = \frac{K}{50.61} + \frac{K}{50.61} + \frac{K}{54.78} + \frac{K}{61} + \frac{K}{40} + \frac{K}{32.28} + \frac{K}{36.89} + \frac{K}{41.48} + \frac{K}{22.83} + \frac{K}{22.83} + \frac{K}{21.93} + \frac{K}{11} + \frac{K}{40} + \frac{K}{32.28} + \frac{K}{44.72} + \frac{K}{42.45} \\ & = 11.7 \times 10^{ - 20} {\text{J}} \\ \end{aligned}\) where \({\text{k}} = \frac{{q^{2} }}{{4\pi \in_{0} \in_{r} }} = 23.04 \times 10^{ - 20}\) and D is the distance between two dots.The proposed XOR is verified by simulating it with QCADesigner software and the results are given in Sect. 5.

Fig. 8
figure 8

proposed configuration to analysis the proposed XOR gate

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3.1.2 Power Consumption Analysis

The estimation of the dissipated power for the proposed gate can be defined using the most common tool called QCAPro. This tool has the ability to manipulate large circuit because it uses fast approximation and it can expect the losses of power in non-adiabatic switching.

The analysis of power dissipation at different tunneling energy levels (0.5 Ek, 1 Ek and 1.5 Ek) for the proposed gate in comparison with previously counterparts is shown in Table 2. The power dissipation map for proposed gate at 0.5 Ek is illustrated in Fig. 9.

Table 2 Power dissipation comparison at 2 K for many XOR gates
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Fig. 9
figure 9

The power dissipation map for the proposed 2-input XOR gate with the level 0.5 Ek tunnelling energy at 2-Kelvin temperature

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4 Adder Circuits

4.1 Half Adder

Half adder responsible for adding two logical inputs and provides two outputs sum and carry, if input variables are A and B. The sum and carry of these two variables can be calculated by Eq. 4.

$$\begin{aligned} & {\text{Sum}} = {\text{A}} \oplus {\text{B}} \\ & {\text{Carry}} = {\text{AB}} \\ \end{aligned}$$
(4)

Half adder logic circuit is illustrated in Fig. 10.

Fig. 10
figure 10

Half adder logic diagram

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On the other hand, the full adder adds three logical variables and provides two outputs, sum and carry. If the input variables are A, B, and Cin, the two outputs can be found using Eq. 5.

$$\begin{aligned} & {\text{Sum}} = \left( {\text{A}} \right){\text{XOR}}\left( {\text{B}} \right){\text{XOR}}\left( {{\text{C}}_{\text{in}} } \right) \\ & {\text{Carry = }}\left( {\text{AB}} \right){\text{ OR }}\left( {{\text{B C}}_{\text{in}} } \right){\text{ OR }}\left( {{\text{C}}_{\text{in}} {\text{A}}} \right) \\ \end{aligned}$$
(5)

By following the logic circuit previously given in Fig. 10, the half adder can be easily designed with proposed XOR gate as illustrated in Fig. 11.

Fig. 11
figure 11

Proposed QCA-half adder

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4.2 Full Adder

The full adder logic circuit is illustrated in Fig. 12.

Fig. 12
figure 12

Full adder logic diagram

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Note: the carry equation is the same as the Maj-3 equation, as previously mentioned in Eq. 1. Therefore, the full adder circuit can be implemented as shown in Fig. 13. Another form of full adder logical representation that utilizes multi-input majority function and its reliability is studied in [42].

Fig. 13
figure 13

Full adder logic circuit a based on Maj-3, b based on Maj-5 [24]

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The full adder design approach illustrated in Fig. 13b is adopted in most of previous literatures because it produces more efficient circuit with less complexity (number of cells and circuit layout area) and latency (number of required clock phases to produce output) as the circuits reported in [14, 43, 44] as shown in Fig. 14a, b. On the other hand, the design approach shown in Fig. 13a is not commonly used in QCA circuitry due to the high complexity of the produced circuit and the designs reported in [26, 45]. The proposed XOR in this work solve this issue. It was used to design full adder circuit with QCA technology as shown in Fig. 14c.

Fig. 14
figure 14

QCA-full adder a presented in [44], b presented in [14], c proposed structure

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5 Simulation Results

In this work, QCADesigner tool V 2.0.3 [46] is used to simulate the proposed circuits with the simulation parameters shown in Fig. 15. The proposed XOR in Fig. 7c produces the output waveform shown in Fig. 16 and it is clear from the output that the proposed gate shows error-free operation for all input possibilities. From noticing the polarization of the output waveform, it can be concluded that the proposed gate has acceptable robustness. The proposed half adder and full adder circuits are simulated under the same conditions and produced the output waveforms shown in Figs. 17 and 18 respectively. In both circuits, the output was correct for all input states.

Fig. 15
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QCADesigner simulation parameters

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Fig. 16
figure 16

Proposed XOR simulation result

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Fig. 17
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Proposed half adder simulation result

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Fig. 18
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Proposed full adder simulation result

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The proposed gate is superior in terms of area, number of cells, latency when compared with previous reported designs. Table 3 gives the comparison results. Furthermore, the proposed gate makes a reduction in delay time to 50% compared to best previously reported; where it can be implemented in a ¼ clock cycle of the clock signal defined in Fig. 5. The proposed design requires only 9 cells; while the best previous design required 14 cells. Another important aspect of the proposed design is that it does not require wire crossover.

Table 3 Comparison of proposed XOR with existing structures
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The results of the comparison for the proposed half adder, with existing designs, are shown in Table 4. From this table, it is obvious that the proposed structure is an optimal design in comparison with previously counterparts. The proposed half adder is crossover free, with minimum cell number and area. Table 5 details the comparison results of the full adder with existing structures. It is clear from this table that the proposed full adder is distinguished in terms of complexity; where it was implemented using only 39 cells, by improving 15% from the nearest competitor structure presented in [43].

Table 4 Comparison of proposed half adder with existing structures
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Table 5 Proposed full adder compared to previously reported structures
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6 Conclusions

In this paper, a new single layer Exclusive-OR gate design is introduced with QCA technology. The proposed design has a 50% speed improvement and a 35% reduction in the number of cells needed over the best reported XOR. The presented gate is used to design superior half and full adders with a very noticeable reduction in the circuit layout area and number of cells. The proposed XOR gate shows a noticeable reduction in the power dissipation compared to the previous designs. The reduction in the complexity of the proposed designs is very encouraging to adapt it to other circuit designs.