1 Introduction

Recently, studies to find the new technologies to substitute CMOS circuits have increased. Quantum–dot cellular automata (QCA) is one of these technologies for digital logic designs at nano-scale with ultra low power, high performance and least feature size [2, 3]. The basic component in QCA is quantum cell. Each quantum cell is composed of four dots and two excess electrons. These electrons can tunnel between dots due to columbic interaction and diagonally occupy corners of the cell, hence leading to two stable arrangements for quantum cell which are shown in Fig. 1. These two stable states of a quantum cell are named as cell polarizations. Polarizations − 1 and + 1 are encoded as logic “0” and “1”, respectively. As shown in Fig. 2a, by placing several quantum cells side by side, a standard QCA wire can be constructed to transmit a logic value. Moreover, a QCA inverter chain can be constructed exploiting 45 orotated QCA cells. This kind of wire propagates the input signal in odd cells and inversion of the input signal in even cells, as shown in Fig. 2b. Coplanar wire is achieved using these two types of wires as shown in Fig. 3 [2, 25, 26].

Fig. 1
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Two possible polarization states in a quantum cell

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Fig. 2
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a QCA standard wire and b inverter chain

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Fig. 3
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Coplanar cross wiring

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Clock scheme in QCA contains four phases. In the Switch phase, cell begins to polarize. In the Hold phase, barrier is kept high. In the Release phase, cells will be allowed to start going in internal polarity state. Finally, in the Relax phase, cell remains in non-polarity state [4,5,6]. This scheme is shown in Fig. 4.

Fig. 4
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Clocking scheme

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2 QCA Main Gates

Inverter gate is one of the basic gates in QCA. The structure of this gate is shown in Fig. 5 where columbic repulsion between the corners of the parallel cells makes the polarization of the starred cell to change into the opposite polarity of the input.

Fig. 5
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QCA inverter gate

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The majority gate; majority voter; that is shown in Fig. 6, is the elementary gate in designing QCA based circuits. The majority gate acts as a three input logic function. Assuming that the inputs are A, B and C, the function of the majority gate is shown as (1).

$$ \text{M(A,B,C)}=\text{AB}+\text{AC}+\text{BC} $$
(1)

If one of the input cells in the majority gate is constantly fixed to + 1, only one of the other cells is required to be + 1, so that the polarity in output cell is + 1. In fact, it behaves like an OR gate and is represented as:

$$ \text{M(A,B,1)} = \text{AB} + \text{(A1)} + \text{(B1)} = \text{AB} + \text{A} + \text{B} = \text{A} + \text{B} $$
(2)

By fixing the polarization of one input cell to − 1, it is clear that the other two inputs must be in + 1 polarization to result in + 1 polarization in the output cell. In fact, this structure acts like an AND gate and is demonstrated as:

$$ \text{M(A,B,0)} = \text{AB} + \text{(A0)} + \text{(B0)} = \text{AB} $$
(3)

The logic function of five-input majority gate is as:

$$\begin{array}{@{}rcl@{}} \text{M(A,B,C,D,E)} &=& \text{ABC}+\text{ABD}+\text{ABE}+\text{ACD}+\text{ACE}+\text{ADE}+\text{BCD}\\ &&+\text{BCE}+\text{BDE}+\text{CDE} \end{array} $$
(4)

The structure of this gate is shown in Fig. 7 [20,21,22,23,24]. By setting two of the input cells’ polarization to − 1 or + 1, a three-input AND gate and also a three-input OR gate can be formed, respectively.

Fig. 6
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QCA three-input majority gate

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Fig. 7
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QCA five-input majority gate

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3 Reversible Logic

Reversible gates are circuits in which number of outputs is equal to the number of inputs and there is a one-to-one correspondence between the vector of inputs and outputs. It not only helps us to determine the outputs from the inputs, but also helps us to uniquely recover the inputs from the outputs [1, 7].

Reversible logic gates are those with zero loss of information. Reversible logic gate reduces the power dissipation and the latency in the manipulation of any logical operation.

4 Related Works

Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The main difference between latches and flip-flops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other word, when they are enabled, their content changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes. There are basically four main types of latches and flip-flops; SR, D, JK and T. The major differences in these flip-flops are the number of inputs and how they change state.

One of the most attractive areas in QCA technology is designing reversible circuits especially flip-flop cells. Several QCA based designs of reversible circuits and reversible flip-flops have been reported previously [8,9,10,11,12,13,14,15,16,17]. In [8] different reversible circuits are achieved based on a novel design methodology and implemented through QCA logic device. the work reported in [9], deals with the QCA realization of different latches, such as SR, JK, T and D latches based on reversible approach for molecular QCA. The single missing/additional cell based defect of those latches is also explored in [9]. In [10], several classical logic gates, such as XOR gate and XNOR gate are implemented based on QCA technology. Beside, CNOT gate and Toffoli gate also realized through QCA in [10].

A heuristic model based on cell-cell interactions is presented for ordinary flip-flop in [14]. A theoretical approach for the analysis of QCA power and energy based on density matrix formalism is presented in [15]. It has discussed the approach to analyze the energy flow within QCA architecture and also discussed about the energy relaxation time. However, it is devoid of any derivation and analysis.

A circuit of D flip-flop using seven reversible gates with eight garbage outputs is presented in [16]. Then an improved version of [16] for reversible D flip-flop which was a realization of the conventional D flip-flop sequential circuit is proposed in [17]. This work proposed a new gate; BME gate; which was used to optimize the existing reversible circuit based on the number of reversible gates used and the garbage outputs produced. The number of gates was reduced to four and the number of garbage outputs was also reduced to four.

In [13] the author interested to determine the exact clock energy required to operation of a reversible flip flop architecture consisting of N number of cells. This work optimized 4 to 2 electron two dimensional quantum-dot cellular automata logic reversible flip-flops. The presented structures in this work are shown in Fig. 8. Inputs are in the circle in the presented structures in this paper.

Fig. 8
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Reversible flip-flops presented in [13], a D, b T, c JK and d SR

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These structures have disadvantages such as large number of cells and large occupation area. In this paper, we propose efficient reversible structures for four flip-flops.

5 Proposed Reversible Structures

In this section, we describe the proposed architectures for the four flip-flops. The proposed architectures of the flip-flops have been shown below.

Table 1 shows the truth table of proposed reversible D flip-flop. This table contains the three input lines and also three output lines. The block structure and QCA design of proposed reversible D flip-flop are illustrated in Fig. 9a and b, respectively. This structure is useful and very simple. The logic functions of outputs of proposed D flip-flop are as:

$$ \text{C}=\text{C}, \text{O1}=\text{D}, \text{Q(t}+\text{1)}=\text{Q(t)} $$
(5)

Table 2 shows the truth table of proposed reversible T flip-flop. This table contains the three input lines and also three output lines. The block structure and QCA design of proposed reversible T flip-flop are illustrated in Fig. 10a and b, respectively. This structure is constructed from one two-input AND gate and one two-input XOR gate. This structure is similar to the structure of Toffoli gate. The proposed reversible T flip-flop has 23 QCA cells and 0.02 µm 2 occupation area. As it can be seen in Fig. 10, this structure is implemented in a single layer. It uses only 90-degree cells and does not use the coplanar cross-wiring. The logic functions of outputs of proposed T flip-flop are as:

$$ \text{C}=\text{C}, \text{O1}=\text{T}, \text{Q(t}+\text{1)}=\text{(CT) XOR Q(t)} $$
(6)
Table 1 Truth table of proposed reversible D flip-flop
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Fig. 9
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Proposed reversible D flip-flop, a block structure and b QCA design

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Table 2 Truth table of proposed reversible T flip-flop
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Fig. 10
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Proposed reversible T flip-flop, a block structure and b QCA design

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The truth table of proposed JK flip-flop is shown in Table 3. This table contains the four input lines and also four output lines. The block structure and QCA design of proposed reversible JK flip-flop are illustrated in Fig. 11a and b, respectively. This design is composed of six three-input majority gates and three five-input majority gates. The proposed reversible JK flip-flop has 274 QCA cells and 0.29 µm 2 occupied area. It uses only 90-degree cells and also uses the coplanar cross-wiring. The logic functions of outputs of proposed JK flip-flop are as:

$$ \text{C}=\text{C} $$
(7)
$$\text{O1}=\text{C}^{\prime}\text{J}+\text{CJK}+\text{CJQ(t)}+\text{JKQ(t)}+\text{CJKQ(t)}=\text{C}^{\prime}\text{J}+\text{Maj(C,J,K,Q(t),0)} $$
$$\text{O2}=\text{C}^{\prime}\text{K}+\text{CJK}+\text{CJQ}^{\prime}\text{(t)}+\text{JKQ}^{\prime}\text{(t)}+\text{CJKQ}^{\prime}\text{(t)}=\text{C}^{\prime}\text{K}+\text{Maj(C,J,K,Q}^{\prime}\text{(t),0)} $$
$$\begin{array}{@{}rcl@{}} \text{Q(t}+\text{1)}&=&\text{C}^{\prime}\text{Q(t)}+\text{CJK}^{\prime}+\text{CJQ(t)}+\text{JK}^{\prime}\text{Q(t)}+\text{CJK}^{\prime}\text{Q(t)}=\text{C}^{\prime}\text{Q(t)}\\ &&+\text{Maj(C,J,K}^{\prime},\text{Q(t),0)} \end{array} $$

We use the truth table of JK flip-flop to construct the SR flip-flop. These flip-flops have the same behavior in reversible logic in QCA.

Table 3 Truth table of proposed reversible JK flip-flop
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Fig. 11
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Proposed reversible JK flip-flop, a block structure and b QCA design

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6 Simulation Results

In this section, the proposed structures for reversible flip-flops are simulated with QCADesigner version 2.0.3 [18] that is an accurate simulation tool for QCA circuits. Simulation parameters are assumed as Table 4 for all structures. Proposed structures are simulated using the Coherence Vector simulation engine and also Bistable Approximation simulation engine and similar operations were achieved from both simulation engines.

Table 4 Simulation parameters
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The simulation result of proposed reversible T flip-flop is illustrated in Fig. 12. This result confirms that the proposed structure works correctly and its outputs are achieved only after two clock zones.

Fig. 12
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Simulation result of proposed reversible T flip-flop

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Figure 13 Shows the simulation results of the proposed JK flip-flop. This result confirms that the expected operation is correctly achieved with one clock cycle delay.

Fig. 13
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Simulation result of proposed reversible JK flip-flop

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Table 5 shows the result of performance analysis of the proposed structures and previous structures [13] in terms of the cell count, area and Latency. As can be inferred from the values of Table 5, the proposed structures provide an improvement in cell count, latency and area compared to the other previous structures.

Table 5 The comparative results for the flip-flops
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We use QCAPro tool [19] to evaluate the energy consumption of proposed structures. We evaluate the proposed structures under three different tunneling energy levels (0.5 Ek, 1 Ek and 1.5 Ek) at 2.0 K temperature. The power dissipation maps of our structures with 0.5 Ek are shown in Fig. 14. High power dissipating cells are indicated using thermal hotspots with darker colors. Table 6 shows the total dissipated energy divided into leakage and switching energies for the proposed structures and previous structures. It is obvious that we have achieved a consistent reduction in power dissipation.

Fig. 14
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Power dissipation maps for the proposed reversible flip-flops with 0.5 E k , a D, b T and c JK

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Table 6 Analysis of energy consumption of the flip-flops
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7 Conclusion

In this paper, we proposed the reversible structures for four flip-flops in QCA. QCADesigner is used to simulate these structures. Simulation results confirmed the operations of proposed structures. The comparison demonstrated that the proposed structure is better than previous designs. We used QCAPro to evaluate the power consumption of QCA structures.