1 Introduction

In today’s modern period, due to competition in market and industry, all devices and machines should be developed in terms of accuracy, power consumption, minimum required voltage, dimensions, and manufacturing costs, etc. In other words, various components of a device must be optimized to compete in industry and market. One crucial element that significantly affects the overall performance of devices is a bandgap references (BGR). Voltage references are frequently used in analog and electronic circuits. These circuits is usually used in bias circuitries, low-dropout regulators, DRAMs, flash memories, and data converters. The performance and accuracy of decoders and encoders, as well as the accuracy of conversion of a signal processing block in data converter systems, depends on the accuracy of the voltage references. Important parameters in design of voltage references are temperature coefficient (TC), line sensitivity (LS), power supply ripple rejection (PSRR), and power consumption [1,2,3].

Voltage references should be designed such that they stay unchanged towards the changes of process, supply voltage and temperature. In order to design a bandgap circuit that is independent of temperature, a complementary-to-absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage should be generated and mixed to compensate the temperature changes [1]. A CTAT voltage can be generated through the base-emitter voltage of a diode-connected BJT or gate–source voltage of a MOS transistor. A PTAT voltage can be generated through the difference of the gate-source voltages of two transistors or difference of base-emitter voltages of two BJTs with different collector currents. For generating a voltage reference, the sum of PTAT and CTAT voltages with appropriate coefficients is mandatory [1,2,3,4,5].

There is a demand for small bandgap voltage reference that are insensitive to process, voltage, and temperature (PVT) variations while minimizing power dissipation. The reduction of power consumption and circuit dimensions not only necessitates the adoption of new technologies but also affects certain parameters, such as the maximum voltage headroom. As dimensions decrease, the threshold voltage also decreases. The amount of voltage reference should be decreased proportionally with the technology, to prevent a decrease in circuit lifespan, minimize power consumption, and lower chip temperature. Hence, sub-1-V and low-power supply voltage reference is an inevitable part of modern systems [5].

It is worth noting that while silicon references are commonly used in industries to reduce final costs by using standard CMOS technologies, Hedayati and et al. with the help of materials like silicon carbide (SiC), introduce a voltage reference that operates for a wide temperature range of 25–500 °C. However, this circuit suffers from high power consumption and such structure is not applicable in standard CMOS technologies [6]. In Ref. [7], a fractional bandgap is presented. Using emitter–base voltage of a BJT as a CTAT voltage and applying a current with positive TC to a resistor in a feedback loop, a near zero TC voltage is generated. Due to the use of op-amp and BJTs, the power consumption of the fractional bandgap is in micro watt range [7]. Banba and et al. [8] proposed a sub-1-V bandgap voltage reference by converting sum of two PTAT and CTAT currents to a voltage in a feedback loop. Due to use of op-amp and diodes, it also suffers from high power consumption and supply voltage. In [9] a switched-capacitor bandgap circuit is introduced in which no resistor is used. Using capacitors instead of resistors in [9] results in a high precision voltage reference. While an offset cancellation technique is used [9], but the power consumption of the op-amp is still a challenging issue.

Wang and et al. [10] used a MOS transistor in the weak inversion to reduce the power consumption and voltage headroom of the circuit. Also, the offset of op-amp has been suppressed in [10]. In [11] a cross-coupled structure for BGR is presented. But this circuit is suitable for the voltage references higher than one volt, which is not compatible with the recent technology nodes [11]. The line sensitivity has been significantly improved by using a self-adjusting circuit in [12]. All the transistors used in [12] operate in the sub-threshold region, which has reduced the power consumption of the circuit. However, this circuit has a high TC [12]. A self-biased nano-watt voltage and current reference has been presented in [13] by using a single resistor with zero temperature coefficient (TC). The main challenge in [13] is realizing such a zero TC resistor. A trimless voltage reference has been offered in [14] with using stack of LVT MOS transistor. This approach leads to improvement of occupied area and power consumption as well. Some other BGRs are also presented in literature [15, 16] that suffer from high power consumption.

In [17] a bandgap circuit is presented in which a modified beta multiplier bias circuit is used to reduce the mismatch caused by the contribution of the PMOS transistors op-amp and threshold mismatch between two NMOS transistors. A sub-1V voltage-mode reference circuit that sums the PTAT voltage with a scaled version of the CTAT voltage has been presented in [18]. The advantages of the proposed circuit compared to current-mode bandgap circuits are the elimination of a current mirror stage and minimizing the current mirror ratio of PTAT, which leads to error reduction. In order to achieve a low TC voltage reference, a curvature compensation technique is applied to a voltage-mode sub-bandgap reference circuit in [19] that results in flicker noise reduction and ease of op-amp requirements. Nagulapalli and et al. [20] introduce a bandgap reference circuit in which noise multiplication of the operational amplifier is limited by moving the resistor used in the emitter of BJT into its base. This resistance is combined with a CTAT resistance in the current mode bandgap reference.

In this work a simple three-branched design is proposed without the use of any op-amp and BJT. Only two resistors and MOS transistors have been used in the weak inversion region to significantly reduce the power consumption. The remains of the paper are organized as follows: Sect. 2 presents a study of the proposed BGR circuit. The proposed BGR is analytically examined in Sect. 3. The important parameters (like LS, PSRR, and TC) of a bandgap circuit are defined in Sect. 4. Section 5 presents the post-layout simulation results and the paper is concluded in Sect. 6.

2 Proposed BGR structure

The schematic of the proposed BGR structure is shown in Fig. 1. The behavior of the gate-source voltage of MOS transistors in weak inversion is similar to that of the emitter–base voltage of a BJT [5, 13, 21]. Therefore, the gate-source voltage of MOS transistors in sub-threshold is utilized as a CTAT voltage and the difference of gate-source voltages of two MOS transistors is used for generating a PTAT voltage. The proposed circuit has a self-biased structure that eliminates the need for any external bias circuitry. By employing the MOS devices in sub-threshold, the circuit can operate with low supply voltages (i.e. less than 1V) that results in a very low power consumption.

Fig. 1
figure 1

Schematic of the proposed BGR with start-up circuit

Full size image

As shown in Fig. 1, the proposed circuit includes a start-up circuitry and a bandgap core. The start-up circuit consists of transistors MS1, MS2, and MS3 in which MS1 acts as a MOS capacitor. When the circuit is powered-up, gate of MS2 is charged via MS1 until it turns on, and when MS2 turns on, the gate voltage of M4, M5 and M6 is pulled down and leads to the separation of the circuit from the zero point; as a result, the circuit returns to its desired operation. When the output voltage reaches its steady state value, MS3 turns on, and in this case, the gate voltage of MS2 transistor is pulled down and turns off. At this point, the start-up circuit completes its work and is disconnected from the bandgap core. Actually, due to self-biasing of the proposed BGR, the start-up circuit only helps the circuit to start quickly [22].

According to the Fig. 1, the bandgap core has three branches. In the first branch consists of M1, to generate the required PTAT current (ID1 = IPTAT), the gate-source voltage of transistor M1 is connected to one side of R1 (i.e. node A) and the gate-source voltage of transistor M2 is connected to the other side of R1 (i.e. node B). In this way a PTAT current given by (VAB) /R1 = (VGS1 − VGS2)/R1 is achieved. It is worth mentioning that transistors M7–9 are used in a cascode scheme with M4–6 to improve the PSRR and LS, and also reduce the impact of power supply noise on the reference voltage. The generated PTAT current ID1 is mirrored into the second branch by ratio of\(\frac{{(\frac{W}{L})}_{8}}{ {(\frac{W}{L})}_{7}}\). Similarly, with ratio of\(\frac{{(\frac{W}{L})}_{9}}{ {(\frac{W}{L})}_{8}}\), the current ID2 is mirrored into the third branch. ID3 passes through resistor R2 and generates the required PTAT voltage. Supposing identical aspect ratio for M7, M8 and M9, the generated PTAT voltage is equal to VPTAT = VCD = R2.ID3 = R2\(.(\frac{{V}_{GS1-\text{VGS}2}}{\text{R}1}\)). The mentioned current passes through a diode-connected transistor (i.e. M3) and generates a CTAT voltage (VGS3). Therefore, output voltage Vref is obtained by applying a KVL from the output node of the circuit (C node) to ground as VREF = VCD + VGS3, where VCD = R2 \(.\frac{{V}_{GS1-\text{VGS}2}}{\text{R}1}\) is a PTAT voltage and VGS3 is a CTAT voltage.

Note that, here, all the currents of the three branches are assumed identical (ID1 = ID2 = ID3). Finally, generated CTAT voltage (i.e. VGS3) and PTAT voltage (i.e. voltage across R2) are added to each other and the desired reference voltage is generated. The proposed design, operates with a nano-ampere current and ultra-low power consumption. Detailed analyses of the proposed circuit are presented below.

3 Mathematical analysis

The drain current of a MOS transistor in the weak inversion region is given by (1) [21]:

$$I_{D} = I_{0} \left( \frac{W}{L} \right)\exp \left( {\frac{{V_{GS} - V_{TH} }}{{nV_{T} }}} \right)\left[ {1 {-} \exp \left( { - \frac{{V_{DS} }}{{V_{T} }}} \right)} \right]$$
(1)

where VTH, VGS, VDS and VT are the threshold, gate-source, drain-source, and thermal voltages, respectively and \(\frac{W}{L}\) is MOS transistor aspect ratio. I0 is drain’s current when VGS = VTH and is given by (2):

$${I}_{0}={{\mu {C}_{ox}\left(n-1\right) V}_{T}}^{2}$$
(2)

in which \(n\) is the sub-threshold gradient coefficient. In subthreshold, when VDS > 4VT the transistor is in the saturation region, and its current is independent of VDS. To avoid the effect of changes in VDS on the circuit, parameters of the transistor should be chosen to operate in saturation region. The approximate value of transistor’s current in saturation is as follows:

$$I_{D} = \mu C_{ox} \left( {n - 1} \right)V_{T}^{2} \left( \frac{W}{L} \right).{\text{ exp}}\left( {\frac{{V_{GS} - V_{TH} }}{{nV_{T} }}} \right).\left[ {1{ }{-}{\text{ exp }}\left( { - \frac{{V_{DS} }}{{V_{T} }}} \right)} \right] \approx \mu C_{ox} \left( {n - 1} \right) V_{T}^{2} \left( \frac{W}{L} \right){\text{exp}}\left( {\frac{{V_{GS} - V_{TH} }}{{nV_{T} }}} \right)$$
(3)

So the VGS of transistors in subthreshold is given by (4):

$${V}_{GS}=n{V}_{T}ln\left(\frac{{I}_{D}}{\mu {C}_{ox}\left(n-1\right){{V}_{T}}^{2}\left(\frac{W}{L}\right)}\right)+{V}_{TH}$$
(4)

VGS can be assumed as a CTAT voltage that can be represented for a MOS transistor as (5):

$${V}_{GS} (T)={ \beta }_{0} + {\beta }_{1}T + {\beta }_{2}T ln\left(T\right)\approx { \beta }_{0}+ {\beta }_{1}T$$
(5)

The constant coefficients \(\beta\) 0, \(\beta\) 1, and \(\beta\) 2 depend on the technology and \(\beta\) 2 is high-order nonlinear effects which is considered negligible. The temperature dependancy of VGS1, VGS2, and VGS3 are shown in Fig. 2. In Fig. 2, the voltages VGS1, VGS2, and VGS3 show CTAT behaviour. VGS1 − VGS2 is also is depicted in Fig. 2 and it represents a PTAT behaviour.

Fig. 2
figure 2

VGS of M1, M2 and M3 transistors versus temperature

Full size image

Using Kirchhoff law in Fig. 1, the current ID1 can be determined as (6),

$${I}_{D1}=\frac{{V}_{AB}}{\text{R}1}=\frac{{V}_{GS1}-{V}_{GS2}}{\text{R}1}$$
(6)

and current ID2 is given by (7):

$${I}_{D2}={K}_{1} {I}_{D1}$$
(7)

in which,

$${K}_{1}=\frac{ {(\frac{W}{L})}_{8}}{ {(\frac{W}{L})}_{7}}$$
(8)

The transistors M4 to M9 form a current mirror, so the current ID3 can be expressed as follows:

$${I}_{D3}={K}_{2} {I}_{D2}$$
(9)
$${K}_{2}=\frac{ {(\frac{W}{L})}_{9}}{ {(\frac{W}{L})}_{8}}$$
(10)

Therefore the generated reference voltage is as (11):

$${{V}_{ref} =V}_{GS3}+(\frac{{\text{R}}_{2}}{{\text{R}}_{1}}\frac{ {(\frac{W}{L})}_{8}}{ {(\frac{W}{L})}_{7}}\frac{ {(\frac{W}{L})}_{9}}{ {(\frac{W}{L})}_{8}})({V}_{GS1}-{V}_{GS2})$$
(11)

Obviuosly Eq. (11) is comprised of a PTAT term (i.e. \({V}_{GS1}-{V}_{GS2}\)) and a CTAT term (i.e. \({V}_{GS3}\)), and choosing propoer value for \(\frac{{\text{R}}_{2}}{{\text{R}}_{1}}\frac{ {(\frac{W}{L})}_{8}}{ {(\frac{W}{L})}_{7}}\frac{ {(\frac{W}{L})}_{9}}{ {(\frac{W}{L})}_{8}}\) results in a zero TC Vref. The required value for \(\frac{{\text{R}}_{2}}{{\text{R}}_{1}}\) can be obtained by derivation of (11) with respect to temperature and setting it equal to 0 as follows:

$$\frac{\partial Vref}{\partial T}=\frac{\partial ({ \beta }_{\text{0,3}}+{ \beta }_{\text{1,3}}T)}{\partial T}+\frac{{\text{R}}_{2}}{{\text{R}}_{1}}\frac{ {(\frac{W}{L})}_{8}}{ {(\frac{W}{L})}_{7}}\frac{ {(\frac{W}{L})}_{9}}{ {(\frac{W}{L})}_{8}}\left[\frac{\partial \left({ \beta }_{\text{0,1}}+{ \beta }_{\text{1,1}}T\right)}{\partial T}-\frac{\partial \left({ \beta }_{\text{0,2}}+{ \beta }_{\text{1,2}}T\right)}{\partial T}\right]=0$$
(12)
$$\frac{{\text{R}}_{2}}{{\text{R}}_{1}}\frac{ {(\frac{W}{L})}_{8}}{ {(\frac{W}{L})}_{7}}\frac{ {(\frac{W}{L})}_{9}}{ {(\frac{W}{L})}_{8}}=\frac{{ \beta }_{\text{1,3}}}{{ \beta }_{\text{1,2}}-{ \beta }_{\text{1,1}}}$$
(13)

According to Fig. 2 the temperature coefficient (TC) of PTAT voltage is 0.345 mV/°C, while the TC of the CTAT voltage is − 0.845 mV/°C. Therefore, supposing \(\frac{{(\frac{W}{L})}_{8}}{ {(\frac{W}{L})}_{7}}\frac{ {(\frac{W}{L})}_{9}}{ {(\frac{W}{L})}_{8}}=1\) and considering Eq. (13), requierd \(\frac{{\text{R}}_{2}}{{\text{R}}_{1}}\) is given by (14):

$$\frac{{\text{R}}_{2}}{{\text{R}}_{1}}=\frac{0.845}{0.345}=2.5$$
(14)

4 Line Sensitivity, PSRR and Temperature coefficient

Line sensitivity (LS) explains the sensitivity of the voltage reference to the supply voltage. According to this description, lower LS results in lower dependency of Vref to VDD. LS is directly related to Power Supply Rejection Ratio (PSRR) as well, and minimizing LS results in mimimizing low frequency PSRR.

The LS for a voltage reference can be determined using (15):

$$LS=\frac{\frac{\Delta Vref}{\Delta Vdd}}{Vref}\times 100\%$$
(15)

where, ∆Vref represents voltage reference variations, while ∆Vdd denotes supply voltage variations. It is worth noting that employing a cascode structure reduces LS, though it may also increases the minimum required supply voltage.

PSRR describes the effect of power supply noise (small-signal variation) on voltage reference. It is also defined as (16):

$$\text{PSRR }=20\text{log }(|\frac{{v}_{ref}}{{v}_{dd}}|)$$
(16)

By using the small-signal equivalent circuit and simplifying it, the value of \(\frac{{v}_{ref}}{{v}_{dd}}\) for Fig. 1 can be obtained as (17):

$$(\frac{{v}_{ref}}{{v}_{dd}})\approx \frac{({R}_{2}+\frac{1}{{g}_{m3}}||{r}_{o3}) }{({R}_{2} +\frac{1}{{g}_{m3}}||{r}_{o3}) + {g}_{m6}{r}_{o6}{r}_{o9}})$$
(17)

The temperature coefficient of a bandgap reference is defined as (18). Apparently low TC is desirable to acheive a tempereture independent reference voltage.

$$TC=\frac{{V}_{ref\left(maximum\right)}-{V}_{ref\left(minimum\right)}}{({T}_{maximum}-{T}_{minmum})\times {V}_{ref\left(at T=27^\circ \text{C}\right)}}$$
(18)

5 Post layout simulation results

To verify the performance of the suggested bandgap reference (BGR) circuit in Fig. 1, a prototype of the circuit is designed using TSMC 0.18-μm CMOS technology, and the circuit parameters are shown in Table 1. The circuit was designed with an active area of 480μm × 840μm. All required resistors are implemented by using high-resistance polysilicon (HpolyR). Since all resistors have identical temperature coefficient so the ratio of \(\frac{{\text{R}}_{2}}{{\text{R}}_{1}}\) in (11) remains independent of temperature and does not affect the temperature coefficient of Vref. To mitigate the effect of channel length modulation, the cascode transistors should be sufficiently large to reduce the line sensitivity (LS) of the produced voltage reference.

Table 1 Circuit parameters
Full size table

The current of the circuit in Fig. 1 is set by the value of R1. Therefore, R1 should be adjusted to maintain the current of the first branch in nano ampere range (here, 3.033nA) for achieving ultra-low power consumption.

Figure 3 shows the post layout simulation results of supply dependency of the proposed circuit at TT corner. As seen, over a wide range of power supply variations from 0.8 to 1.8V, LS is as low as 0.31%/V that indicates ultra-low dependency of the generated reference voltage to power supply variation. The circuit consistently produces a constant voltage of 644 mV, while drawing a total current of only 9.1 nA from the 0.9 V power supply, resulting in an ultra-low power consumption of 8.2 nW.

Fig. 3
figure 3

Supply dependency of the proposed BGR

Full size image

The simulated reference voltage vs. temperature is depicted in Fig. 4. According to Fig. 4, the circuit’s temperature coefficient (TC) is 78.5 ppm/°C over the temperature range of − 25 to 85 °C, that confirms the voltage reference has a good robustness against temperature variations. Figure 5 illustrates the simulated Vref versus VDD variation in different process corners. It shows the BGR sensitivity to the power supply variation in all process corners. Line sensitivity (LS) of the circuit is 0.48%/V, 0.30%/V, 0.34%/V and 0.33%/V respectively in the SS, FF, SF and FS corners.

Fig. 4
figure 4

Thermal behavior of the proposed BGR

Full size image
Fig. 5
figure 5

Line sensitivity at different process corners

Full size image

The simulated Vref versus temperature in different process corners is depicted in Fig. 6. The TC is measured to be 78.5 ppm/°C for TT corner while the TC is 92.4 ppm/°C for FF. The TC is 136 ppm/°C for the FS corner and it is 98.2 ppm/°C at SF corner. For SS corner the TC is 79.8 ppm/°C. Hence, the simulation results in Fig. 6 indicate that the proposed circuit has a low dependency on the process corner.

Fig. 6
figure 6

Thermal behavior of BGR at all process corners

Full size image

Figure 7 demonstrates the PSR of the proposed circuit. According to Fig. 7 the effect of power supply noise on the voltage reference has 40 dB attention in the frequency range of 1–100 Hz.

Fig. 7
figure 7

PSRR of the proposed BGR

Full size image

To estimate the effect of process and fabrication errors on the circuit, Monte Carlo simulation results for 1000 trials are shown in Fig. 8. In Fig. 8a the average generated reference voltage is 644.23 mV with a standard deviation of 16.24 mV. As seen in Fig. 8b, the circuit has an average TC of 81.59 ppm/°C and the average LS in Fig. 8c is 0.322%/V. Totally, Monte Carlo simulation results show a good robustness of the BGR to the process and fabrication errors.

Fig. 8
figure 8

Monte-Carlo simulation results of a generated reference voltage, b TC and c LS

Full size image

While the Monte Carlo simulation results in Fig. 8 show the robustness of the circuit against process variation, the exact value of generated Vref may vary from one process corner to another corner in Fig. 6. It is worth mentioning that in low power BGRs the impact of process deviation is often greater due to the exponential characteristics of subthreshold currents. However, if more accurate Vref at all process corners are required, using trimming techniques (like [23]) is mandatory. Actually trimming circuits [23] usually adjust Vref by sinking/sourcing additional current from/to the bandgap core. It is important to mention that, taking into account both the area requirements and the relatively minor deviation of this circuit compared to similar types of BGRs, this work opts not to employ any trimming circuitry.

The power spectral density (PSD) of the proposed BGR is shown in Fig. 9 for different load capacitances (CL). Although, due to the extremely low power consumption of the proposed circuit in the subthreshold region, it tends to exhibit poor noise performance, but the noise level of the circuit is still promising. According to the simulation results, noise of the circuit is 4 µV/\(\sqrt{Hz}\) at the frequency of 100 Hz for CL = 0.5 pF. As expected, higher value of CL results in lower noise power at the output. For example, the output noise of the circuit at frequency of 1 MHz, is 8.46, 4.26, 2.13 nV/\(\sqrt{Hz}\), respectively, for CL of 0.5, 1 and 2 pF. Apparently, the main source of low frequency noise (here < 100Hz) in BGRs is caused by flicker noise of MOS transistors, while the thermal noise is dominant at high frequencies (here > 100Hz).

Fig. 9
figure 9

Noise spectrum of proposed BGR

Full size image

Although the proposed BGR has a self-biased configuration and needs no start-up circuit, a conventional start-up circuit is used in Fig. 1 to accelerate the circuit’s transition to a normal operating state after power-up. Transient response of the reference voltage after power-up with and without start-up circuit is shown in Fig. 10. As seen, the start-up circuit reduces the start-up time from 10 ms to less than 2 ms and results in a faster start-up.

Fig. 10
figure 10

Start-up time of the circuit with/without start-up circuit

Full size image

The layout of the circuit has been optimized to utilize the minimum chip area. As shown in Fig. 11 the chip area of the BGR is as small as 480 μm × 840 μm.

Fig. 11
figure 11

Layout of the proposed circuit

Full size image

For comparison, the performance summary of the proposed BGR and some similar prior works are shown in Table 2. The performance of the circuit is amongst the best prior works.

Table 2 Performance summary of the circuit and some simillar prior works
Full size table

6 Conclusion

A low-power BGR has been developed that consits of three branches with nine MOS transistors and two resistors. All transistors have been biased in weak inversion region. The circuit generates a PTAT current by using the gate-source voltage difference of two MOS transistors. This current is then mirrored into the second and third branches and passed through a resistor to generate a PTAT voltage. This PTAT voltage is combined with the VGS of a diode-connected transistor (as a CTAT voltage) to generate the voltage reference. The circuit has been simulated and post-layout results confirm its performance. The post-layout simulation results demonstrate that the circuit produces a voltage reference of 644 mV with a TC of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. The line sensitivity of the circuit was measured 0.31%/V, indicating a minimal change in the voltage reference for power supply voltages ranging from 0.9 to 1.8 V. The PSRR of the proposed circuit is − 40dB within the frequency range of 1–100 Hz, Furthermore, the chip area of this circuit has been significantly reduced compared to similar designs. The simulation results demonstrate that the proposed circuit exhibits a good robustness against process, supply voltage and temperature (PVT) variations, making it a promising solution for ultra-low power applications.