1 Introduction

According to transistor size reduction which in turn leads to deca-nanometer regime, process variability due to the I.C. fabrication steps and statistical random variations due to intrinsic parameter fluctuations increase circuit vulnerability and causes precision and reliability issues in circuits [1,2,3]. Without having an exact model of these effects, designed circuits would not be guaranteed to follow their predicted performance. To make confidence about final performance of the circuit, the impact of these variations on circuit parameters should be considered in early design stage. This needs an accurate modeling of variation effects in order to achieve an accurate variability aware design [3,4,5].

Fabrication-induced variations have been identified as one of the most significant impediments for the IC design. The magnitude of these variations highly depends on the relevant IC technology process [4,5,6]. For instance with shrinking the transistor dimensions to 45 nm technology node and below, process variations make a significant rule in performance variability and eventually in diminishment of yield [7]. A significant amount of research has been carried out to characterize and model the device variability and to estimate its impact on circuit behavior and to develop new topologies and design techniques that can reduce the impact [8,9,10,11]. For a new technology appropriate modeling of these variations is necessary to predict the performance of the system. By shrinking the device dimensions, the magnitude of random variations increases [6]. Moreover it is possible to observe new variation sources. Thus, variation modeling, for both present and next generation technology is necessary.

Different number of modeling approaches presented by researchers, among them the Pelgrom’s model is one of the most basic models. In this model standard deviation (SD) of electrical parameters has an inverse square proportional with the active area of the device [8,9,10,11,12]. Scaling down the dimensions and advancements in technology causes new effects. Thus, this model is not reliable any more. Therefore, more accurate and complicated modeling is required to estimate these variations with an acceptable precision particularly in SRAM [13], ADC/DAC [14, 15], and amplifier circuits [16]. Authors in [17] presented an approach for statistical simulation and circuit performance-driven optimization of semiconductor technologies. Moreover, in [18], authors presented a reliability simulation framework that has been integrated with variability analysis. Authors in [19] have investigated the impact of statistical variability on the accuracy of a propagation delay time compact model. In model presented in [20], the impact of transistor mismatch on the design tradeoffs at the circuit level and some techniques that can break the mismatch imposed limits in certain applications in analog circuits are investigated. In model [21], comprehensive mismatch characterization data and analysis in deep-submicrometer have been investigated. Threshold voltage mismatch in nano-meter regimes has been investigated and modeled in [22].

Mismatch effects can be divided into two components: systematic and random. Systematic component arises from fabrication induced variations and it can be reduced by applying various techniques in layout design. The other one is random component whose the main variation sources are Random Discrete Dopants (RDD) [23], Line Edge Roughness (LER) [24], and Poly Gate Granularity (PGG) [25] which are all considered as intrinsic parameter fluctuations [1, 2, 26,27,28]. A list of electrical and physical parameters of the device is presented in Table 1. Mismatch effects has a significant impact on electrical parameters and cause variations in operating point, bandwidth, gain and other circuit’s main characteristics [4]. Authors in [29] presented a study on drain current mismatch by considering the threshold voltage and subthreshold swing fluctuations.

Table 1 Process and electrical parameters as presented in [4]
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The paper is organized as follows: in Sect. 2 analytical models of mismatch in short channel regime are reviewed. In the Sect. 3 the proposed algorithm is presented which is based on the introduction of appropriate variations in the channel length, width and input voltage of the gate in single stage amplifiers. In Sect. 4, the verification of the algorithm is carried out using single stage amplifiers. It means that the statistical behavior of the small signal parameters for common source, common drain and common gate amplifiers are modeled using the proposed method and their accuracies are evaluated. Finally, Conclusion is presented in Sect. 5.

2 Mismatch models

For modeling mismatch effects, the main variation sources should be identified. Dominant variations are physical parameter’s random variation of device. After identification of sources, they were historically formulated and calculated based on their SD variations. Their impact on electrical parameters of the circuits has been always in attention [28]. Pelgrom’s model is an analytical relation which models local and global variation. Variance of a parameter’s difference (ΔP) between two transistors with the same bias is given by [11]:

$$\sigma^{2} \left( {\Delta P} \right) = \frac{{A_{P}^{2} }}{WL} + S_{P}^{2} D$$
(1)

where A P and S P are technology-dependent parameters, W and L are channel dimensions, and D is the distance between two transistors. The current factor (β) and threshold voltage (V th ) commonly are used as mismatch modeling parameters [2, 11]. This model can be used for long channel transistors by prediction of variations down to channel lengths of 2 μm [3]. By scaling down dimensions into deca-nanometer regime and subsequent Short Channel Effects (SCE), the long channel variation models are not true at all and hence, more accuracy is required to model these variations. Two important manifests of SCE are velocity saturation and mobility degradation. Velocity saturation occurs when drain-source voltage is high enough to make a critical field in channel length (E C  = VDS,sat/L). Subject to this equation, VDS,sat is drain-source voltage in velocity saturation [30]. In fact drain current in short channel transistors enters saturation regime earlier than long channel ones because carrier’s velocity saturates (ν sat  = μ0E C ). The drain current relation in short channel transistor in the saturation regime, when the velocity saturation occurs, is expressed as [31]:

$$\begin{aligned} I_{DS} & = \nu_{sat} C_{ox} W(V_{GS} - V_{TH} ) \\ & = \beta (V_{GS} - V_{TH} )V_{DS,sat} \\ \end{aligned}$$
(2)

where C OX is the gate oxide capacitance per unit area, β defined as \(\beta\,\triangleq\,\mu_{0} C_{ox} W /L\) which μ0 is the low-field mobility of the carriers. Current mismatch (ΔI ds ) that is the difference between two identical transistor currents, based on variance of β and V TH , will be given by:

$$\begin{aligned}\Delta I_{DS} & = \frac{{\partial I_{DS} }}{\partial \beta }\Delta \beta + \frac{{\partial I_{DS} }}{{\partial V_{TH} }}\Delta V_{TH} \\ & = (V_{GS} - V_{TH} )V_{DS,sat} \cdot\Delta \beta - \beta V_{DS,sat} \cdot\Delta V_{TH} \\ \end{aligned}$$
(3)

where Δβ and ΔV TH are the differences between current factor and threshold voltage of two identical transistors. It can be shown that ΔI DS  = βVDS,sat·ΔV GS . Thus an equation for the modeling of the gate voltage mismatch as an offset voltage in the gate can be derived as presented in Eq. (4). This equation can be used to compensate the mismatch between 1000 identical transistors subject to intrinsic parameter fluctuations as presented in Fig. 1 [1].

$$\Delta V_{GS} = \frac{{V_{GS} - V_{TH} }}{\beta }\Delta \beta -\Delta V_{TH} .$$
(4)
Fig. 1: a
figure 1

Drain current mismatch between two identical transistors under same bias conditions, b compensation of mismatch with addition of appropriate voltage source in the gate of transistors, c I DS –V GS characteristics of 1000 identical transistors subject to mismatch with the inset histogram at a given point, d I DS –V GS characteristics of mismatch compensated transistors with the inset histogram at a given point [1]

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The other SCE, mobility degradation, happens when the gate voltage is higher than drain-source voltage. If V GS  − V DS  > 0.7 V, the effect of mobility degradation remarkably affects circuit performance [1]. To take this phenomenon into account in the drain current equation, effective carrier mobility (μ eff ) should be used in drain current equations which can be expressed as:

$$\mu_{eff} = \frac{{\mu_{0} }}{{1 + \theta (V_{GS} - V_{TH} )}} \approx \mu_{0} \left[ {1 - \theta (V_{GS} - V_{TH} )} \right]$$
(5)

where θ is the mobility degradation coefficient. Substituting Eq. (5) into Eqs. (2) and (4) gives:

$$\begin{aligned} I_{DS} & \approx \beta \left[ {1 - \theta (V_{GS} - V_{TH} )} \right](V_{GS} - V_{TH} )V_{DS,sat} \\\Delta V_{GS} & \approx \frac{{\left[ {1 - \theta (V_{GS} - V_{TH} )} \right](V_{GS} - V_{TH} )V_{DS,sat} }}{{V_{DS,sat} \left[ {1 - 2\theta (V_{GS} - V_{TH} )} \right]}}\frac{{\Delta \beta }}{\beta } -\Delta V_{TH} \\ & \approx \left[ {1 + \theta (V_{GS} - V_{TH} )} \right](V_{GS} - V_{TH} )\frac{{\Delta \beta }}{\beta } -\Delta V_{TH} . \\ \end{aligned}$$
(6)

3 Proposed method for mismatch modeling

Current circuit mismatch models use a series input voltage source (V GS ) to compensate the mismatch between identical transistors as shown in Fig. 1. However, these DC-compensated mismatch models are not accurate to predict variation of AC parameters of transistors. The aim of this paper is to analyze the mismatch in small signal parameters and model these variations in single stage amplifiers.

In the proposed method, modeling is carried out using appropriate channel length variations in the transistor under test. This makes sense in the first order because LER which is one of the important sources of variation as defined in Sect. 1, has a significant impact on the channel length. Hence, we need to use the HSPICE netlist and statistical information of the desired parameters as the input data according to Fig. 2. Statistical information contains standard deviation and mean value (average) of transistor parameters. Using mismatch models, the desired variation sources are calculated based on the first guess for the standard deviation of the channel length and input voltage.

Fig. 2
figure 2

Mismatch modeling approach

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As shown in Fig. 3, a variation source across the channel length (σL) is added to netlist. Then, the Monte Carlo simulations will be carried out in HSPICE and finally statistical information of important parameters will be extracted. We repeat this process by increasing σL, until the SD error of the voltage gain reaches to less than 10% (X is a set point or minimum value for SD error of gain voltage, and assume equal to 10% at the first). At the first step, voltage gain parameter will be analyzed, because the better this parameter get modeled, the less error other parameters will have in modeling. At the next step, we investigate the introduced error in other parameters. Considering target error of 5%, the algorithm decides whether to repeat previous step or enter to second. In the second loop a variation source will be added in series with transistor gate and then the error of important parameters will be extracted. Note that increasing σ(V GS ) affects operating region of the transistor. However, for the validation of our proposed algorithm with real data, as presented in Ref. [6], it can be seen that our obtained results for σ(V GS ) agrees very well with the corresponding value of σ(V TH ), roughly equal to 50 mV. Finally, the error of standard deviation of parameters will be faded by increasing each variation source. This process repeats two times, the first time will be continued with less than 10% error and the second time with less than 5%. It should be noticed that as technology advanced to decreased channel lengths, it is expected that the variation sources (σ(V GS ), σL) will be increased [6]. However, to evaluate the introduced error in our proposed algorithm in respect to accurate MC simulations, we need appropriate library of modelcards for that particular technology.

Fig. 3
figure 3

Proposed algorithm of mismatch modeling

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4 Evaluating the accuracy of algorithm

4.1 Common source amplifier

For a complete study on the modeling of the statistical variability in a common source amplifier, we use Fig. 4(a). Since devices with larger area cause less mismatch effects, to achieve maximum variations we adopt W = L = 35 nm. Using this topology, the intrinsic gain of the amplifier can be achieved. Small signal model of this configuration is shown in Fig. 4(b) where the gain is given by:

$$A_{V} = - g_{m} r_{ds} .$$
(7)
Fig. 4
figure 4

a Common source amplifier circuit under test, b its small signal model

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The bias point and small signal parameters are presented in Table 2. Now, using 1000 samples of BSIM4 compact model cards in 35 nm technology node for M1, we simulate the mismatch variation of parameters of the amplifier. The important parameters are extracted and the standard deviations are calculated. Based on the novel algorithm, statistical replication is carried out two times: first with a Gaussian source with 6 nm SD along transistor’s length and the second time with a 35 mV SD source in series with the gate-source voltage. Results of the statistical model are finally compared with atomistic model results and are represented in Table 3(a). It can be seen that results have less than 5% error for all important parameters of an amplifier. Moreover, number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm is represented in Table 3(b). This is while the required time for the MC simulations using atomistic library modelcards is approximately 20 min. It should be noticed that the computational time measurements are carried out on a CPU of Intel-Core i3-2.40 GHz and memory RAM of 4 GB.

Table 2 Common source amplifier parameters
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Table 3 (a) Results of the proposed mismatch model for the common source amplifier, (b) number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm
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For more detailed investigation, a resistor in parallel with the inductor used as the amplifier load as depicted in Fig. 5. Voltage gain of the circuit will be:

$$A_{V} = - g_{m} (r_{ds} ||R_{D} ) = - g_{m} R_{out}$$
(8)

where for R D  ≪ r ds , R out  ≈ R D . In this case, it is concluded that g m and R out are independent and the gain almost varies with g m variation because changes in R out values are negligible. By increasing R D , the correlation between g m and R out will increase as shown in Fig. 6. On the other hand, when R D is much higher than r ds , the gain fluctuations is close to intrinsic mode. Whereas correlation of g m and R out increases due to increase in R D , SD of R out and then variation of gain will be increased.

Fig. 5
figure 5

Common source amplifier with RD

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Fig. 6
figure 6

Correlation between g m and R out for various R D , insert is the scatter plots of g m versus Rout for R D  = 100 kΩ

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This circuit could be modeled using variation sources came from last circuit in intrinsic mode because both circuits have same bias current. Statistical simulations are carried out using various values of R D from 100 Ω to 1 MΩ and SD of gain and the output resistance is shown in Figs. 7 and 8. The highest error occurs when R D is too large which replicates close results with the amplifier in the intrinsic gain mode; however, for the smaller values of R D , the results obtained from the proposed algorithm are in better agreement with the atomistic simulation results.

Fig. 7
figure 7

SD of the voltage gain for various R D . The inset is the magnified figure for R D between 100 Ω to 1000 kΩ

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Fig. 8
figure 8

SD of output resistance for various R D . The inset is the magnified figure for R D between 100 Ω to 1000 kΩ

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4.2 Common drain amplifier

The second type of basic amplifiers studied here is the common drain or source follower amplifier. Unlike common Source amplifier which has a large gain, this configuration has a gain below one and usually is used as a buffer in analogue circuits. A source follower amplifier with an active load is shown in Fig. 9, where the element values and parameters of the amplifier are presented in Table 4.

Fig. 9
figure 9

Common drain amplifier

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Table 4 Common drain amplifier parameters
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The mean and SD of the transconductance, output resistance and gain are presented in Table 5(a). The comparison of obtained values with respect to most accurate atomistic simulation results gives less than 5% error in all cases. Moreover, number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm is represented in Table 5(b). This is while the required time for the MC simulations using atomistic library modelcards is approximately 20 min. For implementation of the proposed algorithm in this circuit a Gaussian voltage source with 6.1 nm SD in series with the transistor’s gate in addition of 82 nA SD current source in parallel with the drain current are used. In comparison to the results achieved from atomistic model, the average error stays less than 1% while the SD error will be less than 5%. Moreover, the histogram graphs of the desired parameters including transconductance (g m ), output resistance (R out ), and voltage gain (A v ) are illustrated in Fig. 10.

Table 5 (a) Results of the proposed mismatch model for the source follower amplifier. (b) Number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm
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Fig. 10
figure 10

Histogram of variations for a transconductance (g m ), b output resistance (R out ), and c voltage gain (A v ) of common drain amplifier. The red bins represent most accurate results from ‘Atomistic’ model and blue bins are obtained from the proposed model (Color figure online)

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4.3 Common gate amplifier

The final configuration studied here is the common gate amplifier. Unlike common source and source follower amplifiers where the input signal triggers the gate, in this configuration, the input signal triggers the source and the output is taken from the drain. Meanwhile, this configuration is used in complex amplifiers like chain configuration that improves the bandwidth.

Sample circuit in Fig. 11(a) is used to study the mismatch in this amplifier. Drain current is adjusted with V com in the gate. Based on the small signal circuit shown in Fig. 11(b), the circuit gain will be given by:

$$A_{V} = \frac{{(g_{m} + g_{mb} )r_{ds1} + 1}}{{r_{ds1} + (g_{m} + g_{mb} )r_{ds1} R_{s} + R_{s} + R_{D} }}R_{D}$$
(9)

where g m is transistor transconductance, g mb is transconductance of transistor bulk and rds1 is drain-source resistance of transistor M1. The parameter and element values are presented in Table 6.

Fig. 11
figure 11

a Common gate amplifier, b its small signal model

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Table 6 Common gate amplifier parameters
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Modeling is carried out with a 5.82 nm SD Gaussian source along transistor length and a 45.5 mV SD Gaussian source in series with the gate. The results are compared with the most accurate atomistic model and it can be concluded again that the error values are less than 5%, as presented in Table 7(a). Moreover, number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm is represented in Table 7(b). This is while the required time for the MC simulations using atomistic library modelcards is approximately 20 min. Note that the voltage gain has a very low error and it is basically one of parameters that are usually close to desired value in atomistic model. This is due to the fact that this parameter is used as a target parameter in the proposed algorithm. Figure 12 shows the histogram graphs related to the variation of transconductance (g m ), output resistance (R out ), and voltage gain (A v ) of the common gate amplifier.

Table 7 (a) Results of the proposed mismatch model for the common gate amplifier. (b) Number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm
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Fig. 12
figure 12

Histogram graph of variations of a transconductance (g m ), b output resistance (R out ), and c voltage gain (A v ) of common gate amplifier. The red bins represent most accurate results from ‘Atomistic’ model and blue bins are obtained from the proposed model (Color figure online)

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5 Case study

In order to evaluate the performance of mismatch algorithm, case studies are common practice as presented in [32, 33]. However, since our proposed algorithm is suitable for replicating AC parameter variations of analogue amplifiers, we perform two case studies in more complicated cases. First, we investigate a 5-transistor Op-Amp with active load and second, we study the phenomenon when the number of matched transistors increases.

Figure 13 illustrates the schematic of a 5-transistor CMOS OP-Amp with active load. Modeling is carried out with a 3.8 nm SD Gaussian source along transistor length and a 48 mV SD Gaussian source in series with the gate. The results are compared with the most accurate atomistic model and it can be concluded again that the error values are less than 4%, as presented in Table 8(a). Moreover, number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm is represented in Table 8(b).

Fig. 13
figure 13

Schematic of a 5-transistor Op-Amp with active load

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Table 8 (a) Results of the proposed mismatch model for the Op-Amp. (b) Number of computational cycles and time to reach less than 10% error in the first stage and less than 5% error in the second stage of the proposed algorithm
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Figure 14 depicts the schematic of a common source amplifier consisting of a higher width nMOS transistor. To evaluate its performance in respect to mismatch, we convert the wider transistor to a number of parallel basic width transistors as shown in this figure. Then, we investigate the error introduced in the mean and SD of this amplifier using our proposed algorithm in respect to MC atomistic simulations. It can be seen that by increasing the number of matched transistors, the gain variability (SD/mean) is decreased as the fluctuations of parallel transistors compensate each other. Moreover, the introduced error in the SD of gain remains less than 3% as presented in Table 9.

Fig. 14
figure 14

Schematic of a common source amplifier employing wider width nMOS transistor equal to parallel combination of basic width transistors

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Table 9 Results of the proposed mismatch model for the circuit shown in Fig. 14
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6 Conclusion

Previous researches in the field of mismatch models have been focused on the modeling of DC parameters of the device with the aid of approaches such as addition of an offset voltage in series with the gate of the MOSFET transistors. Although these approaches could be used in a specific technology and results in modeling of electrical parameters with high precision, but for the purpose of replicating variations in AC parameters, there cause large errors particularly in deca-nanometer and ultra-short channel regime. Using accurate statistical BSIM4 modelcards, we have been able to extract distributions for the AC parameters such as transconductance (g m ), output resistance (R out ), and the voltage gain (A v ) of a single stage amplifier. The results demonstrated that the accuracy of the algorithm is high and the introduced error stays less than 5% compared with the most accurate Monte Carlo atomistic simulations. Two circuits have been  investigated as case studies to confirm the applicability of our proposed algorithm in more complicated circuits including an OP-amp and an amplifier employing parallel combination of basic width transistors.