Model-Based Variation-Aware Integrated Circuit Design

Abstract

Modern integrated circuit designers must deal with complex design and simulation problems while coping with large device to device parametric variations and often imperfect information. This chapter presents surrogate model-based methods to generate circuit performance models for design, device models, and high-speed input-output (IO) buffer macromodels. Circuit performance models are built with design parameters and parametric variations, and they can be used for fast and systematic design space exploration and yield analysis. Surrogate models of the main device characteristics are generated in order to assess the effects of variability in analog circuits. The variation-aware IO buffer macromodel integrates surrogate modeling and a physically based model structure. The new IO macromodel provides both good accuracy and scalability for signal integrity analysis.

1 Introduction

As integrated circuit (IC) technology continues to scale down, process variations become increasingly critical and lead to large variances of important transistor parameters. These large process uncertainties have caused significant yield loss. In addition, environmental variations (such as changes in supply voltage and temperature) and reliability issues contribute to further yield reduction and make it more challenging to create a reliable, robust design. In coping with these problems in circuit design, it is important to consider the effects of variations in circuit modeling and design analysis at an early stage. However this is a nontrivial task. In this chapter, surrogate modeling is applied to handle the complexities in variation-aware circuit macromodeling, model-based design optimization, high-speed IO macromodeling and device modeling. This chapter presents the advantages of using surrogate modeling in enhancing the accuracy, flexibility, and efficiency in those applications.

2 Circuit Performance Modeling and Design Optimization

2.1 Overview

Today circuit designers are confronted with large design spaces and many design variables whose relationships must be analyzed. In this situation, tasks such as sensitivity analysis, design space exploration, and visualization become difficult, even if a single simulation takes only a short period of time. The analyses are becoming impractical, as some of the circuit simulations are computationally expensive and time-consuming. In addition a designer must not only search for the optimal design with the nominal conditions, but must also carefully consider the circuit robustness in the presence of variations. However, the fulfillment of all these requirements introduces more complications in circuit design. One way to reduce design complexities and costs is to build performance models which can be used as replacements for the real circuit performance responses.

In the approach described here, performance models are built by directly approximating circuit performance parameters (e.g., S-parameter, gain, power consumption, and noise figure) with design variables (e.g., transistor size, bias voltage, and current) and parametric variations (e.g., V _th, t _ox, L _eff) and then these models are used to drive the design. The modeling concept is illustrated in Fig. 1. This method is data-driven and black-box by nature, and thus it can be applied to a wide range of circuit design problems. When performance models are available, it is possible to explore the design space with these cheap-to-run performance models. This could help provide circuit designers with a better understanding of the design problem. Performance models can also help designers to better formulate the design problems with virtualization, sensitivity analysis, and optimization.

Fig. 1

Circuit performance modeling

2.2 Performance Model Construction

Technique Approaches

Global surrogate modeling [1] is used to create performance models with good accuracy over the complete design space. This is different from building a local surrogate model for the purpose of optimization [2, 3].

Surrogate modeling accuracy and efficiency are determined by several key steps including the sampling plan, model template, and validation.

The first step is determination of a sampling plan. A good sampling plan decides how to efficiently choose samples for fitting good models, considering that the number of samples is limited by the desire to constrain computational expense. Recently, adaptive sampling techniques were developed in order to achieve better efficiency in sampling [4, 5]. These techniques analyze the data from previous iterations and select new samples in the areas that are more difficult to fit.

The model template selection step determines the surrogate model type and model complexity. Multiple popular surrogate model types are available, including rational functions, Kriging models, radial basis function (RBF) models, artificial neural networks (ANNs), and support vector machines (SVMs) [4, 6]. All of these methods can have an embedded analytic coarse model. The model complexity is controlled by a set of hyperparameters which would be optimized during a modeling process.

The model validation step establishes the predictive capabilities of the models and estimates their accuracy. One popular method is fivefold cross-validation [4, 6] in which the training data are divided into five subsets. A surrogate model is then constructed five times: each time four subsets are used for model construction and one subset is used for error measurement. The model error can be measured as an absolute error, e.g., maximum absolute error (MAE), or a relative error, e.g., root mean square error (RMSE), root relative square error (RRSE), and Bayesian estimation error quotient (BEEQ).

Automatic Modeling Flow

Figure 2 presents an automatic modeling flow that is able to generate performance models from transistor-level circuit simulations. Before the modeling starts, sets of input and output parameters are defined. The modeling techniques are also configured, including the model template, adaptive sampling strategy, and accuracy measurement. An accuracy target is defined as well. At the beginning of the modeling process a small set of initial samples are generated. Then transistor-level Simulation Program with Integrated Circuit Emphasis (SPICE) simulations are performed using this initial set, and the corresponding responses are collected and used as the modeling data. Surrogate models are then constructed and their parameters optimized. The model accuracy is measured, and the optimization continues until only negligible improvements can be made by changing the model parameters. If the desired accuracy is not reached, the adaptive sampling is evoked to add a new set of samples. The process continues until the fit reaches the targeted accuracy. When the process finishes, the model expressions are exported and used in the follow design steps.

Fig. 2

Automatic adaptive circuit performance surrogate modeling flow

In the examples presented in this section, the modeling techniques are explored using the SUrrogate MOdeling (SUMO) Matlab Toolbox [7]. SUMO is a plug-in based, adaptive platform that can be customized flexibly. The toolbox makes it feasible to test a variety of modeling techniques. Transient circuit simulators, including Cadence Virtuoso Spectre^® and Synopsys HSPICE^®, are used here for performing transistor-level circuit simulations.

2.3 Surrogate-Based Design and Optimization

Once the surrogate models are constructed, it is possible to explore the multidimensional design space by plotting the model surfaces. The design space set by different design parameters and parametric variation values can be conveniently explored. By using the models it is possible to quickly estimate design feasibility. It is also feasible to compute global sensitivity using the models, and to obtain the relations among factors such as the performance versus the design parameters, the performance versus the variation parameters, and the correlation among the design and variation parameters.

Surrogate models can be integrated to enable global circuit optimization which requires a great number of iterative evaluations of objective functions. In the surrogate-based optimization process there are generally two types of simulation models: a low-fidelity and a high-fidelity model. In circuit design problems the transistor-level circuit simulation is used as a high-fidelity model while the constructed surrogate model is used as the low-fidelity model. Figure 3 shows a general surrogate-based optimization process for circuit design. This method can accommodate additional samples chosen as the optimal design is approached, with the guidance of the existing surrogate model based on past samples [3]. As the surrogate model is used as a guide for adaptive sampling, model accuracy is enhanced with a higher density of samples near the optimum design. Some optimization flows do not involve model updating. Therefore, a global surrogate model is fitted and used as a surrogate for the expensive functions. This method requires high-fidelity surrogate models and uses a relatively large number of samples to build the models. Adaptive sampling can also be used during initial model construction, to obtain better sampling efficiency.

Fig. 3

Surrogate-based optimization flow

2.4 Application Case: Self-Calibrated Low Noise Amplifier Design

This section presents self-calibrated circuit design with application of the surrogate-based performance modeling and model-based optimization.

Recently, post-silicon calibration techniques have been used to compensate for the impact of process-voltage-temperature (PVT) variations on analog and RF circuits [8, 9]. With appropriate design, the circuits are capable of self-calibrating their performance. However, a general design infrastructure and the tools to assist a self-calibrated design are unavailable. Without a general design method, it takes much ad hoc work to realize such an adaptive design.

Recently, a new design approach was developed for designing cost-effective self-calibrating analog and RF circuits [10]. The key idea is building multiple operating states to compensate for large PVT variations. In particular, each operating state tolerates a specific range of variations. In circuit implementation a set of design parameters are selected to construct the operating states, and their values for each state are determined at the design phase. A surrogate model-based design flow was developed to select these effective design parameters and to design the optimal operating states.

This section presents a self-calibrated low noise amplifier (LNA) circuit design using this new design approach. The 12 GHz LNA design with the simplified circuit schematic shown in Fig. 4 was implemented in a 65 nm CMOS process. The LNA employs a cascode structure which is composed of a common-source amplifier stage followed by a common-gate amplifier stage. A negative g _m cell is used in the load. The supply voltage is 1.2 V. The specifications of interest are voltage gain, noise factor (NF), |S ₁₁|, and power. Table 1 lists the nominal performance and design specifications. Two key bias voltages, the input bias voltage V _g and tail bias voltage V _c in the negative g _m cell, are selected as the tunable design parameters for self-calibration. These bias voltages are chosen as they provide critical control over the performance of interest and introduce low area overhead. To ensure that the transistors are working in the correct operating regions, the tunable bias V _g has the range 0.58 V to 0.8 V and V _c has the range 0.58 V to 1.0 V. As a design choice, the bias voltages V _c and V _g can be tuned in 10 mV steps, provided by the voltage generator, indicated in Fig. 4.

Fig. 4

Simplified schematic of the low noise amplifier (LNA) circuit [10]

Table 1 Performance specifications (center frequency=12 GHz) [10]

In this case, we consider transistor threshold voltage variation ΔV _th as the main process variation and assume that ΔV _th has a normal distribution with 3σ=15 %. Temperature is considered as an additional environmental variation and is in the range of −10 ^∘C to 80 ^∘C. The variation space is uniformly partitioned into 36 subregions. This requires that each operating state be able to tolerate 5 % threshold voltage variation and 15 ^∘C temperature change.

Model Construction

The automatic modeling process discussed in Sect. 2.2 was used to construct the performance models. A Kriging model [4] was selected as the model template. The Gaussian correlation function and a linear regression were used in the kriging model construction. The hyperparameters of the models were optimized using a genetic algorithm [7] suitable for the cases where little problem specific information can be explored.

An initial optimized Latin hypercube design [4] of size 24 was used augmented with the corner points. New samples were selected using the adaptive sampling algorithm with a combination of LOLA-Voronoi [5] and error-based sampler. LOLA-Voronoi is a highly adaptive sampling algorithm which performs a trade-off between exploration (filling up the design space as equally as possible) and exploitation (selecting data points in highly nonlinear regions). Error-based sampling is driven by the evaluation of the model on a dense grid, and this algorithm selects samples in the locations where the model error is estimated to be the largest. Fivefold cross-validation [4, 6] was used to assess the model accuracy. In addition to the training set, a separate data set of 500 samples was available for validation purposes. This data set was sampled by Latin hypercube design and was not used in training the models. The model accuracy was measured using the root relative square error (RRSE) and maximum relative error (MRE).

Figure 5 shows the slice plot of the performance model |S ₁₁|(V _g,V _c,P,T). The sample numbers and the achieved accuracy are listed in Table 2. The results show that the modeling cost is dominated by |S ₁₁| modeling, as its response is strongly nonlinear.

Fig. 5

Slice plots of performance response |S ₁₁|. The three slices in each plot are for three temperatures: 80 ^∘C, 45 ^∘C, and −10 ^∘C

Table 2 LNA performance modeling samples and accuracy measurement with RRSE and MRE [10]

Model-Based Design

The design objective is to minimize the performance deviations from the nominal performance. The design objective function is defined as follows:

$$ \begin{array}{l} \mbox{Minimize}\quad \varPhi (\mathbf{X},\mathbf{V}) = \big\| f_{1}(X,V),f_{2}(X,V),f_{3}(X,V),f_{4}(X,V) \big\|_{2}\\\hphantom{\mbox{Minimize}\quad} f_{i}(\mathbf{X},\mathbf{V}) = \displaystyle\frac{P_{i}(X,V) - P_{i\_\mathrm{norm}}}{P_{i\_\mathrm{norm}}},\quad i=1, 2, 3, 4 \end{array} $$

(1)

where P _i is one of the performance parameters |S ₁₁|, gain, NF, and power, as selected by the index i. P _{i_norm} is the ith nominal performance. X is the vector of the tunable design parameters, i.e., bias voltages V _g and V _c. V is a set of variation conditions used for validation.

Design Results

As the tunable bias voltages are discrete variables, a grid search is used with the performance surrogate model and the derived operating states. Figure 6 shows |S ₁₁| performance responses of the nominal design and of the self-calibrated design. Figure 6a shows that when the design parameters are set to their nominal values, only a limited number of the subregions are able to meet specifications. Figure 6b shows that when the tunable parameters for the optimal design are set in each sub-region, all of the sub-regions are able to meet the performance constraints.

Fig. 6

Plot of performance response |S ₁₁|: (a) the nominal design, (b) the self-calibrated design [10]

Validation

The results are validated using transistor-level Monte Carlo simulations. It is assumed that ΔV _th has a normal distribution with a 3σ of 15 % and a uniform temperature distribution from −10 ^∘C to 80 ^∘C. Note that the process variations are bounded by ±3σ. The results after calibration were generated using the precomputed optimal operating states for the subregions. The circuit performance was analyzed by running 1,000 Monte Carlo simulations. Tables 3 and 4 list the performance mean (μ), standard deviation (σ), and yield. As the results show, the performance degradation is fully compensated and thus the final circuit is able to meet specifications.

Table 3 LNA performance calculated using transistor-level simulations of the nominal design and the self-calibrated design [10]

Table 4 LNA performance yield calculated using transistor-level simulations of the nominal design and the self-calibrated design [10]

In summary, the method designs multiple operating states in the LNA circuit in order to compensate for extensive process and temperature variations. By considering both performance constraints and variation tolerance at the design stage, the circuit is able to calibrate performance responding to the variations. A surrogate-based process is constructed to obtain the optimal operating states. Surrogate modeling technologies approximate the circuit performances as a function of design parameters and parametric variations using the results of detailed circuit simulations obtained using a small number of samples. Thus, it efficiently assists design analysis and optimization. The results show that the new design method reduces performance distribution and significantly improves the circuit yield.

3 Accurate and Scalable IO Macromodel

Macromodels of input/output (IO) circuits are essential for fast timing, signal integrity, and power integrity analyses in high-speed digital systems. The most popular approach to IO modeling is to use the traditional table-based input-output buffer information specification (IBIS) [11]. IBIS models are simple, portable, IP-protected, and fast in simulations. However, they are unable to simulate continuous process-voltage-temperature (PVT) variations and are unsuitable for statistical analysis. This section describes a new type of macromodel, called the surrogate IBIS model, to solve this problem [12]. In the new method, an equivalent circuit structure is used to capture the static and dynamic circuit behaviors, while surrogate modeling is used to approximate each element over a range of PVT parameters, so that the macromodel is able to dynamically adapt to the PVT variations in analysis. Figure 7 shows the structure of the surrogate-based IBIS model. I _pu and I _pd represent the nonlinear output current. Time-variant coefficients K _pu and K _pd determine the partial turn-on of the pull-up/down networks during switching transitions. C _power and C _gnd represent the nonlinear parasitic capacitance between the output and the supply rails. Surrogate models of these model elements are constructed to capture the effects of supply voltage, terminal voltages, semiconductor process, and temperature.

Fig. 7

Structural IO buffer macromodel template with surrogate model elements [12]

3.1 IO Macromodel Construction

The automatic modeling process described in Sect. 2.2 can be used to construct surrogate models for the model elements in Fig. 7. Here modeling data extracted from transistor-level SPICE circuit simulations is used. Figure 8a shows the circuit test-bench used to extract the pull-up output current I _pu (V _S, V _pu, T, ΔV _th). The parameter V _pu is defined as the voltage difference between the power supply rail and the output, and it ranges from −V _CC to +2V _CC, covering the maximum reflection case [13]. Transient simulations are performed, and the simulation time must be long enough to record a stable output current I _pu. Similarly, the pull-down current model I _pd was extracted by turning on the pull-down network and turning off the pull-up network. I _pd was extracted as a model function of PVT variations and V _pd, where V _pd is defined as the voltage difference between the output and the ground.

Fig. 8

Test-benches for extracting model elements: (a) pull-up current I _pu, (b) output capacitance C _gnd and C _power [12]

The data was used to fit rational function models in the form

$$ f(X) = \frac{P(X)}{Q(X)}, $$

(2)

where P and Q are polynomial functions in X={x ₁,x ₂,…,x _n }, and Q is nonzero. P and Q have no common factor of positive degree.

The test setup for extracting the output parasitic capacitance is shown in Fig. 8b. An AC signal is attached to the output ports, and the imaginary currents in the power and the ground ports are measured. The capacitances C _power and C _gnd were derived using Eq. (3):

$$ C_{\mathrm{power}} = \frac{\Im (I_{\mathrm{VCC}})}{2\pi fV_{\mathrm{AC}}},\quad \mbox{and}\quad C_{\mathrm{gnd}} = \frac{ - \Im (I_{\mathrm{gnd}})}{2\pi fV_{\mathrm{AC}}}, $$

(3)

where ℑ(I _VCC) and ℑ(I _gnd) are the imaginary parts of the measured currents, f is the frequency of the AC source, and V _AC is the AC voltage amplitude.

The time-variant transition coefficients K _pu and K _pd were obtained using the 2EQ/2UK algorithm [14]. Figure 9a shows the test to obtain the switching output voltage waveforms. A simplified circuit to illustrate the 2EQ/2UK algorithm is shown in Fig. 9b. The switching output voltage waveforms wfm₁ and wfm₂ were obtained for different terminal voltages V _term, and the unknown coefficients K _pu and K _pd were derived using the equations

$$ K_{\mathrm{pu}}(t)I_{\mathrm{pu}}\bigl(V_{\mathrm{wfm}_{1}}(t)\bigr) - K_{\mathrm{pd}}(t)I_{\mathrm{pd}}\bigl(V_{\mathrm{wfm}_{1}}(t)\bigr) - I_{\mathrm{out}} = 0 $$

(4)

and

$$ K_{\mathrm{pu}}(t)I_{\mathrm{pu}}\bigl(V_{\mathrm{wfm}_{2}}(t)\bigr) - K_{\mathrm{pd}}(t)I_{\mathrm{pd}}\bigl(V_{\mathrm{wfm}_{2}}(t)\bigr) - I_{\mathrm{out}} = 0, $$

(5)

where I _out=(V _out−V _term)/R _load. I _pu and I _pd are the output current models.

Fig. 9

(a) Test-benches for extracting rising/falling transition waveforms for K _pu and K _pd. (b) Illustration of 2EQ/2UK algorithm [12]

The new model can be implemented in the Verilog-A behavioral version of the IBIS model [15], in which the surrogate models are implemented in the form of analog functions.

3.2 Example

This section presents the macromodeling of a single-ended output buffer circuit with the new method. Figure 10 shows the circuit designed in the 180 nm CMOS process with a 3.3 V nominal supply voltage. The threshold voltage variations ΔV _th in the MOS transistors are considered as the main process variations, and they are assumed to be within ±20 % of the nominal value V _th0. The parameter P=ΔV _th/V _th0 is used to describe the threshold voltage variation. The supply voltage V _s is assumed to fluctuate within ±30 % of the nominal supply (3.3 V), and the temperature (T) is set in the range of 0 to 100 ^∘C. In the modeling process, those PVT-related parameters are sampled adaptively in their ranges.

Fig. 10

Simplified buffer circuit and test setup for validation [12]

The generated surrogate IBIS model is compared to the reference provided by the transistor-level simulation, and to the traditional IBIS model extracted from SPICE using the S2IBIS3 v1.0 tool [16].

The test setup is shown in Fig. 10 where the driver is connected to a 0.75-m long lossy transmission line (RLGC model) with a loading resistor. The characteristic impedance of the transmission line is 50 Ω. The loading resistor is 75 Ω. Two test cases were examined. The results are shown in Fig. 11.

• 1. Case 1: This case has a 250 MHz square wave as the test input signal. The input data has the pattern “01010” with a 0.1-ns rise/fall time and 2-ns bit period. The supply voltage varies from 2.8 to 3.8 V.

• 2. Case 2: This case has a data pattern with a 1,024-bit-long pseudorandom bit sequence (PRBS) with 2-ns bit time. The power supply voltage is constant.

The accuracy of the macromodels is quantified by computing the timing error and the maximum relative voltage error. The timing error is defined as the time difference between the reference and the macromodel voltage responses measured for crossing half of the output voltage swing. The maximum relative voltage error is defined as the maximum error between the reference and macromodel voltage responses divided by the voltage swing.

Fig. 11

Output voltage at the far end of the transmission line. (a) Case 1, black solid line—transistor model, gray solid line—traditional IBIS, black dashed line—proposed surrogate IBIS. Black dash-dotted line—supply voltage. (b) Case 2, gray solid line—transistor, black dashed line—macromodel [12]

The results for Case 1 show that when there is a large variation of the supply voltage, the surrogate IBIS model has much better accuracy for both the timing error and the relative voltage error than does the traditional IBIS model. The maximum timing error of the surrogate IBIS model is 79 ps, and the maximum relative voltage error is 6.77 %. The surrogate IBIS model achieves the improved accuracy by capturing the complex output capacitance characteristics and the effects of the supply voltage and gate modulation effects on the output current [17].

In Case 2, the results show that the surrogate IBIS model achieves good accuracy. In this case the maximum timing error is 70 ps (3.5 % of the bit time) and the maximum relative voltage error is 6.45 %. An analysis of the eye diagram of the output in Case 2 is a further test of model fidelity. The eye width (W) was measured when the eye height (H) was equal to 1 V. The results under different PVT conditions show that the eye-width differences are within 0.04 ns (2 % of the bit time).

In summary, the proposed surrogate IBIS macromodel achieves good accuracy in analysis. The macromodels obtained show good accuracy in capturing the effects of reflections and variations, and their scalability enables flexible design analysis.

4 Surrogate-Based Device Modeling

Scaling of device sizes induces high variability of transistor parameters. There are two major reasons for this. First, quantum mechanics-based phenomena such as drain-induced barrier lowering (DIBL) or gate tunneling, which are negligible in long-channel devices, become more significant. Additional physics-based effects increase the dependence of many circuit design quantities (including the drain current, I _ds, and device transconductance, g _m) on transistor process parameters such as the oxide thickness, t _ox. Furthermore, the tolerances of semiconductor manufacturing components do not scale down as the transistor sizes shrink [18]. As a consequence, the amount of uncertainty of the design quantities remains constant as device sizes become smaller, leading to higher percentage variability with respect to the nominal values of the transistor process parameters. The experimental data revealed that a traditional process corner analysis might not reflect the real distribution of the critical transistor parameters such as the threshold voltage V _th [19], while the Monte Carlo analysis becomes more computationally intensive with the increasing number of variability factors.

The response surfaces of design quantities, which become more complex with the process variations, can be accurately captured by surrogate modeling. Surrogate modeling aims to express the output quantity in terms of a few input parameters by evaluating a limited number of samples. These samples are used by the basis functions which establish the response surface of the desired output. The coefficients of the basis functions for the response surfaces should be optimized to minimize modeling error. This approach has been applied to the problem of I _ds modeling in order to assess the effects of variability in analog circuit building blocks, in particular, for differential amplifiers [20]. In this section, the modeling of g _m of n-channel transistors will be discussed.

The transconductance g _m is an important quantity for analog circuits, particularly in determining the AC performance of amplifiers, mixers, and voltage-controlled oscillators. The modeling here is based on 65 nm device technology (IBM 10SF design kit) and uses six process parameters (t _ox, intrinsic threshold voltage V _th,0, intrinsic drain-source resistance R _ds,0, intrinsic mobility μ ₀, channel length variation ΔL _eff, and channel doping N _ch) as input to the model in addition to the terminal voltages of the transistor (gate-source voltage V _gs, drain-source voltage V _ds, and bulk-source voltage V _bs) and the temperature T. The choice of these process parameters is based on their physical origin, which ensures a weak correlation between each parameter. The I _ds equations of the BSIM model are analytically differentiated to yield g _m [21]:

$$ g_{\mathrm{m}} = \partial I_{\mathrm{ds}} / \partial V_{\mathrm{gs}}. $$

(6)

The g _m expression is validated by extensive SPICE circuit simulations over the process corners and at temperature extremes so that it can be used to evaluate the samples, each a function of the ten parameters described above. Although an analytic equation for g _m is used in this work, the modeling methodology is general and can employ simulations or measurement results if they have the same input and output parameters.

Kriging basis functions are used to construct the surrogate model, and the necessary coefficients are optimized using the MATLAB toolbox Design and Analysis of Computer Experiments (DACE) [22]. The device width is assumed to be 10 μm. The final model is tested for accuracy using the root relative square error (RRSE) metric [4, 6].

The g _m model was constructed using a total number of 2,560 input samples and tested with 6,400 samples not part of the set of input samples used in developing the model. The resulting model yields an RRSE of 3.96 %, indicating a high level of accuracy.

The model can be used to observe the changes in g _m with respect to its input parameters. Examples of this are provided in Fig. 12. The graphs provide critical insight to the designer about the fundamental relations and trade-offs between the chosen process parameters, terminal voltages, and temperature. Higher g _m values are obtained with smaller V _th0, L _eff, and t _ox, as well as larger μ ₀. This information becomes especially vital when variability of the circuit performance that depends on g _m must be considered. In the example of an RF cascode LNA, the voltage gain A _v, input and output scattering parameters S ₁₁ and S ₂₂, as well as the optimum noise impedance Z _opt are complex functions of the g _m value of the common source transistor [23]. Any variability of the process parameters of this transistor may push the design outside of the specification range. In this case, the information presented in Fig. 12a–c can be used to change the matching network of the amplifier such that it can yield the desired design metrics in all cases of process variability.

Fig. 12

3D graphs showing the trade-offs between the different inputs on the modeled g _m. (a) inputs are μ ₀ and V, (b) inputs are Leff and t _ox, (c) inputs are V and T

Finally, note that surrogate model-based device modeling is not limited to a single design quantity. Response surface models of other important design metrics can also be developed by using the methodology described here. As an example, consider the bandwidth of a single-stage amplifier. The bandwidth is a function of both the process parameters used in g _m modeling and of the parasitic capacitances of the transistors. However, these capacitances also depend on some process parameters. The exact relationships can be quantified by analytical expressions as given in the device model equations [21]. Once the additionally required parameters are determined, then the surrogate modeling process can be applied as in g _m modeling.

It should be kept in mind that the main premise of using surrogate models in device modeling is both to enhance the computational efficiency and to provide the designer with insight about the relation of the process parameters and circuit outputs. With respect to the first goal, Monte Carlo methods have been traditionally applied to describe the output variation of circuits. However, Monte Carlo methods require a very large number of samples to be simulated to yield meaningful relations between the process parameters and circuit parameters. Surrogate models can be used to replace Monte Carlo methods by building a response surface model representing the circuit outputs in terms of the input parameters and using it instead of the actual simulations to determine the effects of process variations. Thus, the computational cost will be reduced considerably.

The second goal, which tries to identify the impact of die-to-die and within-die variations on circuit outputs, has been achieved using application-specific process cards that are generated to satisfy different levels of process variations leveraging from device-level measurements [24]. This method accurately indicates the level of variations in the circuit outputs, but it does not really show how within-die variations can alter the circuit output. Additionally, designers must use multiple different process cards to check the performance variations, which can result in conflicting recommendations to be implemented in design. Surrogate models aim to unify the information regarding the process variations in a single model. The designer can then use this model to visualize both the die-to-die and within-die variations by evaluating different devices with distinct process parameters that are not necessarily specified by a process card.

5 Conclusions

This chapter presented applications of surrogate modeling to variation-aware circuit macromodeling and design analysis. Surrogate modeling facilitates efficient design exploration and optimization with variation-aware performance models. An example was provided that showed that surrogate modeling can be used to enhance the accuracy and scalability of IO macromodels. Moreover, the surrogate model-based method is able to generate device models with critical variability parameters. The surrogate-based method greatly reduces the complexities and costs of variation-aware macromodeling and circuit design.