1 Introduction

In modern communications systems, there is a need of low power and high performance integrated circuits (ICs) to observe wide range of bandwidth in accord with high gain. Additionally, in wireless technologies, the need of high switching speed and synchronization can be achieved with high speed clock signals [1, 2]. Ring oscillator has the capability of producing high speed clock signals along with high bandwidth [2]. Additionally, recent trends in VLSI design require low power optimized ICs for modern internet of thing (IoT) applications [3, 4]. However, the backbones of the high density ICs are Si MOSFETs, as each IC is made up of millions of MOS transistors. So, it is a primary requirement that the available MOS technology should provide the necessary and efficient performance after integration with such ICs.

Moreover, to construct better digital world and improve the quality of the device and user experience, the scaling of the transistors have been continuously done, while increasing performance and reducing power consumption [5, 6]. The endless scaling of MOS device beyond nano meters has affected the device performance and resulted in various short channel effects (SCEs) like, DIBL, off-state tunneling, etc. [6]. So, there is a need to overcome the device reliability issues with conventional Si MOSFETs. Various researches have been done and technologies have given resolution in the device design at nano meters dimensions like FinFET, SOI, and Recessed S/D, etc., Saremi et al. had discussed the attractive features of FinFET-based MOS structures in nano meter regime [7]. Additionally, some of complex structures had also been proposed like, surrounding gate MOSFET [8].

However, channel density problems associated with the conventional structures have been precisely overcome by the un-doped channel concept in SOI technology [9, 10]. Moreover, FD SOI technology has been reported as a most promising technology to overcome these problems and seen as an alternative technology due to its high performance constraints and simplest fabrication processes [11,12,13,14,15,16,17]. Young had come with the very first model for FD SOI MOSFET and discussed the advantages of this technology [11]. In continuation, Suzuki et al. had also described the perspective of buried oxide to off-flow the leakages in sub-threshold region through analytical model [12]. Nakajima et al. had discussed the strategy of thin BOX optimization over the performance of SOI MOSFETs [13]. Cheng et al. suggested that FD SOI has become a possible technology not only for continued CMOS scaling to 22 nm node, but also for enhancing the performance of legacy technology when rendering to old technology nodes [14]. Mishra et al. proposed a new concept of modified source in designing of FD SOI MOSFET to enhance the electrical characteristics of the device at 50 nm gate length [15]. In this, two levels of source doping have been introduced in source region. In continuation, Srivastava et al. has given the analytical model for this source modification in the design of FD SOI MOSFET to authenticate the reliability of the device [16]. Mukherjee et al. has given the impact of BOX oxide thickness on analogue circuit performance [17].

1.1 Background

Due to scaling in MOS devices, various operating problems related issues have also regarded as major challenging issues in the MOS design. When working beyond 100 nm, the related problems like boron penetration, high gate resistance and poly-si depletion are contrasted to be dominating. These obstructions in device performance have been predominantly overcome by application of metal gates. The metal gates concept was first provided using tantalum gate to replace the polysilicon gate [18]. In continuation to the research, dual metal gate technology [19, 20] has been utilized in the design of FD SOI MOSFET. In which, use of two metal gates in place of single gate, gives a step-up potential at source side and hence no drop in threshold voltage due to inclusion of drain potential, and hence reduced SCEs. J. P. Colling had concluded the importance of multi-gate structures in SOI MOSFETs [19]. Kumar et al. had developed a model of FD SOI MOSFET using dual material gate and discussed the potential benefits of this technology [20]. Additionally, Priya et al. has given a concept of triple-metal-gate with recessed S/D technology in the design of FD SOI MOSFET [21]. This structure has been intensively designed to decrease the series resistance of S/D regions, which in turn improves the drive current capability of the device and hence enhanced circuit performance.

In dual metal gate technology two metal gates of different work functions are used. However, the major challenge is to find two metals with suitable work functions and a way to integrate them into a modern metallization process in MOS fabrication. So, the integration of multiple metal gates side by side has some serious fabrication complexities [22]. These complexities can be overcome by placing an insulator in between two metal gates. Recently, Wei et al. have discussed the incorporation of insulator in between two metal gates and the advantages over short channel effects, like DIBL [23]. However, none has discussed this dual metal insulated gate technique with source engineered FD SOI MOS technology for the design of ring oscillator circuit. It is, therefore, necessary to investigate the performance of DMIG technique in the design of source engineered FD SOI MOSFET for low power applications.

1.2 Contribution

In this work, the dual metal insulated gate technique in the design of source engineered FD SOI MOSFET has been employed for the first time. It has been assured that the device is performing at low power and successfully accommodating the SCEs as compared to other devices at this node [15,16,17]. Additionally, for the first time, a ring oscillator circuit has been designed with nano-scaled DMIG FD SOI MOSFETs for the analysis of delay, power consumption and oscillation frequency. This paper has been divided in following sections. First, the device structure and proposed fabrication feasibility of the device are discussed in Sect. 2. Then, the comparative analysis over DC characteristics and potential benefits of FD SOI MOSFETs has been taken into account in Sect. 3. Further, studied device based ring oscillator circuit has been analyzed on the basis of CMOS inverter as individual stage in Sect. 4. The overall contribution of the work is discussed in conclusion Sect. 5.

2 Device structure and specification

Figure 1 shows the cross sectional view of the proposed FD SOI MOSFET ‘C’ along with two different MOS structures, ‘A’ and ‘B’ [15], and the complete specifications are listed in Table 1. Where, L is the channel length and Tox is front oxide thickness. The carrier concentrations are denoted as Psub, Ns+, Ns− and Nd for substrate, highly doped source, lightly doped source and for drain region, respectively. The BOX and silicon film thickness are denoted as TBOX and Tsi. For the comparison purpose, all the three devices have been modelled with same parameters. The device A is the conventional structure of FD SOI MOSFET and device B has already been recognised at same technology node of 50 nm [15]. In device structures ‘B’ and ‘C’, Ns+ has been taken up to Tsi1= 2 nm and Ns− concentration for Tsi2= 10 nm, such that Tsi= Tsi1+ Tsi2 [15]. The substrate voltage is considered as Vsub = 0 for all three devices studied here. The device C is featured with two metal gates (M1 and M2) of materials molybdenum and titanium with work functions 4.6 eV and 4.4 eV, respectively, and insulated gap is of high-k dielectric HfO2. The gate voltages \(V_{{{\text{g}}_{1} }}\) and \(V_{{{\text{g}}_{2} }}\) are kept equal in device C. Moreover, for the proposed device ‘C’, channel length (L) is equal to the sum of two metal gates and the insulator gap (L = LM1+ LIN+ LM2), where LM1 and LM2 are the length of the two metal gates and are taken as 22 nm each, and LIN is the insulator gap of 6 nm.

Fig. 1
figure 1

Devices under consideration: a device A: conventional FD SOI MOSFET, b device B: referenced FD SOI MOSFET [15], c device C: proposed DMIG Source Engineered FD SOI MOSFET

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Table 1 Device parameters and specifications for the devices under study
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2.1 Fabrication feasibility of the proposed device

The device fabrication is experimentally feasible with the following steps as shown in Fig. 2. Moreover, as per the recent literatures, the fabrication of FD SOI MOSFETs is possible [24,25,26,27,28,29,30]. Very firstly, a SOI wafer will be prepared on a patterned Si sample using UNIBOND process with smart cut technology [24]. These processes involves H+ ion-implantation into a Si donor wafer followed by cleaning, bonding, smart-cut and anneal process as well. Then, the top silicon layer will be doped using boron implant to control the threshold of the device. This process is reported better as compared to SiMOX technology [24]. Then next step is the formation of multiple BOX profile \(N_{\text{s}}^{ + } /N_{\text{s}}^{ - }\) implantation at source side. The \(N_{\text{s}}^{ + } /N_{\text{s}}^{ - }\) implantation of (2 nm/10 nm) at source side could be done with active substrate ion-implantation technique [25] and also Nd implantation at drain side of 12 nm followed by annealing process for dopant activity. Then, the metal contact is formed over and above these S/D implantations. Then, the high-k gate dielectric (HfO2) of 1 nm is grown over through active layer deposition method at defined temperature and pressure as discussed in [26]. After this step, two separated metal gates (M1 and M2) are deposited on either sides of the gate dielectric using normal evaporation method on the top of the gate dielectric considering E-beam lithography along with thermal anneal process and followed by deposition of HfO2 inside the visible cavity through plasma active layer deposition [27,28,29,30]. There may be possibility of process induced damage, such that gate oxide is not completely etched and residual oxide is left or it may get damaged at the gate edge, resulting in dielectric edge damage. This may removed by the multi-step dielectric damage process after etching as suggested in [28]. Additionally, chemical mechanical polishing (CMP) is suggested to perfectly separate the two metal gates as described in [29, 30]. After the gate pattering, nano cavity can be produced similarly as per the fabrication steps in [29, 30]. Additionally, one more step is required to clear the HfO2 gate dielectric over the G/S/D electrodes, i.e., reactive ion etching. Then acetone solution is used to remove the unwanted contact areas in sample and finally the sample will be ready for test [25, 27]. The complete device dimensions and doping levels are listed in Table 1.

Fig. 2
figure 2

Process flow of proposed DMIG source engineered FD SOI MOSFET

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2.2 Simulation setup

The electrical performance of these devices has been extensively examined using numerical ATLAS Silvaco simulator [31]. For the accurate estimation of the studied designs, various mathematical models have been included in the simulator. As for the majority career life time, Shockley–Read–Hall (SRH) generation and recombination model has been used. To accommodate the temperature dependency on mobility, the Lombardi mobility and constant voltage and temperature (CVT) model has been taken into account. FLDMOB model has been included to analyse effects of saturation velocity due to high transversal electric fields because of small dimensions. Additionally, Gummel Newton and drift diffusion model has been chosen for current transport (on–off switching). In addition to this, the quantum confinement model needs to be included in nano-scaled devices. For this, the Bohm quantum potential (BQP) model is used here along with hydrodynamic model. In which, the semi-classical potential is converted into quantum potential in the same manner as the continuity equation. The provided meshing strategies in [31] have been utilized for the deep matrix calculations at each step of simulation.

3 DC characteristics of the proposed FD SOI MOSFET

Figure 3 shows the drain current versus gate voltage characteristics of the studied devices (A, B and C). From, Fig. 3a, it can be seen that the proposed device C is better as compare to other. As, the device C is offering low-off-state leakage current and sufficient drive current at drain bias of 0.1 V. This is due to the proposed DMIG technique which increases the average electric field under the gate M1 and this automatically enhances the carrier life time of the carriers. That results in higher gate transport efficiency. Gate transport efficiency is average travelling velocity of electron through the channel which is directly related to the distribution of electric field in the channel. Hence, the gate controllability over the channel is improved in device C as compare to device A and B at sufficient drain bias. It is also worth here to mention that due to the source modification technique adopted in device B and C, the parasitic capacitance effects have been greatly reduced when a lightly doped N- layer has been introduced underneath the highly doped N+ layer in source region as compared to the conventional FD SOI MOSFET (A). The switching ratio (Ion/Ioff) is calculated maximum for device C as 1012, which is quite enough to justify the immunity of the device C over various short channel effects.

Fig. 3
figure 3

Input (Id vs. Vgs) characteristics a for the devices under study at fixed BOX thickness of 5 nm, b impact of BOX oxide thickness variation on Id versus Vgs characteristics

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It is also necessary to verify the device performance with certain design parameters variation. For a FD SOI MOSFET, proper selection of buried oxide thickness is necessary to conquer the off-state leakage. Figure 3b indicates the Id versus Vgs characteristics of studied devices at different BOX oxide thickness. It can be concluded from the plot, as the BOX thickness is increased from 5 to 20 nm, the drive current is also incremented because of the enhanced lateral field. The drive current is found maximum for device C as 2.7 mA at BOX thickness of 20 nm due to the insulated gate technique.

Moreover, there is a trade-off in selection of BOX thickness as per the required application necessities. In this way, the proposed device is almost free from short dimension effects. This analysis has been listed in Table 2, in which the exact simulated extractions are mentioned clearly.

Table 2 Detailed analysis of drive current (Ion), off-state leakage (Ioff) and switching ratio (Ion/Ioff) for the devices under study at different buried oxide thickness (TBOX)
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The main feature of the dual metal insulated gate technology is that it introduces a potential step in channel region of MOSFET. So, it is, therefore, necessary to verify the threshold voltage roll-off effect for the further conclusions. Figure 4a, b shows the graph of threshold voltage variation with device channel length for the devices taken into consideration for different drain voltages of 0.05 V and 0.1 V, respectively. The maximum slope method of threshold voltage extraction is used during TCAD simulations [31]. One can observe from the plots that there is no roll-off seen in the case of proposed device C and small roll-off in case of device B when Vds is increased from 0.05 to 0.1 V. Whereas, device A shows the higher roll-off as compared to device B and C. This also justifies that the DMIG enabled device is free from drain electric field penetrations and offers lower voltage of operation as well. So, DMIG technology provides more flexibility to optimize the channel region under low work-function metal (M2) because of device threshold depends upon higher work-function metal (M1) and high-k insulator gap maintains the potential excursions’.

Fig. 4
figure 4

Threshold voltage variation with channel length: a at Vds = .05 V, b at Vds = 0.1 V

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Threshold voltage variation with channel length at different buried oxide thickness is listed in Table 3. The threshold voltage is increased by decrease in BOX thickness which assures better immunity to short channel effect at small BOX thickness as compared to other reports [15,16,17]. Increasing BOX thickness reduces threshold voltage. So there is less consumption of gate voltage at thicker BOX layer.

Table 3 Threshold voltage variation at different buried oxide thickness with variation in drain voltage (Vds) at L = 50 nm
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The plot of sub-threshold slope versus channel length has been shown in Fig. 5 for the studied devices at TBOX= 5 nm. The plot shows that the device C is approaching towards the ideal value of sub-threshold slope as compared to device A and B. This dictates that the proposed device C can be scaled down till 30 nm and also as per analysis Table 4, the proposed device have scope of further scaling down till 20 nm. The analysis of sub-threshold slope with variation in BOX thickness has also been extracted by two-dimensional numerical simulations here and listed in Table 4. The channel length of device C is scaled down as follows L = 50 nm (LM1= 22 nm, LIN= 6 nm, LM2= 22 nm), L = 40 nm (LM1= 17 nm, LIN= 6 nm, LM2= 17 nm), L = 30 nm (LM1= 13 nm, LIN= 4 nm, LM2= 13 nm) and L = 20 nm (LM1= 8 nm, LIN= 4 nm, LM2= 8 nm).

Fig. 5
figure 5

Effect of channel length scaling on sub-threshold slope for all devices under study at TBOX = 5 nm

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Table 4 Sub-threshold slope with variation in BOX thickness (TBOX in nm) at different channel length
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It is observed from the extraction results that there is a less variability in device C as the BOX thickness is increased to 20 nm. This is due to the suppression of various parasitic effects because of dual metal insulated gate technique with source engineered FD SOI MOSFET. The source engineering will result in variation of built in potential of the device that will off-flow the minority carriers’ conduction during weak inversion and will cause the device leakage free. Also the DMIG with source engineered results in suppression of trans-capacitances. So, these two techniques will enhance the device performance and the studied device can be used for high density ICs.

Moreover, the reported subthreshold-slope for device B is 57 mV/decade. However, the proposed device offers better drive current and excellent switching (Ion/Ioff ratio) performance as compared to device B, which dominates the short channel performance in a device. So, this must be considered as a trade-off depending upon the requirements. The performance of the proposed device has also been verified in terms of DIBL and compared against recent literatures [15, 23] as shown in Fig. 6. It is find the proposed device exhibits better performance due to the utilization of DMIG and source engineering both as compared to [15] and [23].

Fig. 6
figure 6

Comparison of different MOSFETs with proposed FD SOI MOSFET in terms of DIBL

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3.1 Potential benefits of the proposed FD SOI MOSFET

Further to verify the results obtained above, a brief discussion over the surface potential profile, channel electron concentration, electric field and the contour plot of conduction current density have also been taken into consideration. Figure 7 shows the surface potential variation along the channel for the devices under study. In proposed device C, it has been found that the location of the minima surface potential is moved more along the source side of the channel due to the inclusion of HfO2 gap in between two metal gates as compared to device A and B. This step-like function profile clearly indicates that the weak inversion is taking place at the source side of the channel. This will result in more uniform electric field in the channel area as the electric field peak will be located towards the source end. Hence, the source side of the channel region is screened from the changes in the drain potential, i.e., the drain voltage is not affecting the gate controllability over the conduction. Hence, the proposed device with DMIG and source engineering screen-off the drain bias effects twice as compare to other technologies at this node. The position of minima along with the corresponding potentials is listed in Table 5.

Fig. 7
figure 7

Surface potential profile versus channel length of the studied MOSFETs (cutline at Tsi = 2 nm)

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Table 5 Minima position and value of surface potential along the channel
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It is also necessary to demonstrate the performance of the proposed device further by observing the electron concentration under the channel area. The comparative study of carrier concentration for the devices under consideration is shown in Fig. 8. One can observe from the figure that the channel concentration is more uniform and optimum in case of proposed MOSFET and decreasing beyond source to drain edge. This characteristics itself explains the suppression of drain penetration towards gate control. It is also worth here to mention that the continuous/unceasing concentration has been recorded in the channel area under the high-k gap. This evidence itself supports the working of the proposed device with inclusion of high-k that there are various benefits in considering high-k gap.

Fig. 8
figure 8

Comparison of different MOSFETs with proposed FD SOI MOSFET in terms of channel electron concentration (cutline-Tsi = 2 nm)

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In addition to this, the plot of electric field along the channel length is shown in Fig. 9. Similarly, it also supports the potential profile as the maxima peak of the electric field is observed more nearer towards source in case of device C followed by device B and A, respectively. So, the device has better short channel immunity.

Fig. 9
figure 9

Electric filed (V/cm) behaviour of the devices taken under study (cutline at Tsi = 2 nm)

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At last, the contour plots of conduction current density inside the channel at L = 50 nm is presented in Fig. 10. It is evident that the proposed device exhibits more uniform current density as compared to device A and B inside the channel. The electrical performance comparison of different MOS structure available in the literature has also been done in Table 6. One can find that the proposed MOS structures offers lowest off-state leakage and better switching ratio of 1011 at specified dimensions.

Fig. 10
figure 10

Contour plot of conduction current density (A/cm2) of the studied MOSFETs A, B and C at Vds = 1 V, L = 50 nm (LM1 = 22 nm, LIN = 6 nm, LM2 = 22 nm,), TBOX = 5 nm, Tox = 1 nm and Tsi = 12 nm (Tsi1 = 2 nm, Tsi2 = 10 nm)

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Table 6 Electrical performance comparison of different MOSFETs with proposed FD SOI MOSFET
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As per the above discussion, it has been clarified that the studied device C has excellent immunity over various small dimension effects. It is also worth here to mention that the DMIG based MOS device will reduce the fabrication complexity due to insertion of insulator gap as compared to conventional DMG technology based MOSFETs. Additionally, the line-edge roughness effect [22] will be overcome by DMIG based MOSFETs.

Till now, a comparative study of the devices under consideration has been presented and the evidences clearly explain the significance of the proposed device C when it is compared with devices A and B [15] at the same technology node. It is, therefore, necessary to analyse this device further at circuit level. In next section, ring oscillator circuit has been analysed on the basis of CMOS inverter designed with the proposed DMIG based FD SOI MOSFET.

4 Ring oscillator circuit

In this section, high performance and power efficient ring oscillator circuit has been designed using DMIG based source engineered FD SOI MOSFET. Ring oscillator consists of odd number of delay stages in feedback form as shown in Fig. 11. So, it is necessary to evaluate the performance of individual delay stages. Here, all three delay stages are assumed to be identical and output load capacitances are taken as equal to each other with value (CL1= CL2= CL3= CL). Moreover, the delay calculation in a CMOS inverter essentially depends upon the output load capacitance. The accurate value of the output load capacitance can be calculated by combining the overall parasitic capacitances between the output node and the ground [35].

Fig. 11
figure 11

Three stage ring oscillator circuit designed using proposed DMIG FD SOI MOSFET

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In nanoscaled transistors, basically the parasitic capacitances are Cgs, Cgd, Csb and Cdb. Moreover, the source to bulk capacitance (Csb) has almost negligible effect on transient characteristics of CMOS inverter, since the source-substrate potential is kept zero in case of PMOS and NMOS both. Moreover, the gate to drain parasitic capacitance (Cgd) the gate to source capacitance (Cgs), and the drain to bulk parasitic capacitance (Cdb) will be present in calculation.

The plots of Cgd(n/p), Cgs(n/p) and Cdb(n/p) are shown in Figs. 12, 13, and 14. It is clear from the plot that the resulting optimum values of Cgd,p, Cgd,n, Cgs,p, Cgs,n, Cdb,p and Cdb,n are 1.70 fF, 0.918 fF, 0.21 fF, 0.342 fF, 0.056 fF, and 0.031 fF, respectively, for L = 50 nm. So, the maximum value of output load capacitance (CL = Cgd,p + Cgd,n + Cgs,p + Cgs,n + Cdb,p + Cdb,n) could be approximated as 3.257 fF for L = 50 nm and further it slightly decreases with scaling in channel lengths. Similarly, the calculated value of CL is found as 2.80 fF and 2.63 fF for L = 40 nm, 30 nm, respectively. Since, lesser change in parasitic capacitances is observed at L = 40 nm, 30 nm and as it is always advisable to investigate the device performance at circuit level by considering optimum case of parasitic effects. So, we have considered the maximum value of parasitic load capacitance CL = 3.25 fF to analyze the parasitic behaviour of the proposed device at lower dimensions. Now, the transient and DC analysis of the proposed individual inverter stage has been performed using the numerical simulator ATLAS Silvaco [31].

Fig. 12
figure 12

Plot of Cgd,p and Cgd,n with variation in Vgs for proposed MOSFET for L = 50 nm, Vds,p = − 1 V, Vds,n = 1 V

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Fig. 13
figure 13

Characteristics of Cgs,p and Cgs,n versus Vgs for proposed MOSFET for L = 50 nm, Vds,p = − 1 V, Vds,n = 1 V

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Fig. 14
figure 14

Characteristics of Cdb,p and Cdb,n versus Vgs for proposed MOSFET for L = 50 nm, Vds,p = − 1 V, Vds,n = 1 V

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4.1 DC analysis of individual inverter stages

The voltage transfer characteristics of the DMIG source engineered FD SOI MOSFET based inverter circuit is shown in Fig. 15a, b. The operation of the proposed inverter can be discussed as follows. From, Fig. 15a, it is clear that the PMOS device is in the ON state when the input voltage (Vin) is below the threshold voltage of NMOS transistor (\(V_{{{\text{tn}}_{\text{DMIG}} }}\)) and the output voltage will result in VDD. Now, as the input voltage is slightly above \(V_{{{\text{tn}}_{\text{DMIG}} }}\), the conduction of NMOS transistor starts in saturation region, and the output voltage will begin to decrease. As the output voltage decreases further, PMOS transistor will conduct in saturation mode. Now as the output voltage becomes less than Vin − \(V_{{{\text{tn}}_{\text{DMIG}} }}\), NMOS transistor will work in linear region. Finally, as the voltage exceeds the \(V_{\text{dd}} + V_{{{\text{tp}}_{\text{DMIG}} }}\), the pMOS turns off. The TCAD extracted values of \(V_{{{\text{tn}}_{\text{DMIG}} }}\) and \(V_{{{\text{tn}}_{\text{DMIG}} }}\) are 0.40 V and − 0.430 V, respectively. It is also clear from the plot that the characteristics of the inverter is almost centred around \(V_{\text{dd}}\)/2, which is significant in the implementation of the proposed inverter with high density ICs such that high thermal stability.

Fig. 15
figure 15

VTC of individual Inverter designed with DMIG FD SOI MOSFET: a at supply voltage = 1 V, b at supply voltage = 0.5 V

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Figure 15b shows the effect of supply voltage scaling on voltage transfer characteristics of the device. Since, the modern era is running around the optimization of low power enabled integrated circuits. Here, the values of \(V_{{{\text{tn}}_{\text{DMIG}} }}\) and \(V_{{{\text{tp}}_{\text{DMIG}} }}\) are 0.214 V and − 0.226 V, respectively. From, Fig. 15b, it is clear that the voltage transfer characteristics of the proposed MOSFET attains the similar nature even if the supply voltage is scaled to \(V_{\text{dd}}\)/2 and also the switching threshold (\(V_{{{\text{m}}_{\text{DMIG}} }}\)) is found good. This assures the acceptable performance of the proposed CMOS circuit even at lower supply voltages. Moreover, switching threshold is the point where both the transistors (NMOS and PMOS) of CMOS inverter work in saturation region. Also at that point, it is assumed that the current in both the transistors is same.

The exact value of switching threshold has been calculated from Eq. (1). Where,\(k_{{{\text{p}}_{\text{DMIG}} }}\) and \(k_{{{\text{n}}_{\text{DMIG}} }}\) are the saturation point transconductance with device width of Wp = 3 µm, Wn = 1 µm for PMOS and NMOS, respectively, and calculated in similar manner as suggested in [35]. After solving, it is clear that the theoretical value of switching threshold is in a good agreement with the simulator. For the supply voltage of 1 V, \(V_{{{\text{m}}_{\text{DMIG}} }}\)(model) = 0.445 V, \(V_{{{\text{m}}_{\text{DMIG}} }}\)(simulated) = 0.460 V, and for Vdd = 0.5 V, \(V_{{{\text{m}}_{\text{DMIG}} }}\)(model) = 0.216 V, \(V_{{{\text{m}}_{\text{DMIG}} }}\)(simulated) = 0.240 V.

$$V_{{{\text{m}}_{\text{DMIG}} }} = \frac{{V_{{{\text{tn}}_{\text{DMIG}} }} + \left( {\sqrt[2]{{\frac{{k_{{{\text{p}}_{\text{DMIG}} }} }}{{k_{{{\text{n}}_{\text{DMIG}} }} }}}} \times \left( {V_{\text{dd}} + V_{{{\text{tp}}_{\text{DMIG}} }} } \right)} \right)}}{{\left( {1 + \sqrt[2]{{\frac{{k_{{{\text{p}}_{\text{DMIG}} }} }}{{k_{{{\text{n}}_{\text{DMIG}} }} }}}}} \right)}}$$
(1)

The impact of BOX variation on the VTC of DMIG FD SOI MOSFET has been shown in Fig. 16. It is found that the variation in BOX thickness have significant impact on circuit performance. As the BOX thickness has been increased from 5 to 10 nm, the circuit resembles almost same VTC. However, as the BOX thickness is made 20 nm, the VTC take a shift towards right. This will affect the noise margin level of the circuit.

Fig. 16
figure 16

VTC of individual Inverter designed with DMIG FD SOI MOSFET at different BOX oxide thickness

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4.2 Noise margins (NMs)

The amount of noise that a circuit can tolerate is regarded as the noise margin (NM). Beyond this, the logic circuit could not work properly, even reliability issue takes place. So, it is necessary to make the NMs as high as possible. However, very high NMs results in large voltage excursions that leads to larger delay and more power dissipation. It is, therefore, necessary to maintain a trade-off among NMs, delay and power. The calculation of different NMs has been done on the basis of Eqs. (2 and 3). Where \({\text{NM}}_{{{\text{l}}_{\text{DMIG}} }}\) and \({\text{NM}}_{{{\text{H}}_{\text{DMIG}} }}\) are low and high NMs, respectively. Further, \(V_{{{\text{IL}}_{\text{DMIG}} }}\) and \(V_{{{\text{OL}}_{\text{DMIG}} }}\) in Eq. (2) are low level input and output voltages, respectively, and \(V_{{{\text{IH}}_{\text{DMIG}} }}\) is high level input and \(V_{{{\text{OH}}_{\text{DMIG}} }}\) is high level output voltages in Eq. (3).

$${\text{NM}}_{{{\text{l}}_{\text{DMIG}} }} = {\text{V}}_{{{\text{IL}}_{\text{DMIG}} }} - V_{{{\text{OL}}_{\text{DMIG}} }}$$
(2)
$${\text{NM}}_{{{\text{H}}_{\text{DMIG}} }} = V_{{{\text{OH}}_{\text{DMIG}} }} - V_{{{\text{IH}}_{\text{DMIG}} }}$$
(3)

It is worth here to mention that the value of \(V_{{{\text{OL}}_{\text{DMIG}} }}\) can be itself assumed as so low that tends to 0 and \(V_{{{\text{OH}}_{\text{DMIG}} }}\) is equal to \(V_{\text{dd}}\).

The respective values of NMs have been note down from the VTC curve shown in Fig. 15a. The mathematical expression for the calculation of \(V_{{{\text{IL}}_{\text{DMIG}} }}\), \(V_{{{\text{IH}}_{\text{DMIG}} }}\) in Eqs. (4 and 5) are taken from [35]. After calculations, the values are \(V_{{{\text{IL}}_{\text{DMIG}} }}\) = 0.402 V (simulation: 0.430 V), \(V_{{{\text{IH}}_{\text{DMIG}} }}\) = 0.442 V (simulation: 0.510 V), \(V_{{{\text{OL}}_{\text{DMIG}} }}\) = 0 and \(V_{{{\text{OH}}_{\text{DMIG}} }}\) = \(V_{\text{DD}}\) = 1 V. So, from Eqs. (2 and 3), \({\text{NM}}_{{{\text{l}}_{\text{DMIG}} }}\) and \({\text{NM}}_{{{\text{H}}_{\text{DMIG}} }}\) are 0.402 V (simulation: 0.430 V) and 0.558 V (simulation: 0.490 V), respectively.

$$V_{{{\text{IL}}_{\text{DMIG}} }} = \frac{{2V_{\text{out}} + \frac{{k_{{{\text{n}}_{\text{DMIG}} }} }}{{k_{{{\text{p}}_{\text{DMIG}} }} }} \times V_{{{\text{tn}}_{\text{DMIG}} }} + V_{{{\text{tp}}_{\text{DMIG}} }} - V_{\text{DD}} }}{{\left( {1 + \frac{{k_{{{\text{n}}_{\text{DMIG}} }} }}{{k_{{{\text{p}}_{\text{DMIG}} }} }}} \right)}}$$
(4)
$$V_{{{\text{IH}}_{\text{DMIG}} }} = \frac{{V_{\text{DD}} + V_{{{\text{tp}}_{\text{DMIG}} }} + \frac{{k_{{{\text{n}}_{\text{DMIG}} }} }}{{k_{{{\text{p}}_{\text{DMIG}} }} }} \times \left( {2V_{\text{out}} + V_{{{\text{tn}}_{\text{DMIG}} }} } \right)}}{{\left( {1 + \frac{{k_{{{\text{n}}_{\text{DMIG}} }} }}{{k_{{{\text{p}}_{\text{DMIG}} }} }}} \right)}}$$
(5)
$$\tau_{{{\text{phl}}_{\text{DMIG}} }} = \frac{{C_{L} }}{{K_{\text{n}} \left( {V_{\text{DD}} - V_{{{\text{tn}}_{\text{DMIG}} }} } \right)}}\left[ {\frac{{2V_{{{\text{tn}}_{\text{DMIG}} }} }}{{\left( {V_{\text{DD}} - V_{{{\text{tn}}_{\text{DMIG}} }} } \right)}} + \ln \left( {\frac{{4\left( {V_{\text{DD}} - V_{{{\text{tn}}_{\text{DMIG}} }} } \right)}}{{V_{\text{DD}} }} - 1} \right)} \right]$$
(6)
$$\tau_{{{\text{plh}}_{\text{DMIG}} }} = \frac{{C_{L} }}{{K_{\text{p}} \left( {V_{\text{DD}} - \left| {V_{{{\text{tp}}_{\text{DMIG}} }} } \right|} \right)}}\left[ {\frac{{2\left| {V_{{t{\text{p}}_{\text{DMIG}} }} } \right|}}{{\left( {V_{\text{DD}} - \left| {V_{{{\text{tp}}_{\text{DMIG}} }} } \right|} \right)}} + \ln \left( {\frac{{4\left( {V_{\text{DD}} - \left| {V_{{{\text{tp}}_{\text{DMIG}} }} } \right|} \right)}}{{V_{\text{DD}} }} - 1} \right)} \right]$$
(7)
$$\tau_{{{\text{p}}_{\text{DMIG}} }} = \frac{{\tau_{{{\text{phl}}_{\text{DMIG}} }} + \tau_{{{\text{plh}}_{\text{DMIG}} }} }}{2}$$
(8)

4.3 Transient analysis

The transient analysis of the proposed inverter circuit has been discussed here on the basis of propagation delays. Both the dynamic power dissipation and frequency/speed is affected by the propagation delay. So, the timing analysis is of the main concern for IC designers. Propagation delay is defined as the time required in a circuit to produce an output as soon as the input is applied. Basically, propagation delay of CMOS inverter is the average of two types of propagation delays that must be encountered to study the timing constraints of the proposed circuit. These delays depend on the transition from low to high and vice versa. The first one is \(\tau_{{{\text{phl}}_{\text{DMIG}} }}\),which is calculated on the basis of transition from high to low (1–0), and for low to high (0–1) transition, \(\tau_{{{\text{plh}}_{\text{DMIG}} }}\) is considered.

By definition, \(\tau_{{{\text{phl}}_{\text{DMIG}} }}\) is the time delay between the V50%-transition of the rising input voltage and V50%-transition of the falling output voltage [35]. Similarly, \(\tau_{{{\text{plh}}_{\text{DMIG}} }}\) is the time delay between the V50%-transition of the falling input voltage and V50%-transition of the rising output voltage. Moreover, in Fig. 17, we have mentioned \(\tau_{{{\text{phl}}_{\text{DMIG}} }}\) and \(\tau_{{{\text{plh}}_{\text{DMIG}} }}\), as these are responsible for delay in high–low transition and low–high transition, respectively.

Fig. 17
figure 17

Transient analysis of the proposed DMIG FD SOI MOSFET at 50 nm channel length

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The calculation of these delays has been governed here on the basis of simulation result shown in Fig. 17 and verified against the model as per Eqs. (6 and 7) [35]. Moreover, overall delay is being approximated as \(\tau_{{{\text{p}}_{\text{DMIG}} }}\) from Eq. (8), which is average of \(\tau_{{{\text{plh}}_{\text{DMIG}} }}\) and \(\tau_{{{\text{phl}}_{\text{DMIG}} }}\). It is clear from Fig. 17 that the proposed inverter offers almost negligible delay. The individual delay stage calculations at different channel length for fixed BOX thickness (5 nm) is listed in Table 7. One can find from Table 7 that lesser delay is seen at channel length of 50 nm, and also there is further scope of channel length scaling as lower delay recorded at scaled dimensions. Additionally, the mathematical results are found in good agreement with the numerical simulations. The electrical performance parameters and inverter stage delay of proposed MOS structure have also been compared and contrasted with the available state-of-the-arts and presented in Table 8. It is clear from the table that the proposed device offers excellent performance than others [36, 37].

Table 7 Individual inverter stage delay at different channel length for BOX oxide thickness of 5 nm at Vdd = 1 V
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Table 8 Comparison of electrical performance parameters and inverter delay of different MOSFETs
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4.4 Power dissipation

Power dissipation (\(P_{{{\text{D}}_{\text{DMIG}} }}\)) is the main concern of today’s high density ICs. For a CMOS inverter, it is calculated as the sum of static and dynamic power consumption. The associated off-state leakage in the devices is responsible for static power consumption. Moreover, the charging and discharging of capacitor in working condition at load is responsible for dynamic power dissipation. This can be formulated as in Eq. (9). The first part of this equation is due to static power dissipation and second part is due to dynamic.

$$V_{\text{dd}} I_{{{\text{leak}}_{\text{DMIG}} }} + \alpha C_{L} V_{\text{dd}}^{2} f_{{{\text{out}}_{\text{DMIG}} }}$$
(9)

where\(I_{{{\text{leak}}_{\text{DMIG}} }}\) is the off-state leakage of the studied DMIG device, \(\alpha\) is the switching activity factor of CMOS inverter and assumed as 1, and \(f_{{{\text{out}}_{\text{DMIG}} }}\) is output signal frequency. The output load capacitance of individual inverter delay stage is termed as \(C_{L}\) (CL= CL1= CL2= CL3) and is taken as 3.25 fF as per the discussion in Sect. 4.1. It is worth here to mention that as \(I_{{{\text{leak}}_{\text{DMIG}} }}\) is affected with the channel length scaling and buried oxide thickness, and \(f_{{{\text{out}}_{\text{DMIG}} }}\) will depend upon the threshold voltage of operation. So, the power dissipation will become a crucial factor for device designers in current trends of nanometers scaling.

Here for the analysis, power dissipation for the variation in channel length at different buried oxide thickness is shown in Fig. 18. One can observe from Fig. 18 that as the channel length is increased from 30 to 50 nm, the power consumption is getting reduced. This explains the similar scaling performance constraints as discussed in previous Sect. 3. As the increment in channel length will automatically result in lesser off-state leakage and hence reduced power consumption.

Fig. 18
figure 18

Power dissipation of individual inverter stage at different BOX thickness with variation in channel length for Vdd = 1 V

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Moreover, the drive current and frequency of output signal will vary with buried oxide thickness at fixed channel length and will increase power consumption further. However, the designed CMOS inverter is offering lesser power dissipation as compare to [38]. From, Fig. 19, as the supply voltage is increment from 0.5 to 2 V, propagation delay decreases, and also follows the proportional relationship with BOX thickness variation. However, power dissipation increments at higher VDD, and also increases as the BOX thickness varied from 5 to 20 nm.

Fig. 19
figure 19

Propagation delay and power dissipation at different supply voltage of operation at L = 50 nm

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4.5 Oscillation frequency of ring oscillator

In this section, the oscillation frequency \((f_{\text{osc}} )\) of the proposed ring oscillator circuit has been calculated on the basis of Eq. (10). Where, \(\tau_{{{\text{p}}_{\text{DMIG}} }}\) indicates the propagation delay of individual inverter stage and N is the number of inverter stages.

$$f_{\text{osc}} = \frac{1}{{2N\tau_{{{\text{p}}_{\text{DMIG}} }} }}$$
(10)

where N is the total no of stages.

Here, three stages of identical inverters have been taken for the design of ring oscillator circuit. So, same delay is considered as per the Eq. (9) for all three inverter stages. The calculation of \(f_{\text{osc}}\) for the different channel length is listed in Table 9. It has been found that the ring oscillator circuit operates in GHz frequency range and as the channel length is getting reduced, oscillation frequency increases. This happens due to increment in drive current of the studied device at lower channel length. This ultimately dictates the significance of the scaling of MOSFETs in nano-scaled regime. Also the proposed device is in good agreement with analytical results with maximum deviation of 4–10%.

Table 9 Oscillation frequency of 3-stage ring oscillator at different channel length for BOX oxide thickness of 5 nm
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However, in literature, very few have discussed the circuit analysis of the nano-scaled devices. Table 10 represents the comparison of oscillation frequency for studied ring oscillator circuit with available state-of-arts. It is found that the proposed device offers comparable oscillation frequency.

Table 10 Comparison of proposed ring oscillator circuit with available state-of-the-arts normalized for 3-stage design
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5 Conclusion

This paper presents the comprehensive analysis of ring oscillator circuit designed with nano-scaled SOI MOSFETs based CMOS inverter for low power high density ICs. For this, first the impact of DMIG technique on the performance of source engineered FD SOI MOSFET has been taken under study. It has been found that the proposed device is performing at low power and successfully accommodating the SCEs as compared to other devices at this node. The proposed structure exhibits a step-like potential profile with its minima very close to the source side of the channel and results in the lesser DIBL. In addition to this, the channel electron concentration is found uniform below insulator gap and results in better conduction current density. Additionally, the proposed device offers off-state leakage of 0.125 fA, which is quite enough to off-flow the leakage during switch-off condition in a circuit, and the drive current of 2.03 mA at optimized BOX thickness of 5 nm for 50 nm channel length. Hence, the switching ratio in order of 1011 suggests that the device could be analysed for high speed applications. Further, the designed CMOS inverter’s VTC characteristics signifies that the proposed inverter can be utilized for high density ICs with enhanced thermal stability as the high to low transition is almost centred around \(V_{\text{dd}}\)/2. Additionally, the studied inverter follows the supply voltage scaling trends significantly with high noise margin. The power dissipation for the designed inverter circuit is found as 0.280 mW at TBOX = 5 nm and L = 50 nm. In continuation, the designed ring oscillator is offering individual inverter delay of 1.98 ps at TBOX = 5 nm and L = 50 nm, which is almost 86.80% and 38.60% lower as calculated in [36, 37], respectively. Additionally, the oscillation frequency is calculated as 84.18 GHz, 92.50 GHz and 101.62 GHz at L = 50 nm, 40 nm, and 30 nm, respectively. These results itself explain the significance of the studied device in the design of these circuits. So, the studied nano-scaled device could be suggested for the design of high density ICs in low power and high performance applications.