Abstract
Investigation of the proposed Silicon gate all around dielectric window spaced-multi-channel (Si-GAA-DWS-multi-channel) MOSFET is carried out through 3D-ATLAS TCAD simulator. The proposed device parameter has been compared with the existing devices, mainly with Silicon-Nanowire-Dielectric Pocket Packed MOSFET (Si-NW-DPP FET) and Silicon-Nanowire MOSFET (Si-NW FET). The Si-GAA-DWS-Multi-channel FET is found to be the better device than the other two structures with a threshold voltage of 0.40 V, an on current of 0.326 × 10–3 A, off current of 5.9 × 10–13 A, on/off current ratio of 5.52 × 108, sub-threshold swing of 63.4 mV/dec and DIBL of 26.25 mV/V. Impact of interface fixed charges and multi state defects have been studied for the Si-GAA-DWS-multi-channel MOSFET. Presence of fixed negative charges and multi state defects at semiconductor-oxide interface causes a step in the potential profile which results in the shift of threshold voltage, degradation of drain current, and Ion/Ioff ratio.
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Dr. Girija Shankar Sahoo conceived and designed the simulation and written the manuscript; Ushodaya A performed the simulation study and generated the output; Dr. Girija Shankar Sahoo, and Dr. G P Mishra modified the manuscript and analyzed the data; Dr. Guru Prasad Mishra contributed by providing the Silvaco tool; all authors reviewed the entire manuscript.
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Sahoo, G.S., Ushodaya, A. & Mishra, G.P. Effect of Defects on the Switching Performance of Silicon-Gate All Around Dielectric Window Spaced-Multi-channel MOSFET. Silicon 16, 3317–3323 (2024). https://doi.org/10.1007/s12633-024-02924-x
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DOI: https://doi.org/10.1007/s12633-024-02924-x