1 Introduction

After the announcement of Chua’s memristor element in 1971 [7] and the announcement in 2008 of a group of HP Laboratories that a memristor could be realized with \(\hbox {TiO}_{2}\) film [14], the interest on this element has been increasing day by day. The memristor which has led to a great number of applications in various designs of analog electronics like chaotic oscillators, sensors, cellular neural networks, memory devices and other analog circuitries is the element that provides the relation between flux and charge, which is mathematically missing in circuit theory. The relations between electrical variables and elements can be seen from Fig. 1. It is not possible to find a commercial memristor product yet due to the difficulties encountered in the production of the memristor. For this reason, emulator circuit studies that mimic the mathematical model of the memristor proposed by HP are frequently found in the literature. In this study, a memristance simulator circuit which creates the magnitude in Eq. (1) proposed by Chua in 1971 is realized, not the emulator of the \(\hbox {TiO}_{2}\) memristor presented by HP. In this equation, memristance (M) is obtained when flux \((\varphi )\)–charge (q) curve is nonlinear, though the resistance changes with operation point. If external voltage or current is not applied, the resistance will remain constant as the operating point will not change. This is held in memory as the value of the resistance of the memristor and is called the memristance.

$$\begin{aligned} v(t)=\frac{\mathrm{d}\varphi (t)}{\mathrm{d}q(t)}i(t)=M(t)i(t) \end{aligned}$$
(1)
Fig. 1
figure 1

Basic electrical circuit elements

Full size image

There are lots of studies in the literature that the passive element values in the circuit must be changed to obtain the desired nonlinearity degree for a specific frequency [1, 4, 6, 10, 17,18,19,20]. These changes are difficult to implement, and therefore, methods are needed to make it easier to adapt. Also operation frequencies are limited to a narrow range [1, 10, 17, 18]. In [12], controllability of the circuit is provided with the help of three potentiometers. This is also a mechanical control method. Additionally, this circuit contains many number of active and passive components. The other study in the literature that controls the memristance with the transconductance [13] exhibits memristance characteristic hysteresis curve up to 1 kHz. Another electronically controllable study has given the method of controlling with current [11], but only the conceptual structure has been proposed, and no experiment studies have been done with real elements. Also it is stated at the paper [11] that it does not support any long-term memory effect, only realizes the nonlinear memristor dynamics up to 100 Hz. Although [20] appears to be advantageous in terms of the number of active elements and [19] in terms of frequency, it can be seen that one of them contains 50 and the other contains more than 150 transistors. Some studies offer electronic controllability, but their grounded connection restriction brings disadvantage for designers [3, 5]. The other approach about the memristance circuit studies, when almost all studies in the literature are emulator circuits of HPs \(\hbox {TiO}_{2}\) memristor, a small number of circuits are from different memristance equations [6, 17]. The purpose of this study is to design a floating, nonvolatile, electronically controllable memristance simulator circuit that displays the dynamic behavior which is defined by Chua [7] in a wide frequency range.

In the proposed memristance simulator circuit, a wide range of operation frequency from 5 Hz to 180 kHz is obtained when relatively few numbers of active and passive elements are used. Electrical controllability is provided by only changing the bias currents of the dual-output transconductance amplifier (DO-OTA) circuits. Proposed circuit topology and relative equations are explained in Sect. 2. Mathematical analysis and results of simulations are given in Sect. 3. The method and results of the experimental study are given in Sect. 4. Section 6 contains the results of the study and a comparison table.

2 Proposed Simulator Circuit

In this section, a flux-controlled memristance simulator circuit is derived and controllability of the characteristic i–v hysteresis loop is presented. Schematic of the proposed emulator circuit is given in Fig. 2.

Fig. 2
figure 2

Proposed memristance simulator circuits. a Positive memristance simulator. b Negative memristance simulator

Full size image

The circuit consists of two DO-OTA circuits and one analog multiplier. The defining equations of DO-OTA are \(i_p=i_n=0\) , \(i_{z+}=g_m(v_p-v_n)\) and \(i_{z-}=-g_m(v_p-v_n)\). Analog multiplier (AM) is defined with the equation \(v_m=kv_av_b\). k is a real constant measured in \(\hbox {V}^{-1}\).

By using the defining equations of ideal devices and analyzing the circuit schematics given in Fig. 2, the voltages on the capacitor \(v_\mathrm{C}\), on the resistor \(v_\mathrm{R}\), and the output voltage of the multiplier \(v_\mathrm{M}\) can be calculated as Eq. (2a), (2b), and (2c) respectively.

$$\begin{aligned} v_\mathrm{C}(t)= & {} \frac{-g_{m1}\varphi (t)}{C} \end{aligned}$$
(2a)
$$\begin{aligned} v_\mathrm{R}(t)= & {} Rg_{m1}v(t)\end{aligned}$$
(2b)
$$\begin{aligned} v_\mathrm{M}(t)= & {} \pm \,\frac{kRg_{m1}^2\varphi (t)v(t)}{C} \end{aligned}$$
(2c)

Hence, the memristance equation of simulator circuit is obtained as Eq. (3).

$$\begin{aligned} M(t)=\frac{v(t)}{i(t)}=\pm \,\frac{C}{kRg_{m1}^2g_{m2}\varphi (t)} \end{aligned}$$
(3)

If a sinusoidal exciting source \(v_\mathrm{in}=V_m\sin (\omega t)\) is applied to this device, Eq. (3) turns into Eq. (4).

$$\begin{aligned} M(t)=\pm \,\frac{C\omega }{kRg_{m1}^2g_{m2}V_m(1-cos(\omega t))} \end{aligned}$$
(4)

Equations (3) and (4) are used with sign ‘\(+\)’ for positive memristance circuit in Fig. 2a. With a small connection change as in Fig. 2b, the circuit changes its sign and simulation of negative memristance values can be possible. The defining equation of negative memristance simulator circuit has sign ‘−.’

Fig. 3
figure 3

Designed DO-OTA circuit

Full size image

3 Theoretical and Simulation Results

In this work, a DO-OTA circuit is designed by using \(0.18\, \upmu \hbox {m}\) CMOS transistors as seen in Fig. 3 [9]. The dimensions of the MOS transistors used in the DO-OTA implementation are given in Table 1. Supply voltages are chosen as \(\pm \,1.5\, \hbox {V}\). \(I_{\mathrm{b}}\) is the bias current to control the transconductance (\(g_m\)) of the circuit. Designed DO-OTA circuit could have transconductance between the range [50–\(1200\,\upmu \hbox {A/V}\)] by applying a bias current from 5 to \(1000\, \upmu \hbox {A}\). When choosing \(I_{\mathrm{b}}=200\, \upmu \hbox {A}\), the DC characteristic of designed DO-OTA has \(700\, \upmu \hbox {A/V}\) transconductance. Different transconductance curves are given in Fig. 4. Maximum symmetric differential input voltage range for this transconductance level is determined as \(\pm \,\)200 mV. Maximum output current is also determined as \(\pm \,200\,\upmu \hbox {A}\). The simulations are performed using \(0.18\, \upmu \hbox {m}\) level-7 TSMC CMOS technology parameters with PSPICE. AD633JN is used as AM [16].

Table 1 Dimensions of CMOS transistors
Full size table
Fig. 4
figure 4

DC characteristic of DO-OTA for different bias currents

Full size image
Fig. 5
figure 5

Characteristic i–v hysteresis loops for both positive and negative memristance simulators. a Mathematical calculations. b PSPICE analysis

Full size image

In order to be called a circuit as a memristance simulator, the circuit should exhibit a pinched hysteresis loop in the voltage–current plane when driven by a bipolar periodic signal, the hysteresis lobe area should decrease monotonically as the excitation frequency increases and the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity [2]. In this study, both positive and negative memristance simulator circuit equations exhibited the characteristic current–voltage hysteresis loops which pass through the origin of the coordinate system and pinch when the frequency increases. If there is an offset shift problem due to non-ideality of analog multiplier element, it can be ensured that the hysteresis curve passes through the origin by applying an appropriate DC voltage from the ‘Summing Input’ terminal [16]. Figure 5a, b shows the positive and negative memristance simulator hysteresis loops for \(R=15\, \hbox {k}\Omega , C=100\, \hbox {nF}\) and 1 kHz sinusoidal exciting source. To show frequency dependency of the simulator circuit, different sinusoidal exciting sources of 250, 500 Hz, 1 and 5 kHz are applied to the circuit when the other parameters stay constant. Obtained pinched hysteresis loops from mathematical calculations and PSPICE simulations are given in Fig. 6a, b respectively. According to these results, the circuit shows memristance in range [1.9–\(2\, \hbox {k}\Omega ]\) for 5 kHz, [1.75–\(2.2\, \hbox {k}\Omega ]\) for 1 kHz, [1.2–\(2.45\, \hbox {k}\Omega ]\) for 500 Hz and [1.1–\(5\, \hbox {k}\Omega ]\) for 250 Hz.

Fig. 6
figure 6

Characteristic pinched i–v hysteresis loops for positive memristance simulator for 100 nF. a Mathematical calculations. b PSPICE analysis

Full size image

If capacitor value is decreased, frequency range in which memristor simulator shows nonlinearity speciality is increased. Figure 7 shows pinched hysteresis loops for circuit using 4.7 nF capacitor when other parameters stay constant. According to these results, the circuit shows memristance in range [1.6–\(2\, \hbox {k}\Omega ]\) for 25 kHz, [1.3–\(2.25\, \hbox {k}\Omega ]\) for 10 kHz, [1.2–\(5\, \hbox {k}\Omega ]\) for 5 kHz and [1–\(11\, \hbox {k}\Omega ]\) for 3.5 kHz. It can be seen that memristance characteristics can be exhibited over 25 kHz frequency. Congruently increasing capacitor values show memristance characteristic at lower frequencies. Frequency ranges according to capacitor values are given in Table 2.

Fig. 7
figure 7

Characteristic pinched i–v hysteresis loops for positive memristance simulator for 4.7 nF. a Mathematical calculations. b PSPICE analysis

Full size image
Table 2 Frequency ranges according to capacitor values
Full size table

In order to obtain memristance values at different nonlinearity levels for a specific frequency, bias control current of DO-OTA elements can be adjusted. Lower bias currents create lower output currents and lower nonlinearities for memristance devices. Thus, it is possible to form a memristance simulation in a specific frequency, with a specific nonlinearity degree without changing the circuit elements. As an example, for 5 kHz input signal, Fig. 8 shows the PSPICE results of different memristance characteristics with different current sources in a simulator circuit with 4.7 nF capacitor.

Fig. 8
figure 8

Characteristic pinched i–v hysteresis loops for 4.7 nF capacitor and variable bias currents

Full size image

In order to demonstrate the workability of the proposed simulator circuit, it is necessary to provide the nonvolatility test as well as provide the frequency-dependent pinched hysteresis loop. When 15 mV positive pulses with 5 ms period and 1 ms duration are applied continuously, the variations of the memristance are as in Fig. 9a. The circuit parameters during the pulse train are \(R=30\, \hbox {k}\Omega \), \(C=330\) nF, and in addition, 10 kHz, 50 mV sinusoidal exciting source, which the simulator circuit exhibits linear resistor behavior at that frequency, is connected serially to examine the impedance value of the circuit. The proposed memristor has nonvolatile characteristic because of the fact that memristance has no change during the pulse interval time. The shifting at the current–voltage graphs of the memristance simulator circuit, which has displayed the memristance change after each pulse, can be seen in Fig. 9b.

Fig. 9
figure 9

Variations of the memristance when positive pulses are applied continuously. a Variations of the memristor resistance for each pulse along the time and applied input signal. b Changing current–voltage graphs after first four pulses

Full size image
Fig. 10
figure 10

Implementation of DO-OTA with LM13700 integrated circuits

Full size image

4 Experimental Results

In this section, it is intended to conduct experiments with any DO-OTA circuit, to validate the correctness of the proposed circuit topology. Because there is not a commercially available DO-OTA circuit, DO-OTA is implemented using LM13700 integrated circuit in order to obtain experimental results as Fig. 10 [15]. Since there are two OTAs in each integrated LM13700, one integrated circuit is used for one DO-OTA element. Firstly, for testing the frequency-depended pinched hysteresis loops, transconductances of OTA elements are set to \(1700\, \upmu \hbox {A/V}\). R and C are chosen as \(15\, \hbox {k}\Omega \) and 2.2 nF, respectively. By applying exciting sinusoidal sources with the frequencies of 500 Hz, 1, 1.5 and 2 kHz, characteristic frequency-depended hysteresis loops can be seen from Fig. 11. Oscilloscope outputs for this measurement are given in Fig. 12.

Fig. 11
figure 11

Pinched hysteresis loops according to \(1700\, \upmu \hbox {A/V}\) transconductance

Full size image
Fig. 12
figure 12

Oscilloscope output samples for transconductance of \(1700\, \upmu \hbox {A/V}\). a 500 Hz. b 1 kHz. c 1.5 kHz. d 2 kHz

Full size image

Secondly, the electronic controllability can be tested with the same circuit by applying 1 kHz sinusoidal input signal to the circuit with transconductances being 800, 1100, 1300 and \(1700\, \upmu \hbox {A/V}\). Different nonlinearity degrees are obtained as can be seen in Fig. 13, by using ideal DO-OTA circuit which was formed with ideal dependent sources in PSPICE and by using LM13700 onboard circuit.

Fig. 13
figure 13

Controllability of memristance value by changing transconductance for 1 kHz input. a Onboard circuit with LM13700. b PSPICE with ideal DO-OTA circuit

Full size image

5 An Application Example: Serial MC Circuit

In order to show applicability of the proposed memristance simulator circuit, serial MC and RC connections are simulated as in Fig. 14a. If decremental memristor is used in MC circuit, discharge time must be lower; for incremental memristor, discharge time must be higher than serial RC circuit. Used passive element values are \(C=1\) nF, \(R=1.2\, \hbox {k}\Omega \) and \(M_\mathrm{initial}=1.2\, \hbox {k}\Omega \).

According to resistance variations, decay time varies and if memristance becomes lower than initial memristance value, time constant becomes lower. In case of usage of incremental memristor, memristance value is higher than initial memristance value and time constant will be higher as shown in Fig. 14b. As a result, the applicability is verified because simulation results are very similar to Joglekar’s theoretical MC circuit [8].

Fig. 14
figure 14

Serial RC and MC circuit application examples. a RC and MC circuits. b Discharge curves of RC and MC circuits

Full size image

6 Conclusion

In this work, an analog circuit which shows memristance characteristics is proposed by using two DO-OTAs, one analog multiplier, one grounded resistor and one grounded capacitor. Proposed topology has wide enough frequency ranging from 5 Hz up to 180 kHz to satisfy frequency-dependent pinched hysteresis i–v loop. It is possible to obtain different nonlinearity degrees with a specific input frequency by adjusting \(g_{m}\) values of DO-OTAs with \(I_\mathrm{b}\) current. That is, the memristance value of the proposed memristance simulator circuit can be electronically controlled by using bias current. The nonvolatility is displayed by applying a pulse train to the circuit. Theoretical calculations and PSPICE simulations are in good agreement. Also, the proposed circuit is floating and suitable for use as grounded. No matching condition is required for any circuit element or circuit parameter. Decreasing- and increasing-type-memristance simulation can be realized with a simple connection shifting.

Table 3 Comparison between existing studies
Full size table

Table 3 shows a comparison between existing studies. Electronic controllability feature is the most distinctive advantage of memristor emulator and simulator circuits. The proposed structure has a certain advantage in frequency between the simulator circuits. Also it has an advantage in terms of number of elements between emulator circuits. Given the floating structure, the preference of the topology is increasing. With the production of MOS DO-OTA circuit, it is clear that using this simulator circuit in memristive applications will be appropriate. The workability of the proposed floating memristance simulator circuit has been demonstrated by theoretical calculations, PSPICE simulations and experimental results.