1 Introduction

Multilevel converters are widely used in a variety of industrial applications, including those related to renewable energy, motor drives, and power transmission [1,2,3]. These converters are preferred due to their high power density, good power quality, low dv/dt, and the low voltage stress they exert on the switching devices [4]. The neutral-point clamped (NPC) inverter is one type of multilevel converter. In contrast to other types of multilevel inverters, such as the flying capacitor and cascaded H-bridge, the NPC inverter does not require flying capacitors or isolated dc-link sources [2]. However, as the number of levels in the output voltage increases, the number of diodes required also increases, which leads to uneven distribution of switching losses and a reduction in the overall efficiency of the inverter.

To address these issues with the NPC inverter, some hybrid variations of the NPC inverter have been proposed and implemented in industries. One such variation is the five-level active NPC (ANPC) inverter, which was first introduced in 2005 [5], then commercialized by ABB in 2010 in their 800 kW 6 kV transformer-less ACS 2000 drive [6]. This type of inverter is popular due to the fact that it requires fewer active switching devices and capacitors. It is an extension of the three-level hybrid ANPC (HANPC) inverter [7,8,9,10] and incorporates an additional two active switches and one flying capacitor per phase (Cfx).

As shown in Fig. 1, this design utilizes three different cells: Cell-I, Cell-II, and Cell-III. Si IGBT switching devices are employed in Cell-I whereas SiC MOSFET switching devices are used in Cell-II and Cell-III; this is intended to achieve better performance in the high switching frequency (fsw) range. Using all SiC MOSFETs in the five-level inverter design would significantly increase the cost while only slightly improving system performance. On the other hand, if all Si IGBTs were to be used, then the cost would decrease but the performance would deteriorate at high fsw range. Therefore, the criteria for this arrangement are a balance between effective performance, reliability, and cost [11].

Fig. 1
figure 1

Circuit topology of a three-phase five-level HANPC inverter feeding a three-phase load

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Prior studies have presented several modulation techniques that can be used to control the five-level HANPC inverter, including selective harmonics elimination pulse width modulation (SHE-PWM) [12], phase disposition carrier PWM (PDC-PWM) [13], and phase shifted carrier PWM (PSC-PWM) [14]. While the SHE-PWM technique is capable of balancing the voltage across the Cfx, it is complex and requires a predefined lookup table to store as many voltage control angels as possible to reduce output voltages and currents total harmonic distortion (THD) [15]. This process could result in a slow response control of the inverter and increase its complexity. On the other hand, although PDC-PWM offers fast response control with low computational requirements compared to SHE-PWM, it leads to a more distorted output voltage due to non-uniformly distributed switching and conducting losses [16].

The PSC-PWM modulation technique is effective in balancing the flying capacitor voltages in comparison to the PDC-PWM technique, but it requires two inverted PWM carriers, vtri-1 and vtri-2, to create the five-level output pole voltage vxn, as shown in Figs. 2 and 3. Table 1 presents the eight possible voltage states of the five-level HANPC inverter, which can be controlled by the switching mechanism of the PSC-PWM modulation technique. As a result, natural voltage balancing is achieved in dc-link capacitors C1 and C2 at Vdc/2, and Cfx at Vdc/4, where x represents A-, B-, or C-phase. Nevertheless, implementing PSC-PWM modulation technique on a digital signal processor (DSP) is a challenging task due to the need to compensate for the time-delay (Td,PWM) caused by the PWM modulator [17].

Fig. 2
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Block diagram of conventional PSC-PWM for five-level HANPC inverter

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Fig. 3
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Demonstration of conventional PSC-PWM for generating a five-level vxn

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Table 1 Eight switching states of five-level HANPC inverter using PSC-PWM switching scheme
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Recently, a few studies have addressed the issue mentioned above regarding Td,PWM [18,19,20,21,22,23,24,25,26,27]. For example, in [20], the authors proposed a synchronized PSC-PWM for a cascaded H-bridge multilevel inverter. Although this approach results in reduced fsw and switching losses, it suffers from undesirable uncontrolled and noneliminated harmonics. Another approach involves using compensatory techniques such as lead-lag compensators and predictive control [17, 26, 27]. However, these methods are limited in their ability to effectively compensate for computation delay. For example, the lead-lag compensator has been found to only achieve limited compensation effects, and to amplify high-frequency noise. Meanwhile, predictive control relies on past information and the plant model to estimate future information, and it is therefore susceptible to model errors caused by changes in circuit parameters, which can lead to prediction bias and negatively impact control performance and system stability.

Moreover, PWM methods have gained attention as a mean of compensating for computation delay [20, 23, 24]. By moving the sampling instant closer to the PWM loading instant, the computation delay can be reduced substantially. Nevertheless, this approach can still introduce aliasing and switching noise problems. Asymmetric PWM is another method that has been shown to effectively compensate for computation delay, but it may limit the variable range of duty ratios and introduce extra harmonics. Moreover, real-time compensation with dual sampling mode and real-time loading has been proposed as a means of completely eliminating computation delay [18, 22]; however, this method is currently only applicable to single-phase converters due to its reliance on unipolar and frequency-doubling modulation.

Multisampling PWM techniques have been used in recent years to address computation delay in various applications [19]. However, despite their popularity in DSP platforms, multisampling technology has several key issues, such as switching noise, nonlinearities, and vertical crossing DSPs, which may affect the overall performance of the system. In addition, methods such as digital-filter-based delay compensation, including high-pass filter, Smith predictor, and linear predictor, have been proposed, but the compensation effect is limited in the high-frequency range, and high-frequency noise may even be amplified [21].

Therefore, the present paper proposes a low complexity and high efficiency dual-reference voltage-based pulse width modulation (DRV-PWM) scheme as an alternative control scheme for three-phase five-level HANPC inverters. The DRV-PWM does not require sophisticated phase adjustments to achieve a desirable control of this topology without Td,PWM. Instead, it simplifies the control structure without requiring two PWM carriers. Hence, its implementation on a DSP is less complex, and it does not require the PWM phase tuning between Cell-II and Cell-III. As a result, it is achievable to have balanced losses distributions among the three phases of the five-level HANPC inverter due to the elimination of Td,PWM. Further, switching devices could have higher reliability, and overall efficiency would increase. This is demonstrated by sets of experimental trials comparing the operation of the inverter under the conventional PSC-PWM and proposed DRV-PWM.

The rest of this paper is organized as follows. Section II presents the switching scheme and the limitations of the conventional PSC-PWM technique. Section III introduces the proposed DRV-PWM method. Section IV provides information on the intensive experimental verifications that were conducted. Finally, Section V presents the conclusions of this study.

2 Conventional PSC-PWM and its Limitations

2.1 Switching Scheme

Unlike other modulation schemes that are used to control the five-level HANPC inverter, the PSC-PWM can be considered one of the best candidates due to its robust and natural ability to balance the voltage across C1 and C2 at Vdc/2 and Cfx at Vdc/4. The switching losses are also evenly distributed among the switching devices. Figure 3 shows a demonstration diagram of the conventional PSC-PWM. For clarity of the switching mechanism of the conventional PSC-PWM, fsw has been set at 1.3 kHz. As can be seen from Fig. 2, the process of generating the switching states for the Si-IGBT Sx1–Sx4 and SiC-MOSFET Sx5–Sx8 are processed according to the fundamental frequency or line frequency (fo) of 50 Hz for each phase.

To begin, the three phases’ reference voltages v*xs can be expressed as shown in (1),

$$\left\{ \begin{gathered} v_{As}^{*} = v_{m} \cdot \sin \left( {2\pi f_{o} t} \right), \hfill \\ v_{Bs}^{*} = v_{m} \cdot \sin \left( {2\pi f_{o} t - \frac{2\pi }{3}} \right), \hfill \\ v_{Cs}^{*} = v_{m} \cdot \sin \left( {2\pi f_{o} t + \frac{2\pi }{3}} \right), \hfill \\ \end{gathered} \right.$$
(1)

where vm represents the voltage magnitude, which corresponds to MI.

Secondly, the pole voltage (v*xn) needs to be generated by injecting a zero-sequence signal (v*sn) to extend the MI to (2/√3 ≈ 1.15), which improves the THD characteristics of the load current and reduces the switching losses [28]. v*sn can be calculated by considering the absolute values of the maximum and minimum reference voltages v*A, v*B, and v*C, respectively, as in (2),

$$v_{sn}^{*} = - \left( {\frac{{\max \left\{ {v_{As}^{*} ,v_{Bs}^{*} ,v_{Cs}^{*} } \right\} + \min \left\{ {v_{As}^{*} ,v_{Bs}^{*} ,v_{Cs}^{*} } \right\}}}{2}} \right).$$
(2)

Due to the nature of the three-phase system, v*sn is switching fo three times. Therefore, v*xn can be expressed as in (3),

$$v_{Xn}^{*} = v_{Xs}^{*} + v_{sn}^{*}$$
(3)

To effectively simplify the algorithm of conventional PSC-PWM, v*xn needs to be normalized while considering Vdc as expressed in (4),

$$T_{x}^{*} = \left[ {1 + \left( {\frac{{2 \times v_{xn}^{*} }}{{V_{dc} }}} \right)} \right] \times {\text{TBPRD}},$$
(4)

where TBPRD is the time-based period peak value of PWM counter in the DSP. The next step is to convert T*x into T*xx as depicted in the block diagram in Fig. 2. This process could reduce the number of the required PWM carriers to half of the original number. T*xx can be calculated as shown in (5),

$$T_{xx}^{*} = \left\{ \begin{gathered} T_{x}^{*} - {\text{TBPRD,}}\quad T_{x}^{*} \ge {\text{TBPRD,}} \hfill \\ T_{x}^{*} ,\quad \quad \quad \quad \quad \,\;\;T_{x}^{*} < {\text{TBPRD,}} \hfill \\ \end{gathered} \right.$$
(5)

To satisfy the requirements for generating five-level output vxn, two PWM triangular carriers, vtri-1 and vtri-2, need to be included in the structure of the switching scheme with a 180° phase-shift, as shown in Fig. 3. The switching principle for Sx1–Sx4 in Cell-I depends on T*x. This means they are switching at fo. Hence, the switching rules are given by (6),

$$S_{x1} ,S_{x3} ,\overline{S}_{x2} ,\;{\text{and}}\;\overline{S}_{x4} = \left\{ \begin{gathered} {\text{ON}},\quad \;\,T_{x}^{*} \ge {\text{TBPRD}}, \hfill \\ {\text{OFF}},\quad T_{x}^{*} {\text{ < TBPRD}}. \hfill \\ \end{gathered} \right.$$
(6)

By contrast, Cell-II and Cell-III turn ON and OFF in a complementary manner, when comparing T*xx with vtri-1 and vtri-2, respectively, as expressed in (7),

$$\begin{gathered} S_{x5} \;{\text{and}}\;\overline{S}_{x6} = \left\{ \begin{gathered} {\text{ON}},\quad \;\,T_{xx}^{*} \ge V_{tri - 1} , \hfill \\ {\text{OFF}},\quad T_{xx}^{*} < V_{tri - 1} , \hfill \\ \end{gathered} \right. \hfill \\ S_{x7} \;{\text{and}}\;\overline{S}_{x8} = \left\{ \begin{gathered} {\text{ON}},\quad \;\,T_{xx}^{*} \ge V_{tri - 2} , \hfill \\ {\text{OFF}},\quad T_{xx}^{*} < V_{tri - 2} . \hfill \\ \end{gathered} \right. \hfill \\ \end{gathered}$$
(7)

However, this scheme results in a generation of vxn with balanced voltage across Cfx as well as C1 and C2, and the implementation process for a three-phase five-level HANPC inverter is going to be complicated due to the need to generate the switching signals from a single DSP without Td,PWM.

2.2 Limitations of Implementing PSC-PWM on DSPs

It should be noted that the three-phase five-level HANPC inverter requires twenty-four switching signals. Therefore, it is excessively complicated to generate those switching signals from a single DSP due to the limitation of PWM channels and/or other factors such as synchronization process. As a result, a twenty-four PWM-channel single DSP TMS320F28377S from Texas Instruments [29] is selected to perform the execution of the control algorithm. Although this DSP provides switching for all switching devices of the three-phase five-level HANPC inverter, the synchronization process between Cell-II and Cell-III is complex, as shown in Fig. 4. There is also a delay due to the implementation process, as shown in Fig. 5.

Fig. 4
figure 4

Structural scheme of conventional PSC-PWM based on time-base counter synchronization for three-phase five-level HANPC inverter

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Fig. 5
figure 5

Implementation scheme of conventional PSC-PWM based on time-base counter synchronization for Cell-II and Cell-III of five-level HANPC inverter. A half-dash-gray carrier, which is 180° phase shifted with respect to vtri-1, highlights how Td,PWM affects the switching scheme

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To implement the synchronization process to maintain the same switching principle of generating interleaved PWM carriers, as shown in Fig. 5, there is a need to eliminate the Td,PWM, which is a challenging task. It is necessary to have interrupt signals for vtri-1 and vtri-2 to ensure the same switching scheme as the conventional PSC-PWM method. To satisfy this condition, dual-synchronization is implemented as shown in Fig. 4. The first synchronization is related to vtri-1, while the second one is for vtri-2. Updating those interrupt signals twice at the same time creates a time delay, which results in undesirable switching that does not satisfy the control of the five-level HANPC inverter.

3 Proposed DRV-PWM

3.1 Proposed Switching Scheme

Due to the limitations of the conventional PSC-PWM presented in the previous section, there is a need for an effective yet less complex alternative control algorithm for the five-level HANPC inverter. The proposed switching scheme is based on generating dual-reference voltage signals T*xx-1 and T*xx-2 to avoid the complexity involved in implementing the conventional PSC-PWM in a single DSP. T*xx-1 and T*xx-2 are both extracted simultaneously from (5), as shown in Fig. 6, and expressed mathematically as shown in (8),

$$\begin{gathered} T_{xx - 1}^{*} = \left\{ \begin{gathered} T_{x}^{*} - {\text{TBPRD,}}\quad \quad \;T_{x}^{*} \ge {\text{TBPRD}}, \hfill \\ T_{x}^{*} ,\quad \quad \quad \quad \quad \,\quad \quad T_{x}^{*} < {\text{TBPRD,}} \hfill \\ \end{gathered} \right. \hfill \\ T_{xx - 2}^{*} = \left\{ \begin{gathered} {\text{TBPRD}} - T_{xx - 1}^{*} {,}\quad T_{x}^{*} \ge {\text{TBPRD}}, \hfill \\ {\text{TBPRD}} - T_{x}^{*} ,\quad \quad T_{x}^{*} < {\text{TBPRD}}{.} \hfill \\ \end{gathered} \right. \hfill \\ \end{gathered}$$
(8)
Fig. 6
figure 6

Block diagram of proposed DRV-PWM for five-level HANPC inverter

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The proposed DRV-PWM approach maintains a similar switching principle achieved by (6) for Cell-I due to switching at fo. However, Cell-II and Cell-III are turning ON and OFF at fsw in a complementary manner by comparing T*xx-1 and T*xx-2 with only one triangular carrier, vtri-1, as expressed in (9),

$$\begin{gathered} S_{x5} \;{\text{and}}\;\overline{S}_{x6} = \left\{ \begin{gathered} {\text{ON}},\quad \;T_{xx - 1}^{*} \ge V_{tri - 1} , \hfill \\ {\text{OFF}},\;\;T_{xx - 1}^{*} < V_{tri - 1} , \hfill \\ \end{gathered} \right. \hfill \\ S_{x5} \;{\text{and}}\;\overline{S}_{x6} = \left\{ \begin{gathered} {\text{ON}},\quad \;T_{xx - 2}^{*} \ge V_{tri - 1} , \hfill \\ {\text{OFF}},\;\;T_{xx - 2}^{*} < V_{tri - 1} . \hfill \\ \end{gathered} \right. \hfill \\ \end{gathered}$$
(9)

This process satisfies the requirements for operating the five-level HANPC inverter without the need for two PWM carriers or complex phase shift tuning inside the DSP. The new switching states generated by the proposed DRV-PWM are tabulated in Table 2.

Table 2 Eight switching states of five-level HANPC inverter using proposed DRV-PWM switching scheme
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3.2 Implementation on DSPs

Regardless of the advancements that have been achieved in DSPs used to controlling the three-phase five-level hybrid active NPC inverter, it is necessary to support twenty-four PWM channels. The proposed DRV-PWM does not require any phase-shift tuning between Cell-II and Cell-III of this topology, as shown in Fig. 7. Moreover, the reference voltages are designed alternatively to achieve the desired five-level vxn without any abnormal distortion among the three phases. It is worth noting that the switching signals sent to Cell-III do not require any phase-shifting or time-based synchronization; instead, T*xx-2 is compared with vtri-1 as indicated in (9) and shown in Fig. 8, so a simple hardware implementation is achieved.

Fig. 7
figure 7

Structural scheme of proposed DRV-PWM based on time-base counter synchronization for three-phase five-level HANPC inverter. There is no need to include phase-shift algorithm or sophisticated phase tuning

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Fig. 8
figure 8

Implementation scheme of proposed DRV-PWM based on time-base counter synchronization for Cell-II and Cell-III of five-level HANPC inverter with elimination of Td,PWM

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Further, Fig. 8 shows a time-based implementation of the proposed DRV-PWM. Unlike the conventional PSC-PWM, the interrupt signals for loading and sampling the switching signals for Cell-II and Cell-III required to implement the proposed DRV-PWM are less complex. This process simplifies the whole system and eliminates the Td,PWM that might appear during the generation of Sx5–Sx8.

4 Experimental Results and Discussion

4.1 Experimental Hardware Setup

To verify the effectiveness of the proposed DRV-PWM for a three-phase five-level hybrid active NPC inverter, the experimental hardware setup shown in Fig. 9 is used. It consists of a combination of three cells, control, and power parts. Cell-I consists of six Si IGBT module (SK75GBB066T), developed by SEMIKRON, where each module consists of four Si IGBT devices and their gate drives. The other two cells (i.e., Cell-II and Cell-III) contain the SiC MOSFET (C2M0040120D) developed by CREE. It is worth noting that there is one Cfx per phase, which is connected in parallel between Cell-II and Cell-III. The type of Cfx is selected to be a film capacitor type to handle high fsw with lower capacitance ratings than electrolytic capacitors [11].

Fig. 9
figure 9

Experimental setup of hardware

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In the control part, a single TMS320F28377S DSP board is used as a control board, which is supplied by a 5 V DC power supply. There are also two boards connected to the DSP board and used for the PWM signals and the analogue-to-digital converter (ADC). In the power part, C1 and C2 are used to smooth the DC power supplied to the inverter and connected to two voltage sensors that send their signals to the ADC and then on to the DSP control board. The complete list of experimental specifications is presented in Table 3. To achieve high fsw at 30 kHz, TBPRD is denoted as expressed in (10),

$${\text{TBPRD}} = \frac{{EPWMCLK \times T_{PWM} }}{2} = \frac{{100\;{\text{MHZ}}}}{{2 \times 30\;{\text{kHz}}}} = 1667.$$
(10)

where EPWMCLK is the maximum clock used for EPWM in the TMS320F28377S DSP [29].

Table 3 Experimental specifications
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4.2 Hardware Execution Time of Conventional and Proposed Methods

The experimental results of hardware execution time for the conventional PSC-PWM and proposed DRV-PWM techniques are shown in Fig. 10. It can be seen from the figure that the proposed DRV-PWM requires less computational time than the conventional PSC-PWM. This difference is not substantial, because the TMS320F28377S DSP is an advanced microcontroller, which includes some predefined functions such as TBPHS for setting the phase-shift. However, there is still a Td,PWM because of the sophisticated tuning of the phase-shift between the three-phases, particularly in Cell-II and Cell-III, as illustrated in the aforementioned section.

Fig. 10
figure 10

Hardware execution time of PWM control method: a Conventional PSC-PWM; b Proposed DRV-PWM

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The proposed DRV-PWM has the merits of maintaining the simplicity of the hardware coding for generating the switching signals. As explained in the previous section, the proposed method does not require any complex phase-shift tuning between Cell-II and Cell-III to achieve the desired output signals to construct vxn. Conversely, the conventional technique requires an additional coding to create a phase-shift between the switching signals sent to Cell-II and Cell-III. This increases the system complexity and restricts its flexibility from executing other functions properly. Undesirable switching signals are also present in the output waveforms.

4.3 Comparative Experimental Results of Conventional PSC-PWM and Proposed DRV-PWM

Figure 11 shows the experimental validation of the conventional and proposed switching techniques when MI is 1.15. In Fig. 11a, it can be seen that the conventional PSC-PWM can be implemented with sophisticated tuning of phase-shift among switching signals to achieve a similar form of vxn with undesirable switching that leads to high distortion in vxn. Nevertheless, the proposed DRV-PWM solves the issue of Td,PWM as shown in Fig. 11b. This results in less distorted vxn with a 5.7% improvement in the THD, as can be clearly seen from the fast Fourier transform (FFT) analysis of vxn in Fig. 11a and b for the conventional and proposed switching methods, respectively.

Fig. 11
figure 11

Experimental results of generating vAn: a Conventional PSC-PWM; b Proposed DRV-PWM

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Other sets of experimental results are given in Figs. 12 and 13 for the conventional and proposed techniques, respectively. These results show the three-phase output voltage and current waveforms. It can be seen from these figures that the conventional PSC-PWM suffers from Td,PWM issue, which results in asynchronous switching. This leads to higher voltage stress on some switching devices, which in turn degrades system reliability. Meanwhile, the proposed DRV-PWM generates a synchronous output voltage and current waveforms as desired. Moreover, the results shown in Fig. 14a highlight the effects of Td,PWM in disturbing the switching signals in the difference phases, where it can be seen that the A phase has clearer effects as the peaks of the vtri-1 and vtri-2 and other PWM signals are generated with respect to it, as shown in Fig. 4. The black-line triangular in this figure is magnified in Fig. 15a. In addition, the area near zero crossing (i.e., circle black-line area) also showed the disturbance on the switching signals and output vxn. The proposed method effectively eliminates the effects of the uneven losses distribution and PWM switching signals as shown in Figs. 14b and 15b, respectively. Thus, voltage stress and losses can be evenly distributed among three-phase switching devices.

Fig. 12
figure 12

Experimental results of conventional PSC-PWM: a Three-phase pole voltages; b Three-phase line-to-line voltages; c Output voltages and three-phase currents

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Fig. 13
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Experimental results of proposed DRV-PWM: a Three-phase pole voltages; b Three-phase line-to-line voltages; c Output voltages and three-phase currents

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Fig. 15
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Experimental magnified results of Td,PWM effects on vxn: a Conventional PSC-PWM; b Proposed DRV-PWM

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Fig. 14
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Experimental results of Td,PWM effects on vxn: a Conventional PSC-PWM; b Proposed DRV-PWM

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4.4 Numerical Comparative Analysis of Thermal Losses for Conventional PSC-PWM and Proposed DRV-PWM

To verify the capability of the proposed DRV-PWM technique to balance the thermal losses among the among three-phase switching devices, the system was operated at full MI for an hour using the conventional PSC-PWM. This procedure was repeated for the proposed PSC-PWM after allowing the system to completely cool down. The results were taken using a thermal camera, and are shown in Figs. 16, 17, and 18.

Fig. 16
figure 16

Investigation of thermal behavior of the three phases of five-level HANPC inverter: a Conventional PSC-PWM; b Proposed DRV-PWM

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Fig. 17
figure 17

Detailed investigation of Cell-III thermal behavior during the utilization of conventional PSC-PWM: a SA7 and SA8; b SB7 and SB8; c SC7 and SC8

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Fig. 18
figure 18

Detailed investigation of Cell-III thermal behavior during the utilization of proposed DRV-PWM: a SA7 and SA8; b SB7 and SB8; c SC7 and SC8

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Figure 16 depicts the effectiveness of the proposed DRV-PWM in reducing and balancing the thermal losses of Sx7 and Sx8 among the three phases of the five-level HANPC inverter. To obtain a detailed thermal measure of Sx7 and Sx8 in each phase, close-up measurements were taken as shown in Figs. 17 and 18 for the conventional and proposed techniques, respectively. It can be seen in Fig. 17 that the conventional PSC-PWM results in unevenly distributed thermal losses among three phases.

For example, SC7 and SC8 have the highest thermal losses, where the junction temperature TJ reaches a maximum value of 90.4 °C, and where the maximum temperature obtained in other two phases are at ≈ 66 °C. On the other hand, the proposed DRV-PWM maintains the maximum TJ at 72.7 °C for SC7 and SC8, whereas A-phase and B-phase achieve relatively lower temperatures of 63.1 °C and 60.9 °C, respectively. This is due to the total control time-delay of whole system. A summary of the thermal losses comparison between the conventional and proposed switching schemes is presented in Fig. 19. It can be seen that the proposed DRV-PWM technique manages to balance the thermal losses among the switching devices of the three-phase five-level HANPC inverter. Conversely, the conventional PSC-PWM method results in more stress on the C-phase. Therefore, the reliability and efficiency of system is enhanced by implementing the proposed DRV-PWM.

Fig. 19
figure 19

Investigation of thermal losses distribution for the three phases of five-level HANPC inverter: a Conventional PSC-PWM; b Proposed DRV-PWM

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5 Conclusion

This study presents a less complex but still effective and efficient DRV-PWM scheme for three-phase five-level HANPC inverters that can be used as an alternative to the conventional phase shifted PSC-PWM method. The proposed DRV-PWM simplifies the control structure by eliminating the need for complex phase adjustments and additional PWM carriers; therefore, it is recommended for various microcontrollers. The proposed switching scheme also results in a balanced distribution of thermal losses among the three phases, along with improved reliability and efficiency of the switching devices. The implementation process of the proposed DRV-PWM was explained and experimentally validated using a TMS320F28377S DSP. The results showed that the execution of the three-phase pole voltages was effectively synchronized, and that a balanced distribution of thermal losses was maintained. Further, the proposed DRV-PWM simplifies the hardware coding for generating the switching signals and improves the THD by 5.7%. Overall, the proposed DRV-PWM can be effectively implemented in three-phase five-level HANPC inverters to balance the switching losses and achieve optimal control of this topology.