1 Introduction

The feature size of traditional devices is scaling and the integration density is increasing with the rapid development of CMOS technologies, which leads to ever-growing problems, quantum effects, high leakage current and energy dissipation for instance (Sheikhfaal et al. 2015a). Searching for alternatives like novel nanodevices may be an efficient solution. Nanodevices include Carbon Nano Tube (CNT) (Bachtold et al. 2001), Single Electron Transistor (SET) (Kastner 1992), Tunneling-phase-logic (TPL) (Fahmy and Kiehl 1999), Quantum-dot Cellular Automaton (QCA) (Lent et al. 1993) and so on. Among them, QCA utilizing the Coulomb interaction between electrons doesn’t have traditional transistors and possesses the characteristics of high switching rate (Seminario et al. 2004), high integration density (DeHon and Wilson 2004), low energy dissipation (Farazkish et al. 2008) etc., which makes it one of the most promising candidates (Henderson et al. 2004). In recent years, QCA has been intensively studied and achieves a rapid development.

XORs are considered as one of the important modules in digital circuit design since they are frequently used in full adders, parity generators, shifting registers, default detecting circuits etc. (Kumar et al. 2017). Thus, a XOR with high performance is of great importance in improving circuit efficiency. As a complicated gate, XOR can be constituted with elementary gates, majority gates, NOT and NNI gates for example. The proposed gate-based XORs are manifold and can be classified into five different constructions according to components: (1) using three three-input majority gates (M3) and NOT gates (Jagarlamudi et al. 2011; Shah et al. 2012; Roohi et al. 2011; Suresh and Ghosh 2014; Kianpour et al. 2014; Mohammadi et al. 2017; Khosroshahy et al. 2017; Chabi et al. 2014; Singh et al. 2016; Mustafa and Beigh 2013; De et al. 2016; Teja et al. 2008; Beigh et al. 2013); (2) consist of four three-input majority gates and NOT gates (Mustafa and Beigh 2013; Beigh et al. 2013; Poorhosseini and Hejazi 2018); (3) based on a three-input majority gate, a five-input majority gate (M5) and NOT gates (Chabi et al. 2014; Singh et al. 2016; Angizi et al. 2014; Sasamal et al. 2018; Sheikhfaal et al. 2015b; Mohammadi and Navi 2018); (4) realized using four NNIs (Poorhosseini and Hejazi 2018); (5) employing a five-input majority gate and NNI (Zhang et al. 2020). In the hard work of researchers to seek for more efficient circuits, the properties of XORs are obtained optimization continuously.

The main contributions of the work in the article are summarized as follows. (1) A novel five-input majority gate is proposed to construct an efficient XOR using the fifth structure mentioned above (a five-input majority gate and NNI); (2) Compared with the existing designs, XOR put forward in the paper shows superiority with respect to physical properties; (3)Also, n-bit parity generators implemented utilizing the state-of-the-art XOR describe a bright application prospect.

The paper proceeds as follows. Section 2 reviews the basics of QCA. In Sect. 3, previous XOR designs are categorized into five types according to the rule referred to in Sect. 1. The new scheme of XOR and one of its applications-parity generators are presented and discussed in Sect. 4. And Sect. 5 concludes the work.

2 QCA basics

The elementary unit of QCA is QCA cells. As shown in Fig. 1a, a standard cell comprises four quantum dots and two free electrons. The electrons can tunnel between these quantum dots and are liable to occupy the diagonal positions because of the Coulomb interaction. Thus, the cell exists two steady states, namely polarization value \(P = - 1\) and \(P = + 1\), described in Fig. 1b, which is used to represent binary logic “0” and logic “1” respectively.

$$F = M\left( {A,B,C} \right) = AB + AC + BC$$
(1)
$$\begin{gathered} F = M\left( {A,B,C,D,E} \right) = ABC + ABD + ABE + ACD \hfill \\ + ACE + ADE + BCD + BCE + BDE + CDE \hfill \\ \end{gathered}$$
(2)
$$F = NNI\left( {A,B,C} \right) = A\overline{B} + A\overline{C} + \overline{B}\overline{C} = M\left( {A,\overline{B},\overline{C}} \right)$$
(3)
Fig. 1
figure 1

QCA cell, a Standard QCA cell, b Polarized cells

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As the primary gates in QCA, the majority voter and NOT gate can be used to realize all the complicated circuits theoretically. The inputs of majority voters include three inputs and five inputs. Figure 2a is a three-input majority voter (M3), whose logic function is shown in Eq. (1). A AND logic will be achieved if fixing one of the three inputs to the polarity value \(P = - 1\), as presented in Fig. 2b. Similarly, if the fixed polarity value is replaced by \(P = + 1\), a OR function will be acquired, as illustrated in Fig. 2c. Equation (2) is the expression of the five-input majority gate (M5), and its QCA structures have numerous forms. NNI can also be regarded as an elementary gate, whose logic function is shown in Eq. (3) (Sen and Sikdar 2007). Figure 3a exhibits the QCA structure of NNI. The truth table of NNI is shown in Table 1, which is in accord with the simulation results shown in Fig. 3b using the simulation tool QCADesigner. The bistable approximation simulation engine parameters of the tool is presented in Table 2. Based on these most basic gates above, any complicated circuits can be achieved in theory.

Fig. 2
figure 2

Three-input majority voter, a QCA structure, b AND, c OR

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Fig. 3
figure 3

NNI, a QCA structure, b Simulation results

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Table 1 The truth table of NNI
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Table 2 Bistable approximation simulation engine parameters
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QCA clock is applied to control the direction of the information flow normally (Lent and Tougaw 1997). QCA clock employing the quasi-adiabatic switch clock scheme contains four phases, namely switch, hold, release and relax, as shown in Fig. 4. \(\pi {/2}\) delay exists each of these adjacent phases. A complete clock cycle has four clock zones called clock 0, clock 1, clock 2 and clock 3. And the information transmits according to the direction of clock \({0} \to {1} \to {2} \to {3} \to {0} \to {1} \to \cdot \cdot \cdot\). The QCA clock scheme guarantees that the data will be flow follow the scheduled path.

Fig. 4
figure 4

QCA four-phase clock mechanism

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3 Classification of existing XORs

Existing XORs can be grouped into five types according to the components utilized, as presented in Table 3.

Table 3 Existing gated-based XORs
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4 New design schemes

4.1 Novel five-input majority voter

The novel XOR is designed using the fifth construction (a NNI and a five-input majority voter) in Table 3 with the logic function shown in Eq. (4). In order to achieve high-performance XOR, an excellent five-input majority voter is needed. Figure 5a exhibits the QCA structure of the five-input majority voter proposed in the paper. Since two inputs of the five-input majority voter are the same, as shown in Eq. (4), these two equal inputs are designed to share a common input called D. The other three inputs are A, B and C, and F is the output of the proposed five-input majority voter. Thus, the voter can gain the majority function among A, B, C, D and D, as is shown in Table 4. Figure 5b shows the simulation result of the proposed voter.

$$F = M5\left( {A,B,0,NNI\left( {A,B,1} \right),NNI\left( {A,B,1} \right)} \right)$$
(4)
Fig. 5
figure 5

The proposed five-input majority voter, a QCA structure, b Simulation results

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Table 4 The truth table of the proposed five-input majority voter
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4.2 Novel XOR

A new XOR is designed based on the five-input majority voter proposed above and NNI, as shown in Fig. 6a. Figure 6b presents the simulation result, which demonstrates the correctness of the function. In order to illustrate the superiority of the design, XOR in the paper is compared with previous ones in terms of cell count, area, clock delay, cross structure and average energy dissipation, as shown in Tables 5, 6 and Figs. 7, 8, 9 and 10. Through the analysis of these figures, XOR in the article has the least cell count (24 cells), the least area (0.0186 µm2), the least clock delay (0.75) and the least average energy dissipation. At the same time, the novel XOR design can easily be accessed with no crossover (Chaudhary et al. 2007). Figure 11 presents the power dissipation map for the proposed XOR gate at 0.5Ek tunneling energy level and 2.0 K temperature.

Fig. 6
figure 6

The proposed XOR, a QCA structure, b Simulation results

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Table 5 Performance figures of XORs
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Table 6 Energy dissipation of XORs at 2.0 K
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Fig. 7
figure 7

Cell counts for XORs

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Fig. 8
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Areas for XORs

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Fig. 9
figure 9

Clock delay for XORs

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Fig. 10
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Average energy dissipation for XORs

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Fig. 11
figure 11

Power dissipation map for the proposed XOR gate at 0.5Ek tunneling energy level and 2.0 K temperature

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The cost of a QCA circuits is also an important parameter for performance analysis. Area-delay cost (ADC), QCA-specific cost (QSC) and Energy-delay cost (EDC) are calculated respectively according to the formulas presented in Khan and Arya (2022). The area delay cost can be obtained using (Area) × (latency)2. The QCA-specific cost is (MV2 + IN + CV2) × CK2, where MV, IN, CV and CK represent the number of utilized majority voters, inverters, crossovers and clocks, respectively. E2 × D2 is used to calculate the energy-delay cost, where E is the dissipated energy and D is the latency. The cost calculation results of XORs are shown in Table 7 and the graphical view of comparisons are shown in Figs. 12, 13 and 14, respectively. Through these comparisons, Area-delay cost, QCA-specific cost and Energy-delay cost of the proposed XOR always keep the minimum.

Table 7 The cost of XORs
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Fig. 12
figure 12

Area-delay cost for XORs

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Fig. 13
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QCA-specific cost for XORs

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Fig. 14
figure 14

Energy-delay cost for XORs

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All these comparisons certify that the proposed XOR possesses the excellent properties.

4.3 Proposed parity generators

Utilizing the proposed XOR above, n-bit parity generators are implemented to illustrate the practicability. Figure 15a is the QCA circuit of 4-bit parity generator with 76 cells and 0.0820 µm2. A 0.25 clock delay (clock 3) is added to the connection between adjacent XORs so as to hold the original clock design of the XOR, which provides convenience to construct high-bit parity generators. The simulation result of the proposed 4-bit parity generator is shown in Fig. 15b.

Fig. 15
figure 15

The proposed 4-bit parity generator, a QCA structure, b Simulation results

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A comparison between the 4-bit parity generator in the paper and existing designs in cell count, area and average energy dissipation is needed to demonstrate the performance. Since the structure of the proposed circuit is coplanar with no rotated cells, the selected counterparts have the same characteristics, as shown in Fig. 16. The results can be seen from Table 8 and Figs. 17, 18 and 19. By contrasting the data, the novel 4-bit parity generator has the least values in term of cell count, area and average energy dissipation, up to 10.6%, 6.0% and 38.6% (0.5Ek) optimization compared to previous optimum values respectively. Therefore, the 4-bit parity generator based on XORs proposed in the paper has an excellent performance. Since the XOR is the elementary unit to construct the n-bit parity generators, the bit is higher, the optimization results are more significant. Figure 20 is the QCA design of the 32-bit parity generator.

Fig. 16
figure 16

Existing 4-bit parity generators

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Table 8 Performance figures of 4-bit parity generators
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Fig. 17
figure 17

Cell counts for 4-bit parity generators

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Fig. 18
figure 18

Areas for 4-bit parity generators

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Fig. 19
figure 19

Average energy dissipation for 4-bit parity generators

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Fig. 20
figure 20

The proposed 32-bit parity generator

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5 Conclusion

XOR occupies a significant position in algorithmic logic. To improve the physical properties of XOR, an efficient five-input majority voter is designed. Based on the proposed five-input majority voter and NNI, a novel XOR is implemented. The proposed coplanar XOR has an excellent performance with less cell count, area, energy dissipation, and QCA cost. Moreover, the inputs and output of the design are easier to access without any crossovers since they locate on the outside of the structure. The 4-bit parity generator utilizing the novel XOR also presents outstanding physical property improvement in cell count, area and energy dissipation compared to its counterparts. Since the XOR is the elementary unit to construct the n-bit parity generators, the bit is higher, the optimization results will be more significant. Based on the proposed XOR and 5-input majority gate, high-efficiency full adders will be constructed in the future.