1 Introduction

The typical technologies such as CMOS technology are faced with serious challenges such as short cannel effect [1, 2] and high fault tolerance at nano-scale [3]. Carbon-Nano-Tube Field Effect Transistors (CNTFETs), Spintronics, Silicon On Insulator (SOI) MOSFET and Quantum-dot Cellular Automata (QCA) are considered as replaced technologies [3,4,5,6,7,8,9,10,11,12,13,14]. The QCA technology is an emerging technology designed as an appropriate alternative to CMOS technology [7].

In the QCA technology, data is transmitted through polarization based on binary information encoding in quantum dot cells [9]. In recent years, many arithmetic circuits such as counter circuits [15,16,17,18,19,20,21,22,23], flip-flop circuits [15, 17,18,19, 22, 23], shift register circuits [24], full-adder circuits [25,26,27,28,29,30,31], multiplexer circuits [32, 33], switched network circuits [34], number generator circuits [35] and Cellular comparator circuits [36, 37] have been designed in the QCA technology.

One of the most used circuits in arithmetic circuits is the counter circuit. Kong et al. [15] have developed a 5-bit QCA counter circuit. This designed QCA counter circuit consists of 490 cells and 0.7992 μm2area.The authors of [16] have designed a 3-bit QCA counter circuit. This designed QCA counter circuit consists of 238 cells and 0.36 μm2 area. Aghababa et al. [17] have designed a 4-bit QCA counter circuit that consists of 232 cells and 0.20 μm2 area. Sarmadi et al. [18] have developed a 4-bit QCA counter circuit. This designed QCA counter circuit consists of 183 cells and 0.24 μm2 area. Angizi et al. [19] have presented a 4-bit QCA counter circuit, which consists of 422 cells and 0.46 μm2 area. Sheikhfaal et al. [20] have designed a 3-bit QCA counter circuit. This designed QCA counter circuit consists of 428 cells and 0.48 μm2 area. Sangsefidi et al. [21] have proposed a 4-bit QCA counter circuit. This designed QCA counter circuit consists of 273 cells and 0.26 μm2 area. Abutaleb [22] has designed a 3-bit QCA counter circuit. This designed QCA counter circuit consists of 196 cells and 0.22 μm2 area. Yang et al. [23] have designed a 3-bit QCA counter circuit. This designed QCA counter circuit consists of 616 cells and 1.2 μm2 area.

A common method to design a QCA counter circuit is mapping the circuits from CMOS technology to the QCA technology. Developing a building block circuit based on the QCA Flip-Flops (FFs) plays an important role in this method [19].

In this paper, new circuits are designed for implementation of 2-, 3-, 4- and 5-bit QCA counter circuits. First, an efficient modified D-FF circuit is designed and then the 2-, 3-, 4- and 5-bit QCA counter circuits are designed using this modified D-FF circuit as building block. The designed counters are implemented in one layer. The functionality of the designed circuits are verified using QCADesigner tool version 2.0.3.The simulation results indicate that the designed modified D-FF circuit consists of 13 quantum cells and 0.01 μm2 area. The 2-, 3-, 4-, and 5-bit QCA counter circuits contain 44 (0.03 μm2), 93 (0.07 μm2), 160 (0.13 μm2), and 245 (0.2 μm2) quantum cells (area). The comparison indicate that the designed circuits for the QCA counter have better performance compared to other QCA counter circuits in terms of cell count and area.

The rest of the paper is as follows: Section 2 provides a background of the QCA technology. Section 3 provides a general overview of the D-FF circuits and counter circuits in the QCA technology. In section 4, the designed circuits are presented. In section 5, the implementation results of the designed circuits are presented and evaluated. Finally, the paper is concluded in section 6.

2 Background

2.1 Cells in the QCA Technology

Cells in the QCA technology include four cavities located in the square corners. These cells have two electrons, which can freely move in the cavities and create two stable states [38]. These electrons are arranged in the diagonal manner. As a result, two poles of +1 (logic “1”) and − 1 (logic “0”) are created. Figure 1 shows these two stable states [24, 38].

Fig. 1
figure 1

A simplified QCA cell [24, 38]

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Polarization of the cells is calculated as follows [16, 38]:

$$ P=\frac{\left(P1+P3\right)-\left(P2+P4\right)}{P1+P2+P3+P4} $$
(1)

Where Pi denotes the electric charge at ith point. Binary information is displayed using these electrons position in logical cells [9].

2.2 Gates in the QCA Technology

The basic QCA logic gates include the inverter gate and majority gate. Several types of inverter and majority gates are shown in Fig. 2 [9, 39, 40].

Fig. 2
figure 2

The basic gates in the QCA technology: a inverter gates, b three-input majority gate [9, 39, 40]

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The output of the inverter gate is the inverse of the input [9, 24]. In addition, the three-input majority gate consists of at least five QCA cells [9, 39,40,41]. The output of the three-input majority gate is computed as follows [24]:

$$ \mathrm{M}\left(\mathrm{A},\mathrm{B},\mathrm{C}\right)=\mathrm{AB}+\mathrm{CA}+\mathrm{CB} $$
(2)

3 Flip-Flop and Counter

3.1 Flip-Flop

The sequential circuits, which have two stable states output and can store at least one bit, are called flip-flops. Flip-flops can be categorized in 4 groups: T-FF, JK-FF, RS-FF and D-FF [35]. The D-FF is used as a register cell. It is because the D-FF can save its input data and shows this data in output after each clock cycle. The truth table for the D-FF is illustrated in Table 1 [42].

Table 1 The truth table for the D-FF [42]
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It should be noted that if the inverse of the D-FF output is used as the D-FF input, it can be used as a semi-oscillator circuit [17].

3.2 Counter

The counters are a class of sequential logics that are implemented using register-type circuits such as Flip-Flops. Counters can be categorized in several groups such as: asynchronous (ripple) counters, synchronous counters, cascaded counters and modulus counters [17]. The counter circuit plays an important role in the arithmetic circuits. As a result, several attempts have been done to implement efficient counter circuits especially in the QCA technology, which will be considered in the next section.

3.3 Previous QCA Counter Circuits

Figure 3 shows the previous designed counter [15,16,17,18,19, 21,22,23].

Fig. 3
figure 3figure 3figure 3figure 3

The utilized QCA circuit for a 3-bit counter in [23], b 3-bit counter in [16], c 4-bit counter in [17], d 4-bit counter in [18], e 4-bit counter in [19], f 4-bit counter in [21], g 3-bit counter in [22], h 5-bit counter in [15]

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Yang et al. [23] have proposed a 3-bit synchronous counter that is illustrated in Fig. 3a. This designed counter consists of 616 cells and 1.2 μm2 area. The authors of [16] have designed 3-bit synchronous counter, which is illustrated in Fig. 3b. This design consists of 238 cells and 0.36 μm2 area. Aghababa et al. [17] have developed a 4-bit counter that is illustrated in Fig. 3c. This designed counter consists of 232 cells and 0.20 μm2 area. Sarmadi et al. [18] have presented a 4-bit QCA counter, which is shown in Fig. 3d. This designed counter consists of 183 cells and 0.24 μm2 area. Angizi et al. [19] have presented a 4-bit counter that is illustrated in Fig. 3e. This designed counter consists of 422 cells and 0.46 μm2 area. Sangsefidi et al. [21] have developed 4-bit QCA synchronous counter, which is illustrated in Fig. 3f. This counter consists of 273 cells and 0.26 μm2 area. The author of [22] have designed a 3-bit cascading three level-sensitive D-FFs, which is illustrated in Fig. 3g. This design consists of 196 cells and 0.22 μm2 area. Kong et al. [15] have developed a 5-bit QCA counter that is illustrated in Fig. 3h. This designed counter consists of 490 cells and 0.7992 μm2 area.

4 The Designed Circuits

In this section, we propose novel QCA circuits for the counter. The designed QCA counter circuits are based on the modified D-FF circuit that is developed in this paper.

4.1 The Modified D-FF Circuit

Figure 4 shows the designed modified D-FF circuit.

Fig. 4
figure 4

The designed modified D-FF circuit a schematic design, b QCA layout

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The designed modified D-FF circuit has an input and an output, which are shown by clock and out1, respectively. The designed circuit is composed of a new D-FF in which the inverse of the D-FF output is utilized as D-FF input. It contains 13 quantum cells and 0.01 μm2 area. This modified D-FF circuit is used as the building block for design of QCA counter circuits.

4.2 The Designed Counter Circuit

Figure 5 shows the designed circuit for 2-bit QCA counter.

Fig. 5
figure 5

The designed circuit for 2-bit QCA counter

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The designed 2-bit QCA counter circuit has clock input and two outputs, out1 and out2. The designed circuit for the 2-bit QCA counter has 44 quantum cells and 0.03 μm2 area.

It should be noted that this counter can be easily extended to n-bit QCA counter. Figures 6, 7 and 8 shows the designed circuits for 3-, 4-, and 5-bit QCA counter based on designed modified D-FF circuit, respectively. These designed circuits have clock input and n outputs, out1, out2, out3, …, and outn corresponding to the n-bit counter circuits.

Fig. 6
figure 6

The designed circuit for 3-bit QCA counter

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Fig. 7
figure 7

The designed circuit for 4-bit QCA counter

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Fig. 8
figure 8

The designed circuit for 5-bit QCA counter

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The designed circuits for the 3-, 4-, and 5-bit QCA counter have 93 (0.07 μm2), 160 (0.13 μm2) and 245 (0.20 μm2) quantum cells (area), respectively.

5 The Simulation Results and Comparison

The QCADesigner tool version 2.0.3 is used to verify the functionality of the designed QCA circuits. The utilized parameters for the simulation is shown in Table 2.

Table 2 The utilized parameters for the simulation
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5.1 The Modified D-FF Circuit

Figure 9 shows the simulation results of the modified D-FF circuit.

Fig. 9
figure 9

The simulation results of the modified D-FF circuit

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Figures 10, 11, 12 and 13 show the simulation results of the designed 2-, 3-, 4-, and 5-bit QCA counter circuits.

Fig. 10
figure 10

The simulation results of the designed 2-bit QCA counter circuit

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Fig. 11
figure 11

The simulation results of the designed 3-bit QCA counter circuit

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Fig. 12
figure 12

The simulation results of the designed 4-bit QCA counter circuit

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Fig. 13
figure 13

The simulation results of the designed 5-bit QCA counter circuit

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The simulation results indicate that the outputs of the designed QCA counter circuits are correctly obtained. Table 3 shows the simulation results of the designed QCA counter circuits compared with other counter circuits in [15,16,17,18,19,20,21,22,23]. The cost is computed using Eq. (3) [30]:

$$ \mathrm{Cost}=\mathrm{Area}\left({\upmu \mathrm{m}}^2\right)\times \mathrm{Delay}\left(\mathrm{Cycle}\ \mathrm{cycle}\right) $$
(3)
Table 3 Comparison table for the QCA counter circuits
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Based on the simulation results that are summarized in Table 3, the cell count, area and cost of the designed 2-bit QCA counter circuit are considerably improved compared to 2-bit QCA counter circuits in [15, 16, 19,20,21,22,23]. The only 2-bit QCA counter circuit that has the same cost compared to the developed 2-bit QCA counter circuit is the 2-bit QCA counter circuit in [21]. However, the area and cell count in this circuit are about 2 and 1.7 times bigger than the designed 2-bit QCA counter circuit.

Moreover, the cost, cell count, and area of the designed 3-bit QCA counter circuit are considerably improved compared to 3-bit QCA counter circuits in [15, 16, 19,20,21,22,23].

In addition, the cell count, area and cost of the designed 4-bit QCA counter circuit are considerably improved compared to 4-bit QCA counter circuits in [15,16,17,18,19,20,21, 23]. The only 4-bit QCA counter circuit that has a slightly better cost than the designed 4-bit QCA counter circuit is the 4-bit QCA counter circuit of [19]. However, the area and cell count in this circuit are about 3.5 and 2.6 times bigger than the designed 4-bit QCA counter circuit. In addition, the only 4-bit QCA counter circuit that has the same cost compared to the designed 4-bit QCA counter circuit is the 4-bit QCA counter circuit in [21]. However, the area and cell count in this circuit are about 2 and 1.7 times bigger than the designed 4-bit QCA counter circuit.

For 5-bit QCA counter circuit, the cell count, area and cost of the designed QCA counter circuit are considerably improved compared to QCA counter circuit in [15].

6 Conclusion

In the QCA circuits design, counters are the most used circuits. In this paper, 2-, 3-, 4- and 5-bit coplanar counter circuits were designed based on the modified QCA D-FF circuit designed in this paper. In the modified D-FF circuit, the inverse of the D-FF output was used as D-FF input. The designed circuits were simulated and verified by using the QCADesigner tool version 2.0.3. The developed coplanar counter circuits for the 2-, 3-, 4-, and 5-bit QCA counter have 44 (0.03 μm2), 93 (0.07 μm2), 160 (0.13 μm2), and 245 (0.20 μm2) quantum cells (area), respectively. The comparison results demonstrate that the designed QCA counter circuits have improvements compared with other counter circuits in [15,16,17,18,19,20,21,22,23] in terms of cell count, and area.