1 Introduction

Tunneling FET is considered as the most promising device to substitute the MOSFET device due to its sub 60 mV/decade subthreshold swing (SS) and low leakage current. TFET is superior to MOSFET in terms of short channel effects (Wang et al. 2004; Choi et al. 2007; Avci et al. 2015). The major drawbacks faced by TFET devices are low ON-state current and intrinsic ambipolarity (Fuketa et al. 2015; Wang et al. 2016; Chen et al. 2014; Datta et al. 2014; Strangio et al. 2015; Dash et al. 2016). Unlike MOSFET, the working mechanism of TFET is Band to Band tunneling (BTBT). In n-TFET carriers injection depends on electrons BTBT from the valance band (VB) of degenerate p + source to the conduction band (CB) of the channel in presence of positive gate voltage (Bhuwalka et al. 2004; Ionescu 2008; Agarwal et al. 2010; Asra et al. 2011; Ionescu and Riel 2011; Verhulst et al. 2012). In this framework, we modify the SOI structure of U-shaped channel TFET (UTFET) (Wang et al. 2014) by extending the gate over the source pocket and propose a Gate-Extended-U-shaped channel TFET (GE-UTFET) structure. The proposed structure was simulated by means of santaurus technology computer added design (TCAD) (Sentaurus 2014) to investigate the DC and analog/RF performance. The performance of the UTFET and GE-UTFET are examined in terms of various parameter such as drain current (Id), transconductance (gm), subthreshold swing (SS), total gate capacitance (Cgg), gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd), and RF FOMs like fT and fA.

The device structure and the methodology adopted for this study are elaborated in Sect. 2. The results of the investigation are present in Sect. 3. Finally, Sect. 4 concludes the study by summarizing important findings.

2 Device structure and methodology

The 2D schematic SOI structure of UTFET and GE-UTFET are shown in Fig. 1a, b respectively. Both the structures are identical except the extended gate over the source pocket region for GE-UTFET. Germanium source was used in the devices to improve the drive current due to its narrower bandgap as compared to silicon (Kim et al. 2009). Unlike planner TFET, the recessed gate is used in UTFET to increase the channel effective length. The line tunneling was incorporated in both the structures by introducing an L-shaped n + pocket region between the source and gate oxide (Wang et al. 2017; Cao et al. 2011; Abdi and Kumar 2014). The presence of both point tunneling (perpendicular to gate field) and line tunneling (parallel to gate field) enhance the ON-state current of GE-UTFET. Due to the extended gate over the pocket region the electric field increases in the region which induce higher BTBT generation rate, and helps in increasing the drain current at ON-state for GE-UTFET. Figure 2a, b show the energy band profile of GE-UTFET and UTFET at ON-state. In GE-UTFET the gate length is extended up to Lext in the source side so that it overlaps on the small n + pocket region. All the device parameters along with its dimensions are mentioned in Table 1. Gate material used in the structure was TiN with a work function of 4.66 eV. The drain doping (Nd = 1 × 1018 cm−3) was kept lower than source doping (Na = 1 × 1020 cm−3) to restrain the ambipolar behavior (Narang et al. 2012). We studied the device performance of GE-UTFET for change in device geometric parameters like gate extension length (Lext), pocket doping (Np) and back gate voltage (VBG) applied at the substrate.

Fig. 1
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2D schematic structure of a UTFET b GE-TFET

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Fig. 2
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Energy Band profile of GE-UTFET and UTFET along a C1 cutline and b C2 cutline at ON state

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Table 1 Device parameter and dimension
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Different physical models used in the simulation for this study were Dynamic non-local BTBT model, Fermi–Dirac model, and doping dependent mobility model. Dynamic Non-local BTBT model with default parameter was included in the simulation for the non-local generation of electrons and holes and for a more accurate model of the tunneling process. Bandgap narrowing (BNG) model was used to incorporate the reduction in bandgap due to the high doping concentration in the semiconductor material.

Two cut-line C1 and C2 are considered at the source and pocket regions along the horizontal and vertical direction respectively to observe the tunneling phenomenon of the devices. The supply voltages used for this study were VDS = 0.8 V, VGS = 1.5 V. The back-gate voltage (VBG) of 0 V is considered for the analysis unless stated differently. At OFF-state (VGS = 0 V, Vds = 0.8 V) there are no vacant states available in the CB of the pocket region i.e. the VB of the source region is lying above the CB of the pocket region. Hence, no BTBT occurs from source to pocket. Whereas, at ON-state (VGS = 1.5 V, VDS = 0.8 V) as evident in Fig. 2, the positive gate voltage shifts conduction band of pocket region downward. Thus conduction band crosses the valance band of the source region and electron starts tunneling from source to pocket. It is clearly visible from the band diagram that the tunneling is more in case of GE UTFET as compared to the UTFET as the vacant state available in the former is more due to enhanced band banding. The gate extension over the pocket region in GE-UTFET increases the electric field at the tunneling interface which leads to the enhancement in band banding and subsequently reduces the tunneling width. The electron BTBT from source to channel through the pocket region for GE-UTFET is shown in Fig. 3.

Fig. 3
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Electron band to band tunneling (cm−3 s−1) for GE-UTFET

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The Average SS was extracted using the following expression,

$$AvgSS = \frac{VT - Voff}{{\log (IT - Ioff)}}$$
(1)

where Voff signifies the gate voltage at Ioff. The threshold voltage, VT was extracted using the constant current method at IT = 1 × 10–7 A. The important RF parameters fT and fA was extracted by performing small-signal analysis at 1 MHz. The frequency of unity current gain (fA) and gain-bandwidth product or GBW (fA) are expressed as (Vijayvargiya and Vishvakarma 2014),

$$fT = \frac{gm}{{2\pi (Cgd + Cgs)}}$$
(2)
$$fA = \frac{gm}{{2\pi 10Cgd}}$$
(3)

3 Results and analysis

The performance evaluation is done by both DC and analog performance analysis of the devices. The DC performance of UTFET and GE-UTFET are discussed in Sect. 3.1. The analog/RF performance in terms of Cgg, Cgs, Cgd, fT, and fA is examined in Sect. 3.2.

3.1 DC performance of GE-UTFET

Transfer characteristics curve for different drain voltages ranging from 0.1 V to 1.2 V is depicted in Fig. 4a. It is observed that both the ON and OFF-state current increases with an increase in drain voltage. The ambipolar current increases with drain voltage due to increase in drain to source tunneling. It is observed from Fig. 4b that as the extended gate length (Lext) over the pocket region increases, the ON current also increases. It is attributed to the increase in electric field at source pocket interface which in turn enhance the band banding at the tunneling interface. The variation of transfer characteristics with the n+ pocket doping concentrations (1 × 1017 cm−3 to 1 × 1019 cm−3) keeping other parameters constant for GE-UTFET is shown in Fig. 4c. It is evident that the increase in the doping concentration of n+ pocket increases Ion of the device due to easier formation of inversion at the pocket region. But the off-state leakage current almost remains same with changing pocket doping concentration.

Fig. 4
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ID–VG characteristics of GE-UTFET with a variation in aVDS, bLext, cNP

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The effect of back-gate voltage (VBG) on the transfer characteristics are studied for Bulk (Yang 2016) and SOI structure of GE-UTFET. It is clear from Fig. 5 that back gate voltage (VBG) has no impact on the SOI structure because of the BOX layer at the device. But for bulk structure it affects the OFF-state leakage current as well as threshold voltage of the device. However, it does not influence the ON-state of the device. For VBG = − 1 V, the Ioff degraded to the order of 10–9 A/µm as compare with the ~ 10–13 A/µm at VBG = 0 V. While, in case of VBG = 1 V, the threshold voltage increases to 0.8 V from 0.55 V at VBG = 0 V.

Fig. 5
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Impact of back-gate voltage on a SOI GE-UTFET, b bulk GE-UTFET

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The transfer characteristics of GE-UTFET and UTFET is shown in Fig. 6 for both linear and logarithmic scale. On current of 6.57 × 10–4 A/µm is observed for GE-UTFET while UTFET gives an Ion of 3.61 × 10–4 A/µm. The switching ratio, Ioff, Ion, and average SS of UTFET and GE-UTFET are compared and listed in Table 2. An improved ON-state current and sub-threshold swing are observed in case of GE-UTFET as compared with the UTFET.

Fig. 6
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Transfer characteristics for GE-UTFET and UTFET

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Table 2 Performance comparison between GE-UTFET and UTFET
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The variation of transconductance with VGS at VDS = 0.8 V has been analyzed for both the devices. A better result of gm for the proposed structure as compared to UTFET is clearly visible from Fig. 7. The output characteristic of GE-UTFET and UTFET at different gate voltage (VGS = 0.8 V and 1.0 V) is depicted in Fig. 8. In GE-UTFET due to the extended gate over the pocket, the tunneling junction area experience more electric field result in more band bending and more current compared to UTFET.

Fig. 7
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Transconductance variation with gate voltage for GE-UTFET and UTFET

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Fig. 8
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Output characteristics of GE-UTFET and UTFET

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3.2 Analog/RF performance of GE-UTFET

In this section, the analog/RF performances of the devices are examined in terms of Cgg, Cgd, Cgs, fT, and fA. The dependence of the total gate capacitance Cgg on the supply voltage leads to the difference in RF performances of the devices under consideration. Cgg which is a combination of Cgd and Cgs is extracted using small-signal AC simulation at 1 MHz (Yang et al. 2010).

At low gate bias, gate capacitance comprises of parasitic capacitance due to lack of inversion layer. But as the gate voltage increases the inversion takes place from drain to source side which enhances the gate capacitance with gate bias (Paill et al. 2004). Cgd constitutes a larger fraction of total capacitance in TFET due to high source-channel potential barrier. The reduction in the potential barrier at channel-drain interface with gate voltage increases the Cgd exponentially. The gate capacitance is dominated by Cgd at higher gate voltage. Figure 9 shows the variation of intrinsic capacitances (Cgg, Cgs, and Cgd) for GE-UTFET and UTFET with the gate voltage. It is clear from Fig. 9 that due to the extended gate over the pocket region Cgs increases which reduce the miller capacitance Cgd of GE-UTFET.

Fig. 9
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Variation of aCgg, bCgs and cCgd with gate voltage for GE-UTFET and UTFET

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Figures 10 and 11 shows the variation of fT and fA characteristics of GE-UTFET and UTFET with gate voltage. The fT which is a function of gm and Cgg has been extracted using (2). It is evident from Fig. 10 that fT increases with gate bias. It is attributed to the increased transconductance with the gate voltage as discussed earlier. fT attains the maximum and then falls with gate voltage due to the mobility degradation (Hoyniak et al. 2013). A higher value of fT is observed due to reduced Cgd in case of GEUTFET.

Fig. 10
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Variation of fT with gate voltage

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Fig. 11
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Gain Bandwidth products (fA) as functions of gate voltage

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As evident from (3) another RF figure of merit fA is proportional to the ratio gm/Cgd. Hence, fA increases with gate voltage because of the enhanced gm and reduced Cgd as shown in Fig. 11. As the transconductance of GE-UTFET (~ 1.45 × 10–3 S/µm) is higher than UTFET (~ 9 × 10–4 S/µm), the fA is larger in GE-UTFET. After attaining the peak, GBW decreases with higher gate voltage due to mobility degradation and parasitic capacitance. A significantly improved result of GBW is obtained for GE-UTFET.

4 Conclusion

The DC and RF performance comparisons of proposed structure GE-UTFET and UTFET are examined in this study by using Sentaurus TCAD tool. The simulation results reveal that a good average SS of 50 mV/decade and a switching ratio of the order of 109 are witnessed for GE-UTFET. Meanwhile, GEUTFET and UTFET show almost similar DC characteristics up to the gate voltage of 0.8 V. However, gradual differences are observed in their transfer characteristics for VGS above 0.8 V due to the different electric field experienced by the pocket region. Due to the lower miller capacitance and higher value of transconductance, the GE-UTFET have better frequency characteristics showing almost 62% more fT and fA than its counterpart UTFET. All the simulation results above demonstrate GE-UTFET is more suitable for a high-frequency application while comparing with UTFET. Furthermore, the role of back gate voltage on the electrical characteristics also demonstrated briefly in this paper.

It can be concluded from the results obtained in this study that the structural modification technique like gate overlap on source pocket can also be implemented to any TFET device with source pocket to enhance its analog and RF performance.