1 Introduction

With the continuing development of wireless technology and commercial electronic devices, the internet of things (IoT) has become a technological trend that enables ordinary objects capable of exercising independent functions to implement interoperable networks. Cisco is expected to have an IoT market worth US$ 19 trillion within the next decade [14], and analysts have predicted that IoT applications will connect 36 billion devices by 2020 [32]. Energy harvesting plays a key role in IoT applications. Compared with thermal, photovoltaic (PV) [2], and piezoelectric energy harvesting technologies [22, 33], radio frequency (RF) energy harvesting is more suitable for use in low-power, low-cost IoT systems such as wireless sensor platforms [1, 5, 13, 19, 24, 27,28,29]. As shown in Fig. 1, the working principle of an energy harvester for low-power IoT system applications entails the transmission of an RF alternating current (AC) signal to a near-field coupling coil using a power transmitter and its conversion using a rectifier. The AC signal received by the coupling coil is converted to direct current (DC) power supply and used in a load system that is input to a low-dropout regulator (LDO) to produce a stable DC supply.

Fig. 1
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Block diagram of an energy harvester for use in low-power IoT system

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In the standard CMOS process, the diodes are generally easily replaced by the diode-connected MOS. However, this architecture is affected by the threshold voltage \((V_{\mathrm{TH}})\), and the instantaneous voltage change through transistor-based switches caused by channel resistance results in the reduction in the output voltage, which in turn affects the overall power conversion efficiency (PCE) [15]. Therefore, many rectifier architectures, such as the gate cross-coupled rectifier (GCCR) [31], fully cross-coupled rectifier (FCCR) [3, 6, 9], rectifier with unbalanced-biased comparators (RUBC) [8], and rectifier with bootstrapping circuit (RBC) [11, 26], have been proposed.

The remainder of this paper is organized as follows: Sect. 2 discusses the architecture and characteristics of conventional rectifier topologies. Section 3 presents the proposed rectifier topology based on maximum power point tracking (MPPT) and describes its circuit. Section 4 presents the experimental results of the proposed rectifier and compares it with those of other topologies. Concluding remarks are provided in Sect. 5.

Fig. 2
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Full-wave bridge rectifier (FWBR)

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2 Analyses and Comparisons of Conventional Rectifiers

The full-wave bridge rectifier (FWBR) is one of the most common rectifier structures and the most widely implemented full-wave rectifier structure, as shown in Fig. 2. Compared with half-wave rectifiers, it exhibits higher power conversion and lower ripple voltages [31]. The FWBR consists of four diodes and does not require a center-tapped transformer. Because diodes connected to the load are used, a difference is generated between the output voltage \((V_{\mathrm{OUT}})\) and AC input voltage \((V_{\mathrm{AC}})\) for the \(V_{\mathrm{TH}}\) values of these two diodes.

Fig. 3
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Gate cross-coupled rectifier (GCCR)

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The GCCR [31] implements the full-wave rectifier with all MOS transistors, as shown in Fig. 3. The GCCR and FWBR differ in that two diodes in the GCCR are replaced by N-type MOS (NMOS)-based switches \(M_{3}\) and \(M_{4}\), and the NMOS gate is connected directly to the signal source to obtain a greater voltage swing, thereby enabling the transistor to instantaneously switch between the cutoff and linear regions. Therefore, the favorable transmission characteristics of the low voltage potential in the NMOS-based switch can effectively reduce the output voltage loss caused by the threshold voltage, resulting in higher PCE. However, the GCCR uses diode-connected p-channel MOS (PMOS) switches \(M_{1}\) and \(M_{2}\) connected to the load, resulting in a variation in the output voltage and AC input voltage for the \(V_{\mathrm{TH}}\) of one diode. In low-voltage operation, the voltage conversion efficiency (VCE) degrades considerably because of the \(V_{\mathrm{TH}}\), thereby directly affecting the PCE. The \(V_{\mathrm{OUT}}\), VCE, and PCE are defined as:

$$\begin{aligned} V_\mathrm{OUT}= & {} V_\mathrm{AC} -V_\mathrm{TH} \end{aligned}$$
(1)
$$\begin{aligned} \hbox {VCE}= & {} \frac{V_\mathrm{OUT} }{V_\mathrm{AC} }\times 100\% =\frac{V_\mathrm{AC} -V_\mathrm{TH} }{V_\mathrm{AC} }\times 100\% \end{aligned}$$
(2)
$$\begin{aligned} \hbox {PCE}= & {} \frac{P_\mathrm{RL} }{P_\mathrm{IN} }\times 100\% =\frac{V_\mathrm{OUT} \times I_\mathrm{RL} }{P_\mathrm{IN} }\times 100\% \end{aligned}$$
(3)

where \(P_{\mathrm{RL}}\) is the power consumed by the load, \(P_{\mathrm{IN}}\) is the total power input, and \(I_{\mathrm{RL}}\) is the current flowing through the load.

Fig. 4
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a Full cross-coupled rectifier (FCCR). b Condition of the reverse current on PMOS transistors \(M_{1}\) and \(M_{2}\)

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Fig. 5
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Simulation results for FCCR under various PCE characteristic curves

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The FCCR [6] differs from the GCCR in that it contains four MOS-based switches (\(M_{1}-M_{4})\) in the two main branches, and each gate is cross-connected to the other input signal, as shown in Fig. 4a. In contrast to the GCCR, the FCCR circuit solves the problem caused by the output drop by using a full-switch form. However, it cannot achieve high PCE in an operation over a wide voltage range because it experiences reverse current on PMOS transistors \(M_{1}\) and \(M_{2}\) [9], as shown in Fig. 4b. To reduce the difference between the input and output instantaneous voltages in order to suppress the occurrence of reverse current, relative coupling capacitances \(C_{\mathrm{C1}}\) and \(C_{\mathrm{C2}}\) are required during high-voltage operation for achieving high conversion efficiency. Therefore, using reverse current to charge the coupling capacitance improves the input DC level.

Notably, on adjusting the size and the corresponding coupling capacitance, the FCCR yields different peaks in the PCE characteristic curve, as shown in Fig. 5. The simulation results all have shunt loads of \(C_{\mathrm{L}}= 400\, \hbox {pF}\) and \(R_{\mathrm{L}}= 70\,\Omega \) under various AC input voltages. Consequently, increasing the size of all transistors to enhance the current drive capability, which in turn increases the output load voltage, is essential for achieving the ideal PCE peak in low-voltage operation. Because the input signal is small and the output voltage is relatively low in the FCCR, the problem of reverse current is not too concerning and thus no coupling capacitance aid is required. By contrast, obtaining the ideal PCE peak in high-voltage operation does not require an extremely large transistor size to enhance drive capability, but does require auxiliary coupling capacitance to avoid excessive reverse current.

As shown in Fig. 6, the RUBC [8] is based on the FCCR, with the only difference being that the RUBC contains two PMOS transistors controlled by two unbalanced-biased comparators that enable the circuit to more precisely control the switching behavior. Power PMOS transistors \(M_{1}\) and \(M_{2}\) are switched on only when the moment input voltage is higher than the output voltage, thereby effectively preventing reverse current without coupling capacitance. Therefore, the RUBC occupies a smaller area but achieves higher PCE performance than does the FCCR when the operation voltage is high. The RUBC exhibits good PCE character curves in high-voltage operation; however, as a trade-off for the high conversion efficiency, the two unbalanced-biased comparators require a certain degree of input voltage drive to operate normally; thus, achieving high efficiency in low-voltage operation is a substantial challenge for the RUBC.

Fig. 6
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Rectifier with unbalanced-biased comparators (RUBC)

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Fig. 7
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Rectifier with bootstrapping circuit (RBC)

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In most rectifier topologies, the \(V_{\mathrm{TH}}\) of components decreases the conversion efficiency in low-voltage operation. Only the FCCR can achieve optimal conversion; however, it cannot maintain high PCE over a wide input voltage range because of reverse current. As shown in Fig. 7, the RBC [11, 26] uses bootstrapping diodes \(M_{1}\), \(M_{5}\), \(M_{7}\), and \(C_{1}\) and \(M_{2}\), \(M_{6}\), \(M_{8}\), and \(C_{2}\) with \(V_{\mathrm{TH}}\) values lower than those of the diode-connected MOS connected to the load in order to obtain higher VCE and more favorable PCE curves. Therefore, the RBC has the potential to mitigate the problems of low voltage input and a wide input voltage range.

In Eq. (4), in contrast to the conventional diode-connected PMOS structure, the effective \(V_{\mathrm{TH}} (V^{\prime }_{\mathrm{TH}})\) of the circuit is reduced. Thus, reducing the \(V^{\prime }_{\mathrm{TH}}\) of a standard MOS transistor can increase the output voltage range for an input source voltage:

$$\begin{aligned} V_\mathrm{OUT} =V_\mathrm{AC} -V^{{\prime }}_\mathrm{TH} =V_\mathrm{AC} -(\left| {V_\mathrm{TH1} } \right| -V_\mathrm{TH5} ) \end{aligned}$$
(4)

where the \(V_{\mathrm{TH}}\) values of MOS transistors \(M_{1} (V_{\mathrm{TH1}})\) and \(M_{5}(V_{\mathrm{TH5}})\) are equal to those of MOS transistors \(M_{2} (V_{\mathrm{TH2}})\) and \(M_{6}\) \((V_{\mathrm{TH6}})\), respectively.

Figure 8 shows the PCE characteristic curves for the GCCR, FCCR, RUBC, and RBC at the same power transistor size and under a shunt load of \(C_{\mathrm{L}} = 400\, \hbox {pF}\) and \(\hbox {R}_{\mathrm{L}} = 70\,\Omega \). Evidently, the RBC is an evolved version of the GCCR, but it is not as efficient as the FCCR is in low-voltage operation or the RUBC is in high-voltage operation.

Fig. 8
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PCE curves for GCCR, FCCR, RUBC, and RBC

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Table 1 Feature comparison of various topology rectifiers
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Table 1 and the aforementioned description and figures illustrate the advantages and disadvantages of various rectifier topologies and their appropriate operating conditions. In recent years, more and more MPPT techniques are used in the energy harvesting circuits to enhance efficiency [4, 23, 25, 33]. Therefore, this study combines the advantages of the FCCR [6] and RBC [11] with the concept of MPPT technique. Through dynamic sensing, the various output voltage conditions required to switch to the most suitable circuit operation mode at any time were obtained to effectively enhance the input voltage range and operating bandwidth and upgrade the overall PCE under different input conditions in correlation with the many system specifications, thereby achieving the goals of low input voltage, wide harvesting range, wide band, and high efficiency.

3 Design of the Proposed Rectifier

As shown in Fig. 8, among the analyzed topology rectifiers, the FCCR exhibits the best PCE performance for low-voltage operation, and it does not require coupling capacitances (Ver. 3 of Fig. 5), thereby greatly reducing the required chip area. In addition, because the FCCR directly controls the MOS switches from the signal input, the PCE characteristic is almost completely unaffected by the different frequency. Therefore, the FCCR is the preferred circuit for low-voltage and wide-frequency operation. For high-voltage operation, the PCE characteristic of the RUBC is the best. However, the use of comparators results in significant degradation of the PCE curve of the RUBC in high-frequency operation. Therefore, the RUBC exhibits lower performance than does the RBC in relatively high-frequency operation.

To achieve maximum PCE under various operating voltages and frequencies, this paper proposes an MPPT-based structure with a wide harvesting range, wide band, and high efficiency. Figure 9 shows the basic concepts used in this work. The proposed rectifier is controlled by a dynamic output voltage detector (DOVD) that combines the advantages of the FCCR in low-voltage operation as shown in Fig. 9a and the RBC in high-voltage operation as shown in Fig. 9b. Figure 9c shows the proposed rectifier is extended by combining both curves in Fig. 9a, b. Because of its compact architecture, the proposed rectifier can reduce the parasitic effects of internal and external nodes and remain unaffected by the variation in input frequency. Therefore, the proposed rectifier can maintain high PCE in both low-voltage operation and high-voltage operation.

Fig. 9
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Efficiencies of the conventional rectifier a FCCR and b RBC and c the PCE of the proposed rectifier

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Fig. 10
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a Concept diagram of wide-input-voltage-range CMOS rectifier with DOVD; b operating principle under low voltage as FCCR mode; c operating principle under high voltage as RBC mode

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Figure 10a shows a concept diagram of the wide-input-voltage-range CMOS rectifier with DOVD, where the power transistor MOS \(M_{1}-M_{4}\) is the main path transistor, and all the power transistor MOS operate at linear region as switches with low on-resistance as Eq. 5. As a result, it can reduce voltage drops to achieve higher voltage conversion ratio. When the AC input signal is insufficiently high, \(V_{\mathrm{OUT}}\) is relatively low. Consequently, the DOVD provides diode-connected PMOS \(M_{6}\) with a path to ground to send output power transistor PMOS \(M_{5}\) into the linear region as a switch (Fig. 10b), resulting in the FCCR circuit mode for low-voltage operation achieving a high PCE without coupling capacitance. Thus, the \(V_{\mathrm{OUT}}\) of FCCR mode is given by Eq. 6. By contrast, when the \(V_{\mathrm{OUT}}\) is relatively high, the DOVD \(V_{\mathrm{OUT}}\, (V_{\mathrm{DO}})\) follows the rectifier \(V_{\mathrm{OUT}}\) (Fig. 10c), resulting in the RBC circuit mode, and the \(V_{\mathrm{OUT}}\) can be rewritten as Eq. 7. In high-voltage operation, the circuit output connects to a bootstrapping diode that can effectively block reverse current with only a tiny voltage dropout due to the \(V_{\mathrm{TH}}\) of the bootstrapping diode in Eq. (4). Therefore, this circuit can achieve a higher VCE and thus a higher PCE.

$$\begin{aligned} R_\mathrm{on}= & {} \frac{V_\mathrm{DS} }{I_D } =\frac{L}{\mu _n C_\mathrm{OX} \textit{WV}_\mathrm{OV} } \end{aligned}$$
(5)
$$\begin{aligned} V_\mathrm{OUT}= & {} V_\mathrm{AC} \times \frac{R_L }{R_\mathrm{{on,M_{1/2}}} +R_\mathrm{{on,M_{3/4}}} +R_\mathrm{{on,M_5}} +R_L } \end{aligned}$$
(6)
$$\begin{aligned} V_\mathrm{OUT}= & {} (V_\mathrm{AC} -V_\mathrm{TH} )\times \frac{R_L }{R_\mathrm{{on,M_{1/2}}} +R_\mathrm{{on,M_{3/4}}} +R_L } \end{aligned}$$
(7)

The proposed rectifier based on an MPPT with DOVD design to dynamically detect \(V_{\mathrm{OUT}}\) values to enable switching to different circuit modes, thereby achieving high PCE. Figure 11 shows the flowchart of the proposed rectifier based on MPPT technique. The output voltage \((V_{\mathrm{OUT}})\) is the function of AC input voltage \((V_{\mathrm{AC}})\). Once the \(V_{\mathrm{OUT}}\) is greater than \(V_{\mathrm{T}}\), the circuit enters the RBC mode; otherwise, it enters the FCCR mode. Then, the \(V_{\mathrm{OUT}}\) of RBC mode and FCCR mode is given by Eqs. (6) and (7), respectively. As a result, a higher VCE is achieved by reducing voltage drop, thereby achieving higher PCE.

Fig. 11
figure 11

Flowchart of the proposed rectifier based on MPPT technique

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Fig. 12
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Timing diagram of the proposed rectifier with DOVD

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The complete timing diagram of the proposed rectifier with DOVD is illustrated in Fig. 12. A conceptual diagram of the proposed DOVD is depicted in Fig. 13. The DOVD \(V_{\mathrm{OUT}} (V_{\mathrm{DO}})\) is 0 when the DOVD input voltage \((V_{\mathrm{DIN}})\) is lower than the DOVD transition voltage \((V_{\mathrm{T}})\) (line A), and the \(V_{\mathrm{DO}}\) follows the \(V_{\mathrm{DIN}}\) when the \(V_{\mathrm{DIN}}\) is higher than the \(V_{\mathrm{T}}\) (line B).

Fig. 13
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Concept of proposed dynamic output voltage detector (DOVD)

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Fig. 14
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a Proposed wide-input-voltage-range CMOS rectifier; b operating principle under positive half cycle; c operating principle under negative half cycle

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Figure 14a illustrates the proposed high-efficiency CMOS rectifier, and its operating principle of the different input voltage cycles under high-voltage operation is shown in Fig. 14b, c. In the positive half cycle of AC input voltage, the power transistor MOS \(M_{2}\) and \(M_{3 }\)are turned OFF and the power transistor MOS \(M_{1}\) and \(M_{4}\) are turned ON in the linear region to form the main path. The output voltage \((V_{\mathrm{OUT}})\) connects to a bootstrapping diode formed by PMOS \(M_{5}\) and \(M_{6}\) which can effectively block reverse current with only a tiny voltage dropout. By contrast, the power transistor MOS \(M_{1}\) and \(M_{4 }\) are turned OFF and the power transistor MOS \(M_{2}\) and \(M_{3}\) are turned ON in the linear region to form the main path during the negative half cycle of AC input voltage. The proposed DOVD is combined with the FCCR characteristic of high PCE in low-voltage operation without coupling capacitors and the RBC characteristic of effectively preventing reverse current in high-voltage operation with low-voltage dropout, thereby maintaining high voltage and PCE. When the voltage division of the \(V_{\mathrm{DIN}}\) on resistor \(\hbox {R}_{1}\) is higher than the \(V_{\mathrm{TH}}\) of PMOS transistor \(M_{7}\, (V_{\mathrm{T7}})\), PMOS transistor \(M_{7}\) is sent to the linear region, thereby enabling adjustment of the ratio of resistors \(\hbox {R}_{1}\) and \(\hbox {R}_{2}\) the determination of the \(V_{\mathrm{T}}\) in Fig.  13:

$$\begin{aligned} V_T =V_{T7} \times \frac{R_1 +R_2 }{R_1 } \end{aligned}$$
(8)

To enable PMOS transistor \(M_{7}\) to quickly enter the linear region to obtain a low-dropout \(V_{\mathrm{DO}}\), the ratio size of PMOS transistor \(M_{7}\) and resistor \(\hbox {R}_{3}\) must be controlled; a larger transistor size for \(M_{7}\) or larger resistor value for \(\hbox {R}_{3}\) enables PMOS transistor \(M_{7}\) to more quickly and easily enter the linear region.

Fig. 15
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Operation of dynamic base bias (DBB) circuit

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Fig. 16
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Layout diagram of the proposed rectifier

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The main path PMOS transistors \(M_{1}\) and \(M_{2}\) and output power PMOS transistor \(M_{5}\) contribute to a relatively large parasitic capacitance as a smoothing capacitance at node \(V_{\mathrm{X}}\), which causes the DC voltage at the node \(V_{\mathrm{X}}\) to rise. However, different DC and AC voltage at \(V_{\mathrm{AC}}\), \(V_{\mathrm{X}}\), and \(V_{\mathrm{OUT}}\) will cause floating source and drain on PMOS transistors \(M_{1}\), \(M_{2}\), and \(M_{5}\). Because of the floating source and drain, the transistor base in the case of conduction cannot receive the highest potential in the circuit, resulting in the body effect, leakage current, and latch-up effect. To mitigate these problems, the dynamic base bias (DBB) circuit [7] is connected to the base terminal of PMOS transistors \(M_{1}\), \(M_{2}\) and \(M_{5}\) to ensure that the body bias of PMOS transistors \(M_{1}\), \(M_{2}\) and \(M_{5}\) can be maintained at high potential, as shown in Fig.  15.

Fig. 17
figure 17

Simulation results of DOVD under various \(V_{\mathrm{AC}}\) values

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Fig. 18
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PCE characteristic curves for simulation of FCCR, RBC, and the proposed rectifier

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Fig. 19
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Simulation waveforms of the proposed rectifier input and output under 13.56 MHz at a 0.85 V and b 1.8 V in steady state

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Fig. 20
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Simulation results of VCE of the proposed rectifier under various amplitude \(V_{\mathrm{AC}}\) under a source frequency of 13.56 MHz

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Fig. 21
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Simulation waveforms of the proposed rectifier input and output under a 10 MHz and b 960 MHz at 1.8 V in steady state

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Fig. 22
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Simulation results of PCE of the proposed rectifier under various frequency operating points with 1-V peak amplitude \(V_{\mathrm{AC}}\)

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Compared with the FCCR, the proposed rectifier can effectively prevent reverse current to achieve a higher PCE without coupling capacitance. Compared with the RBC, PMOS transistors \(M_{1}\)–\(M_{5}\) in the proposed rectifier operate in the linear area in low-voltage operation to effectively reduce the source–drain voltage and improve the VCE and PCE. In addition, the reduced use of capacitance results in the proposed rectifier requiring less chip area than does the RBC.

4 Experimental Results

The proposed rectifier was developed through \(0.18\hbox {-}\upmu \hbox {m}\) standard CMOS process with a 1.8-V supply voltage. The layout diagram is shown in Fig. 16. The entire system, including the I/O pad, required an area of \(645 \times 790\, \upmu \hbox {m}\). In Fig. 16, region A represents bootstrapped capacitance \(C_{1}\), region B represents the main path PMOS transistors \(M_{1}\) and \(M_{2}\) with DBB circuits and NMOS transistors \(M_{3}\) and \(M_{4}\), region C represents the output power PMOS transistor \(M_{5}\) with DBB circuit, and region D represents the DOVD with PMOS transistor \(M_{6}\).

Figure 17 presents the simulation results of the DOVD under various \(V_{\mathrm{AC}}\) values. In this design, the \(V_{\mathrm{T}}\) is set at 1.1 V to serve as the circuit mode transition point to maintain the highest possible PCE under various \(V_{\mathrm{AC}}\) conditions. The \(V_{\mathrm{DO}}\) is 0 when the \(V_{\mathrm{AC}}\) is less than 1.1 V; otherwise, the \(V_{\mathrm{DO}}\) follows the \(V_{\mathrm{OUT}}\). The \(V_{\mathrm{T}}\) of this circuit can be adjusted according to the load conditions. Appropriate to set the \(V_{\mathrm{T}}\) in the cross-point of PCE of the two adopted circuit architectures (FCCR and RBC) can achieve the overall best PCE output.

PCE is often used to compare the characteristics of various rectifier structures. In this section, we compare the previously discussed FCCR and RBC simulation results with those of the proposed rectifier. Figure 18 shows the PCE characteristic curves and peak input amplitudes of three rectifiers with identical main path power MOS \((M_{1}-M_{4})\) and shunt loads of \(C_{\mathrm{L}}= 400\, \hbox {pF}\) and \(R_{\mathrm{L}}= 70\, \Omega \). Compared with the RBC, the proposed rectifier achieves a 16% PCE upgrade in the case of a 0.85-V peak \(V_{\mathrm{AC}}\); moreover, because of the use of less capacitance than does the RBC, the proposed rectifier requires a relatively small area to achieve higher performance. Because of the lack of reverse current in high-voltage operation, PCE does not degrade as it does in the FCCR structure. The proposed rectifier achieves a PCE upgrade of 47.5% from that of the FCCR in the case of a 1.8-V peak \(V_{\mathrm{AC}}\).

Figure 19a and b shows the simulation waveforms of the proposed rectifier with \(V_{\mathrm{OUT}}\) values of 0.61 and 1.3 V at 0.85 and 1.8 V \(V_{\mathrm{AC}}\), respectively, under 13.56 MHz in steady state. Figure 20 shows the simulation results of the VCE characteristic curves for the load under a source frequency of 13.56 MHz. The voltage conversion efficiencies were 52.51, 72.3, and 71.35%, and the overall power efficiencies were simulated to be 55.1, 73.03, and 73.66% at peak input source amplitudes of 0.7, 0.85, and 1.8 V, respectively. Figure 21a and b shows the simulation waveforms of the proposed rectifier with \(V_{\mathrm{OUT}}\) of 1.2 and 1.25 V at 1.8-V \(V_{\mathrm{AC}}\) and 10 and 960 MHz, respectively, in steady state. Figure 22 presents the PCE simulation results for the proposed rectifier under various frequency operating points with a 1-V peak amplitude \(V_{\mathrm{AC}}\). No significant changes in PCE were observed from 10 to 960 MHz, and the overall power efficiencies were simulated to be approximately 70%.

The proposed CMOS rectifier has the features of a wide harvesting range, wide band, and high efficiency and is based on the FCCR and RBC according to different input voltages for the appropriate switch. The proposed rectifier is designed to adjust the most suitable circuit mode through the DOVD sensing circuit to obtain the highest possible PCE at each operating point. Because of the insensitivity of the FCCR and RBC to the frequency response, the operating frequency range can include the biomedical (low frequency) and IoT (high frequency) bandwidths, thus achieving wide band operation.

Table 2 Rectifier parameter comparison
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Table 2 compares the performance of recently developed state-of-the-art rectifiers. As evident from the table, the proposed rectifier circuit can be applied to biomedical systems operating at a relatively low frequency (13.56 MHz) [16,17,18, 20, 30] and achieves high PCE performance. In addition, the proposed rectifier has been used in an IoT system at relatively high frequencies of 400–950 MHz [10, 12, 21, 28, 34]. Because of the high-frequency operation and parasitic effects engendering low PCE, the input voltage range is often affected by the efficiency of the lifting mechanism. Therefore, enhancing the performance, bandwidth, and input voltage range of the proposed rectifier in high-frequency operation is crucial problem associated with rectifier application in all systems. The proposed rectifier exhibits high PCE performance under low input voltage, wide input range, and wide band.

5 Conclusion

Energy harvesting technologies, which have grown rapidly in recent years, have been applied in various devices. However, varying degrees of RF decay occur because of various environmental factors. Therefore, many conditions of real applications for energy harvesting circuits must be considered to prevent the possibility of heavily affecting the output characteristics and subsequent operation of the entire system.

This study proposed a wide-harvesting-range, wide band, high-efficiency CMOS rectifier based on an MPPT with DOVD design to dynamically detect \(V_{\mathrm{OUT}}\) values to enable switching to different circuit modes, thereby achieving high PCE. The VCE was 52.51, 72.3, and 71.35% and the overall PCE was 55.1, 73.03, and 73.66% at peak input source amplitudes of 0.7, 0.85, and 1.8 V, respectively. Moreover, the overall PCE in the 10–960 MHz range was approximately 70% at peak input source amplitudes of 1 V. The main feature of the proposed rectifier is its ability to maintain high PCE in both low-voltage operation (approximately 0.7 V) and high-voltage operation (approximately 1.8 V) and under wide band operation (10–960 MHz), rendering it suitable for low-power IoT applications and RF energy harvesting systems.