1 Introduction

RF-energy harvesting is considered as an enabling technology for wireless sensor nodes used in applications based on the Internet of Things (IoT). It is useful where battery replacement is highly impractical either due to a large number of nodes or due to an inaccessible location of a node. Some of the examples where RF-energy harvesting is widely used are radio identification systems (RFID), bio-medical implants, structural-monitoring and home automation [1,2,3]. As the name indicates, in RF energy harvesting, the energy required for the working of a system is extracted from the propagating radio waves. The device which converts the received RF into an usable DC power is commonly known as the rectifier [4]. This rectified energy is generally stored in a capacitor or rechargeable battery by the use of a power management unit [5]. In an RF energy harvesting based system, the usage of industrial, scientific and medical (ISM) frequencies is the most convenient. However, in the ISM band, the maximum effective isotropic radiated power (EIRP) permitted by the regulatory bodies is only 36 dBm (4 W) [6] which, restricts the coverage area and therefore a high RF sensitivity is desirable in the rectifier. This RF sensitivity is defined as the minimum incident RF power that is required by the rectifier to obtain a usable DC power [7].

In the literature, various rectifier architectures have been proposed that primarily utilize the Schottky diode. This preference for selecting the Schottky diode is mainly due to its low forward voltage and very high switching speed [8, 9]. However, owing to the ease of its fabrication process, the Complementary Metal Oxide Semiconductor (CMOS) technology is currently most widely used for on-chip implementation [10].

One of the commonly known limitations in CMOS-based implementations is the threshold voltage (V\(_{th}\)) of the Metal Oxide Field Effect Transistor (MOSFET) which, is the minimum gate-to-source voltage required by a transistor for the conduction [11]. Practically, an RF harvester is implemented through a multi-stage rectifier which is commonly known as a Voltage Multiplier (VM). In practice, the increased number of stages in VM architecture results in a decrease in RF sensitivity, which is mainly controlled by the threshold voltage of the switching transistors [12].

To overcome this issue, various threshold cancellation schemes have been proposed in the literature that are either technology-based [13] or circuit-based solutions [14].

The differential drive rectifier [15, 16] is a widely used rectifier architecture due to its ability to achieve the active threshold voltage cancellation of the switching transistors and, hence, results in higher power conversion efficiency. Various architectures, that are based on the differential rectifier, have been proposed in the literature [17, 18].

The proposed architecture is a two-stage voltage multiplier circuit, based on the differential drive rectifier and also is an extension of the works published in [19, 20]. These extensions are in terms of additional results and circuit topology. The issue of threshold voltage in the voltage multiplier circuit [16] has been addressed by deriving a DC voltage from the input RF signal and using it as the DC biasing voltage for switching transistors. As a result, it exhibits higher RF sensitivity and power conversion efficiency when compared with a two-stage conventional voltage multiplier circuit.

The paper is organized as follows. Section 2 provides an overview of the conventional differential drive rectifier and introduces the proposed solution with the implementation details. The measured performances of the conventional and proposed voltage multipliers are discussed in Sect. 4 and conclusions are drawn in Section V.

2 Voltage multiplier circuits

2.1 Conventional voltage multiplier

Fig. 1
figure 1

Conventional differential drive rectifier based two-stage voltage multiplier circuit

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The conventional voltage multiplier circuit, formed by cascading two differential-drive rectifiers, is shown in Fig. 1. In the circuit, N and P are the N-type MOSFET (NMOSFET) and P-type MOSFET (PMOSFET) based switching transistors, C\(_P\) is the fly-capacitor, C\(_L\) and R\(_L\) represent the load capacitor and resistor respectively.

It has been mentioned in [16] that due to the development of a common mode DC voltage in the circuit, a low ON-resistance during the forward conduction mode and small leakage current during the reverse conduction mode has been attained. Due to these characteristics the architecture is widely used for RF energy harvesting. A rectifier is a highly non-linear circuit and hence, to obtain a detailed mathematical description of the circuit, a careful modeling in each region of MOSFET operation is required [21]. Therefore, in this work, to obtain a first order mathematical description of the circuit the following assumptions were made:

  1. 1.

    The peak amplitude of the applied RF signal is greater than the threshold voltage of the switching transistors.

  2. 2.

    The only source of losses in the system is the drain-source voltage drop across the switching transistors.

The differential drive rectifier is a full-wave topology that is formed by using two voltage doublers. Thus, using the aforementioned assumptions the conceptual diagram of stage-I (see Fig. 1) can be represented in terms of the voltage doubler as :

Fig. 2
figure 2

Conceptual working diagram of stage-I

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Fig. 3
figure 3

Equivalent circuits for the a charging and b Discharging phases of stage-I

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Consider that when applying a single tone continuous RF wave (see Fig. 2) in the circuit, a negative peak amplitude −V\(_p\) and a positive peak amplitude \(+\)V\(_p\) appears at nodes (A) and (B) respectively.

As a result, the voltage doubler enters in the charging phase (see Fig. 3a) and thus, applying Kirchoff’s voltage law (KVL) in the charging path, results in:

$$\begin{aligned} V_{cp}= -V_p +V_{dn} \end{aligned}$$
(1)

where \(V_{cp}\) is the voltage developed across capacitor C\(_p\) and \(V_{dn}\) is the voltage drop across NMOSFET N\(_{11}\). Since, the capacitor is assumed to be ideal, therefore the charge equivalent to the voltage \(V_{cp}\) will only be transferred to the next stage during the discharging phase. The discharging phase will start when the polarity of the input signal reverts as shown in Fig. 3b. Thus, by applying KVL in the discharging path:

$$\begin{aligned} V_{x}= 2V_p -(V_{dn}+V_{dp}) \end{aligned}$$
(2)

where \(V_x\) is the DC voltage that appears after the first stage. It can be seen in (2), that the loss (\(V_{dn}, V_{dp}\)) across the transistors is one of the causes of the reduced deliverable DC voltage V\(_x\).

When the voltage multiplier architecture is formed, the voltage \(V_x\) acts as the DC voltage source for the next stage. Thus, equivalent circuits for charging and discharging phases for the second stage can be modeled as:

Fig. 4
figure 4

caption equivalent circuits for the a Charging and b Discharging phases for stage-II

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By applying the KVL first for the charging phase and then for the discharging phase (Fig. 4) will result in:

$$\begin{aligned} V_{out}= 4V_p -2(V_{dn}+V_{dp}) \end{aligned}$$
(3)
Fig. 5
figure 5

Simulation results of conventional differential drive rectifier based two-stage voltage multiplier circuit

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To verify the first order expressions derived above of the circuit, simulations were done using the Spectre simulator in the Cadence environment using standard 0.18 \(\mu\)m CMOS technology. In these simulations, a single tone continuous wave RF signal of ISM 433 MHz frequency with peak amplitude of 500 mV was used with 5 K\(\Omega ||\)20 pF as a load. The simulation results of the conventional voltage multiplier are shown in Fig. 5 where it can be seen that the voltage signal of node a1 has been shifted by \(\approx\) 150 mV. This DC shift is basically the voltage developed across the fly capacitor C\(_p\) during the charging phase [see Fig. 3a and Eq. (1)]. After the discharging phase of the first stage, the rectified DC output voltage \(V_x\) with a value of 300 mV was obtained. As mentioned earlier (see Fig. 4a), \(V_x\) acts as a DC source for the next stage. Thus, the DC-level of the voltage signal at node-a2 is higher than the voltage signal at node-a1. Finally, after the discharging phase of the second stage, an output DC voltage level of 350 mV has been achieved across the load.

Thus, it can be concluded from the simulation results that to get an acceptable level of the output DC voltage i.e = 3V\(_{th}\) under the given load condition, a high amplitude input RF signal would be required.

However, as mentioned earlier, a limit on the maximum transmitted power level has been set by the regulatory bodies [6]; therefore the use of this solution is restricted. As a result, in the literature, various alternate solutions have been proposed such as the use of a zero V\(_{th}\) MOSFET [22], pre-charging of the gate terminal during switching [23] etc. To date, none of these methods have been tested for heavy load conditions. Therefore, the proposed work is targeted towards the development of a multistage rectifier or VM with higher driving capability at the smaller received RF amplitude.

2.2 Proposed voltage multiplier

Fig. 6
figure 6

Proposed two-stage voltage multiplier circuit

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In the proposed work (Fig. 6), two strategies have been simultaneously used for reducing the losses in the rectifier. The first is a reduction in the number of switching transistors in the rectifying chain. Therefore, the voltage doubler has been realized using a gate cross-coupled switching arrangement; which, is widely used in oscillators, clock-doublers, comparators etc., [11].

The second strategy is to shift the incoming RF signal by the DC level generated from stage-I. When this DC-shifted RF signal is fed to the gate cross-coupled switches, the switching action becomes effective. However, these improvements are only for heavy load-conditions i.e. \(R_L\le 10\,K\Omega\). To understand this phenomenon, consider the discharging path shown in Fig. 7 for one of the gate cross-coupled switches.

Fig. 7
figure 7

Discharging path of gate cross-coupled switch

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Fig. 8
figure 8

Simulation results of proposed rectifier

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Referring to the simulation results of the proposed rectifier for a 500 mV peak RF input amplitude of frequency ISM 433 MHz for a load value of 5 K\(\Omega ||\)20 pF, the DC voltage level at the node b2 is 700 mV (see Fig. 8). Thus ideally, the voltage swing at the node b2 ranges from 1.2 V to 200 mV and similarly from 200 mV to 1.2 V at the gate-terminal of the transistor during one cycle of the incoming RF signal. As a result, the transistor works in a linear region during the discharging mode and is completely switched OFF during the charging mode if load (R\(_L||C_L\)) with a low time constant, i.e. heavy load conditions (5 K\(\Omega ||\)20 pF), is used. On the contrary, if the time constant is high, i.e. light load conditions, then the operating conditions of the transistor will tend towards the cut-off region. This phenomenon occurs because of the development of effective gate-source voltage due to the incoming DC-biased RF signal and the stored output DC voltage for the switching transistor.

2.3 Device sizing

In the literature, it can be noticed that the rectifier consists of only two components which are a MOSFET and capacitor. If the architectures are based on classical Dickson topology [24], then either the PMOSFETs or NMOSFETs are used for switching and the capacitors for the pumping actions. On the contrary, if the rectifier is based on differential architecture then both PMOSFET and NMOSFET of the same aspect ratio are used to perform the switching action. Thus, it is noteworthy that for both design approaches the design variables are always two because only two components are being used.

In this work, to determine the device dimensions, a simulation based strategy was used. These simulations were done using the Spectre simulator in the Cadence environment with standard 0.18 \(\mu\)m CMOS technology for the simulation-environment listed in Table 1.

Table 1 Simulation environment to determine device dimensions
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Firstly, the transient simulations were performed by varying the size of the pumping capacitors (\(C_p\) and \(C_x\)) for different transistors widths. The simulation results for the minimum length (0.18 \(\mu\)m) transistors (PMOSFET, NMOSFET) for the width equal to 10 and 100 \(\mu\)m are shown in Fig. 9a, b. The performance of the rectifier was evaluated by using the maximum DC output voltage for the given RF signal amplitude. This is because it is an essential condition to obtain minimum acceptable DC amplitude level (\(\approx\)3\(V_{th}\)) across the load. It can be observed from Fig. 9 that any value of the capacitor which is greater than 10  pF can be selected for the given operating frequencies irrespective of transistor width. Hence, the value of the pumping capacitors was selected as 20 pF (Table 1).

Fig. 9
figure 9

Output DC voltage at a width = 10 \(\mu\)m b width = 100 \(\mu\)m

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To determine the transistor size for the second stage, the power conversion efficiency was selected as the performance metric. The simulation results are shown in Fig. 10 where it can be observed that to obtain a moderate value of PCE for the given operating frequencies (except 2.4 GHz), the width of the transistors should be selected between 100 and 150 \(\mu\)m.

Fig. 10
figure 10

Simulated power conversion efficiency at different transistor widths for C\(_p\), C\(_x\) = 20 pF

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The final device dimensions used in the proposed implementation are mentioned in Table 2.

Table 2 Device sizes used in implementation of proposed rectifier
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3 Measurement results

Fig. 11
figure 11

Microphotograph of proposed voltage multiplier circuit

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The proposed architecture was fabricated using a standard 0.18 \(\mu\)m CMOS technology. The microphotograph of the design is shown in Fig. 11. The total implementation area of the architecture is 0.137mm\(^2\). A Printed Circuit Board (PCB), with a standard FR4 substrate that is used in the measurements, was milled in the laboratory (Fig. 12).

Fig. 12
figure 12

Printed circuit board

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The length of the RF signal feed lines used in the PCBs were determined by using the Agilent ADS simulator. The packaged-IC was soldered directly onto the PCB as shown in the figure in order to minimize the parasitic effects during the measurements. The Agilent 8722ES network analyzer was used to measure the single port S-parameters by using the port extension feature. To obtain the differential input impedance value, the measured S-parameters were converted into the mixed mode S-parameters by using a Matlab program. In the next step, the Agilent ADS simulator was used to determine the discrete component values required to design the matching network for the circuit at ISM 13.56, 433, 915 MHz and 2.4 GHz frequencies.

Fig. 13
figure 13

Block diagram of measurement setup

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The block diagram of the measurement setup is shown in Fig. 13 where the single tone continuous wave RF signal was provided by the signal generator R&HSMIQ06B. This signal was split into the differential signal using a 2-way-180\(^\circ\), DC to 4200  MHz, 50 \(\Omega\) balun [25]. This differential signal was fed into the device under test (DUT) and the rectified DC output values were measured using the multimeter HP34401A.

The performance of the rectifier was characterized in terms of the power conversion efficiency (PCE) and maximum DC output voltage. The parameter power conversion efficiency [16] is defined as:

$$\begin{aligned} PCE(\%)=100\cdot \frac{Pout}{Pin}=\frac{\frac{V_{out}^{2}}{R_{L}}}{Ps(1-|S_{dd11}^2|-|S_{cd11}|^2)} \end{aligned}$$
(4)

where Pout and Pin are the output-power and input-power respectively, and \(V_{out}\) is the output DC voltage measured across the load resistor \(R_L\). The input power to the rectifier was calculated by using the mixed mode S-parameters [16]. Hence in (4), \(P_s\) is the source power, \(S_{dd11}\) is the differential-to-differential and \(S_{cd11}\) is the differential-to-common mode reflection coefficients, respectively. The measured output DC voltage and the power conversion efficiency for different resistive loads at different frequencies of the conventional two-stage voltage multiplier (CVM) and the proposed voltage multiplier (PVM) are shown in Figs.  14 and 15 respectively. A comparison of the performance of the present work with the state-of-the-art work on rectifier designing is presented in Table 3.

The following observations can be derived from the measured results:

  • Proposed rectifier offers a minimum improvement of 300 mV in the output DC voltages for heavy load conditions i.e. \(R_L \le 30\,K\Omega\).

  • Under light load condition i.e. \(R_L=100\,K\Omega\), the output DC voltages from the proposed rectifier are less than those of the conventional rectifier.

  • Power conversion efficiency under heavy load conditions is at-least 5 % higher compared with the conventional rectifier for ISM frequencies of value 13.56, 433 and 915 MHz.

  • Measured performance at ISM 2.4 GHz frequency is poor because the device dimensions used in implementation were not appropriate for this frequency (see Fig. 10).

  • The measured performance decreases with increasing operating frequency because of the increase in losses induced by the PCB tracks, bonding wires, type of package and associated discrete components.

Fig. 14
figure 14figure 14

Measured output DC voltage of a Conventional rectifier (CVM) b Proposed rectifier and (PVM) c their difference (Δ) and various ISM frequencies at different load conditions, d CVM@R L = 5 kΩ, e PVM@R L = 5 kΩ, f Δ@R L = 5 kΩ, g, CVM@R L = 10 kΩ, h PVM@R L = 10 kΩ, i Δ@R L = 10 kΩ, j CVM@R L = 30 kΩ, k PVM@R L = 30 kΩ, l Δ@R L = 30 kΩ, m CVM@R L = 100 kΩ, n PVM@R L = 100 kΩ, o Δ@R L = 100 kΩ

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Fig. 15
figure 15figure 15

Measured power conversion efficiency of a Conventional rectifier (CVM) b Proposed rectifier and their (PVM) c difference (Δ) at various ISM frequencies for different load conditions, d CVM@R L = 5 kΩ, e PVM@R L = 5 kΩ, f Δ@R L = 5 kΩ, g, CVM@R L = 10 kΩ, h PVM@R L = 10 kΩ, i Δ@R L = 10 kΩ, j CVM@R L = 30 kΩ, k PVM@R L = 30 kΩ, l Δ@R L = 30 kΩ, m CVM@R L = 100 kΩ, n PVM@R L = 100 kΩ, o Δ@R L = 100 kΩ

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Table 3 Performance comparison with state-of-the-art rectifiers
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4 Conclusion

This work proposed a strategy for improving the driving capability of the voltage multiplier circuit used in RF energy harvesting. The proposed topology has been experimentally evaluated for various ISM frequencies at different load conditions. When compared with the conventional voltage multiplier the proposed solution requires additional capacitors which inherently increases the overall area. The proposed rectifier arrangement offers a moderate power conversion efficiency for heavy load conditions that makes it suitable for various RF energy harvesting based applications.