1 Introduction

In circuit theory, three basic elements, resistor, capacitor, and inductor, define the relationship between charge, voltage, current, and flux. In 1971, Leon O. Chua postulated the existence of a fourth fundamental two-terminal circuit element called a memristor, which defines the missing relation between charge and flux [1]. Memristors are useful for a wide range of applications, which include amplifier [2], digital logic [3], memory [4], neuromorphic computing [5], neural network [6, 7], synaptic circuit [8], chaotic circuits [9], and oscillators [10].

The first physical memristor was implemented in the HP laboratory in 2008, but unfortunately, this is not commercially available [11]. Over the years, researchers have developed a large number of memristor emulators using various analog building blocks (ABBs) [12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33], some of them are using commercially available ABBs [13, 15,16,17,18,19,20,21,22,23, 30, 33]. The different ABBs used for the realizations are: operational amplifier (OA) [13, 15], operational transconductance amplifier (OTA) [17, 18, 22, 28], current feedback operational amplifier (CFOA) [16, 19, 21], differential difference current conveyor (DDCC) [12, 14], second-generation current conveyor (CCII) [20, 23], current backward transconductance amplifier (CBTA) [24], current conveyor transconductance amplifier (CCTA) [25, 29], differential voltage current conveyor transconductance amplifier (DVCCTA) [26], voltage differential current conveyor (VDCC) [32], and voltage differencing transconductance amplifier (VDTA) [27, 30, 31, 33]. The critical review reveals that the reported circuits suffer from one or more of the following weaknesses: excessive use of the active components [12, 13, 15,16,17,18,19,20,21, 23, 28, 33], excessive use of passive components [12,13,14,15,16,17,18,19,20,21, 23,24,25,26,27, 29, 31, 33], use of multiplier which needs precise adjustment with high accuracy [13,14,15, 17, 18, 20, 22,23,24, 27, 33], use of passive floating components [13,14,15,16,17,18, 20, 21, 23,24,25,26, 29] which are not suitable for IC fabrication, use of passive resistor [12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27, 29, 31, 33], and use of MOS resistor [12, 31, 32]. Moreover, the memristor circuits [13, 15,16,17,18,19,20,21, 23] have been realized using bipolar technology. Due to the use of bipolar technology, the memristor emulators are strictly temperature dependent. Moreover, the internal structures of [14, 22, 24,25,26, 29] memristor emulators suffer from the excessive number of transistors and the complexity, which results in a high-silicon area in the case of on-chip fabrication. Furthermore, topologies [19, 29] used two different types of ABBs, which is not encouraged from an IC point of view.

The authors in this paper proposed a single-OTA-based memristor emulator that overcomes all the aforementioned drawbacks. The proposed memristor emulator uses only one OTA and one capacitor. The used capacitor is grounded and hence is suitable for IC fabrication. The design is simulated using Cadence Virtuoso software with 180-nm Generic Process Design Kit (GPDK) CMOS technology parameters. To check the functionality of the proposed memristor emulator, an application as first-order high-pass filter is also included. Simulation results show that the proposed circuit agrees well with the theory. The pre-layout and post-layout results are also included.

This article is organized as follows. In Sect. 2, the design of the proposed memristor emulator is described. The performance simulation of the proposed memristor emulator is discussed in Sect. 3. In Sect. 4, the application of the proposed circuit is discussed, followed by comparison in Sect. 5. The conclusion is given in Sect. 6.

2 Proposed grounded memristor emulator circuits

A memristor is a two-terminal electrical component. It limits or controls the flow of electrical current in a circuit and also remembers or recollects the amount of charge that has previously flowed through it. Memristors are important because they retain memory without power, and are non-volatile. A memristor is a semiconductor that joins a capacitor, resistor, and inductor to make a fourth new kind of element whose resistance is called memristance that varies as a function of current and flux. Memristors, a combination of “memory resistors,” are a kind of passive circuit element that maintains a relationship between the time integrals of current and voltage across a two-terminal element. When the current flows in one direction, the resistance increases; in contrast, when the current flows in the opposite direction, the resistance decreases. However, resistance cannot go below zero. When the current is stopped, the resistance remains in the value that it had previously [1,2,3,4].

The operational transconductance amplifier (OTA) has a voltage input and a current output device. The symbol of double output OTA (DO-OTA) is shown in Fig. 1 [34], where Vin, IO+, IO−, VB are the differential input voltage, output current at positive terminal, output current at the negative terminal, and bias voltage, respectively.

Fig. 1
figure 1

Symbol of DO-OTA

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The ideal transfer characteristics of an OTA for input Vin are expressed as

$$I_{{{\text{O}} \pm }} = \pm g_{m} V_{{{\text{in}}}}$$
(1)

where \(g_{m}\), IO± and \(V_{{{\text{in}}}} = V_{{{\text{in}} + }} - V_{{{\text{in}} - }}\) are the transconductance, output current, and differential input voltage, respectively. Moreover, the \(V_{{{\text{in}} + }}\) and \(V_{{{\text{in}} - }}\) are the applied input voltages at the positive (p) and negative (n) terminals of the OTA, respectively.

The routine analysis results in the expression of \(g_{m}\) as

$$g_{m} = \frac{k}{\sqrt 2 }\left( {V_{{\text{B}}} - V_{{{\text{ss}}}} - 2V_{{{\text{th}}}} } \right)$$
(2)

where \(k = \mu_{n} C_{{{\text{ox}}}} \frac{W}{L}\) is MOS device parameter and \(\mu_{n}\), \(C_{{{\text{ox}}}}\), W, L, and Vth are mobility, oxide capacitance, width, length, and the threshold voltage of the MOS transistor, respectively.

The proposed grounded memristor emulator is shown in Fig. 2. By interchanging the switch, it can perform the operation of an incremental- and decremental-type memristor emulator. If cross-coupled connected the terminal pins of the switch, i.e., pins P, Q, and R, S are interconnected (P–S and R–Q), an incremental-type memristor emulator is obtained shown in Table 1.

Fig. 2
figure 2

Proposed memristor emulator

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Table 1 Operation of the proposed memristor in the incremental and decremental mode
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The input current (Iin), capacitor current (Ic), and bias voltage (VB) are obtained as

$$I_{{{\text{in}}}} \left( t \right) = - I_{{{\text{O}} + }} = g_{m} V_{{{\text{in}}}} \left( t \right)$$
(3)
$$I_{{\text{c}}} \left( t \right) = + I_{{{\text{O}} - }} = g_{m} V_{{{\text{in}}}} \left( t \right)$$
(4)
$$V_{{\text{B}}} = \frac{1}{C}\int {I_{{\text{c}}} \left( t \right){\text{d}}t} = \frac{{g_{m} }}{C}\int {V_{{{\text{in}}}} \left( t \right){\text{d}}t} = \frac{{g_{m} \phi_{{{\text{in}}}} }}{C}$$
(5)

where \(\phi_{{{\text{in}}}} = \int {V_{{{\text{in}}}} \left( t \right){\text{d}}t}\) is the total flux obtained by the memristor. Putting the value of VB into (2), we get

$$g_{m} = \frac{k}{\sqrt 2 }\left( {\frac{{g_{m} \phi_{{{\text{in}}}} }}{C} - V_{{{\text{ss}}}} - 2V_{{{\text{th}}}} } \right)$$
(6)

Substituting (6) into (3), we get the input current expression as

$$I_{{{\text{in}}}} \left( t \right) = \frac{k}{\sqrt 2 }\left( {\frac{{g_{m} \phi_{{{\text{in}}}} }}{C} - V_{{{\text{ss}}}} - 2V_{{{\text{th}}}} } \right)V_{{{\text{in}}}} \left( t \right).$$
(7)

Hence, the memconductance \(W\left( {\phi_{{\text{m}}} } \right)\) of the proposed incremental memristor is obtained as

$$W\left( {\phi_{{\text{m}}} } \right) = \frac{{I_{{{\text{in}}}} \left( t \right)}}{{V_{{{\text{in}}}} \left( t \right)}} = - \frac{k}{\sqrt 2 }\left( {V_{{{\text{ss}}}} + 2V_{{{\text{th}}}} } \right) + \frac{k}{\sqrt 2 }\left( {\frac{{g_{m} \phi_{{{\text{in}}}} }}{C}} \right).$$
(8)

Similarly, if we change the switch connections, i.e., pins P–Q and R–S changing the polarity of time-variant part of memconductance of (8), a decremental-type memristor emulator is obtained as

$$W\left( {\phi_{{\text{m}}} } \right) = \frac{{I_{{{\text{in}}}} \left( t \right)}}{{V_{{{\text{in}}}} \left( t \right)}} = \frac{k}{\sqrt 2 }\left( {V_{{{\text{ss}}}} + 2V_{{{\text{th}}}} } \right) + \frac{k}{\sqrt 2 }\left( {\frac{{g_{m} \phi_{{{\text{in}}}} }}{C}} \right)$$
(9)

where gm is controllable by bias voltage VB, which makes the proposed emulator electronically tunable.

Equations (8) and (9) show that the proposed circuit works as incremental and decremental memristor emulators, respectively, where \(\frac{k}{\sqrt 2 }\left( {V_{{{\text{ss}}}} + 2V_{{{\text{th}}}} } \right)\) is the constant term and \(\frac{k}{\sqrt 2 }\left( {\frac{{g_{m} \phi_{{{\text{in}}}} }}{C}} \right)\) being the time-varying term as \(\phi_{{{\text{in}}}}\) is the function of time-varying input signals. For \(\phi_{{{\text{in}}}} = 0\), memconductance provides a constant value in both types of incremental and decremental emulators.

3 Simulation results

In this section, the proposed grounded memristor emulator of Fig. 2 using the CMOS structure of the DO-OTA [34] shown in Fig. 3 has been simulated. The aspect ratios of the transistors for Fig. 3 are given in Table 2. All transistors are in the saturation region. The supply voltages \(V_{{{\text{DD}}}} = - V_{{{\text{SS}}}} = 1.2\;{\text{V}}\) and bias voltage VB = 0.45 V are used for simulations, where VDD, VSS, and VB are positive supply voltage, negative supply voltage, and bias voltage, respectively. The DC transfer characteristics of Fig. 3 are shown in Fig. 4.

Fig. 3
figure 3

CMOS implementation of DO-OTA

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Table 2 OTA dimension used in the simulation
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Fig. 4
figure 4

DC transfer characteristics of Fig. 3

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Figure 5 shows the transient response of the grounded memristor emulator of Fig. 2. For transient analysis, a sinusoidal voltage signal of amplitude 1 V and frequency 1 MHz has been applied to the input terminal of the proposed emulator. Figure 6 shows the ac response in 20 dB of Fig. 2 with 0.5 V ac magnitude of the input DC voltage and VB = 0.45 V is applied.

Fig. 5
figure 5

Transient response of proposed memristor emulator using a 1 V sinusoidal input signal with a 1 MHz frequency

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Fig. 6
figure 6

Frequency response of proposed memristor emulator

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Figure 7 is obtained when unit pulse voltage is applied for both incremental and decremental memristor emulators. The applied unit pulse voltage source value is taken as V1 = 0 V and V2 = 1 V. For a decremental graph, we select positive nodes of applied input unit pulse voltage and for an incremental graph, we select negative nodes of applied input unit pulse voltage. From Fig. 7, it can be observed that the current vs. time plot is increasing and decreasing with respect to the time interval for incremental and decremental topologies, respectively.

Fig. 7
figure 7

The various plot between current vs. time for unit pulse voltage for grounded memristor emulator at: a incremental topology with C = 100 nF, time period (tp) = 6 µs, pulse width (td) = 2 µs, b decremental topology with C = 100 nF, time period (tp) = 6 µs, pulse width (td) = 2 µs, c incremental topology with C = 20 nF, time period (tp) = 6 µs, pulse width (td) = 2 µs, d decremental topology with C = 20 nF, time period (tp) = 6 µs, pulse width (td) = 2 µs, e incremental topology with C = 5 nF, time period (tp) = 4 µs, pulse width (td) = 1.5 µs, f decremental topology with C = 5 nF, time period (tp) = 4 µs, pulse width (td) = 1.5 µs

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The relation between the voltage–current of the proposed grounded memristor emulator is shown in Fig. 8. The input sinusoidal voltage is applied with 1 V amplitude and different frequencies such as 200 kHz, 300 kHz, 400 kHz, 500 kHz, and 1 MHz. The hysteresis loop is shown in Fig. 8a, b by the varying capacitor at a fixed value of frequency 400 kHz, the amplitude of input signal = 1 V. It is noted that by increasing of capacitor value the current through the memristor will be decreased. From Eq. (9), it is observed that current through the memristor is inversely proportional to the capacitance and its effect is observed on the V–I curve as expected. The hysteresis loop is shown in Fig. 8c by varying the frequency at a fixed value of capacitor is 250 pF and input sinusoidal voltage is applied with 1 V amplitude and different frequencies. The simulated results clearly show that the voltage–current relationship is very sensitive to the applied frequency of the input sinusoidal signal. Figure 8d shows the effect on hysteresis loop with temperature varying [− 40°, − 32°, 56°, 80°] at fixed value of frequency 1 MHz, capacitor value of C1 = 50 pF and amplitude of input signal = 1 V. The simulated results clearly show that the voltage–current relationship is very sensitive to the applied frequency of the input sinusoidal signal.

Fig. 8
figure 8

Voltage–current plot characteristic for decremental memristor emulator of: a fixed ƒ = 400 kHz, and different value of capacitor, b fixed ƒ = 1 MHz, and different value of capacitor, c fixed C = 250 pF, and different frequency, d fixed C = 50 pF, fixed ƒ = 1 MHz, and different value of temperature

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The important aspect when design moves toward the IC implementation is the process variation. The proposed grounded memristor is examined for the different processes like SS (slow N and slow P transistors), FS (fast N and slow P transistors), FF (fast N and fast P transistors), SF (slow N and fast P transistors), and NN (nominal N and nominal P transistors). Figure 9 shows the process variation at C = 300 pF and ƒ = 250 kHz with 1 V amplitude. It reveals that the current flow in the case of FF is greater than other processes.

Fig. 9
figure 9

Process variation effect of the proposed memristor emulator for different process

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The layout of the proposed memristor emulator is given in Fig. 10. The layout occupies (76.94 µm)·(33.75 µm) area excluding the capacitor. The average power consumption in the NN (normal n and normal p transistor) process of the proposed emulator is found to be 411.2 µW. The applied input signal is sinusoidal with an amplitude of 1 V, at a 1 MHz frequency. The capacitor value is chosen for 250 pF. The pre-layout and post-layout simulation results of the proposed memristor are shown in Fig. 11. The post-simulation is done after extracting the parasitic capacitance and resistance.

Fig. 10
figure 10

The layout of the proposed memristor emulator circuit in Fig. 2

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Fig. 11
figure 11

Post-layout simulation results of the proposed memristor emulator

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4 Applications of proposed memristor emulator

In this section, two application examples are included to verify the functionality of the proposed memristor emulator: first, as a single and parallel configuration, and second as a first-order high-pass filter (HPF).

4.1 Different combinations of memristor emulator

To check the performance of the proposed OTA-based memristor emulator, it is connected in a parallel configuration and compares the obtained result with a single memristor. In a parallel configuration, the memristor value is half by the single memristor, then we said, the proposed circuit is working correctly. The single and parallel combination of the memristor is shown in Fig. 12. To check, through simulation applied a sinusoidal signal with an amplitude of 1 V with 250 kHz frequency. It can see that the proposed memristor emulator works properly as shown in Fig. 13. According to that parallel memristor emulator, the value of the memristor is halved by the single memristor.

Fig. 12
figure 12

Memristor combination in: a single, b parallel

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Fig. 13
figure 13

V–I characteristics for an amplitude of input signal, Am = 1 V, C = 300 pF at 300 kHz for single and parallel combinations of the proposed emulator

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4.2 First-order high-pass filter

In this section, the first-order passive high-pass filter (HPF) is compared with memristor emulator-based first-order HPF. Figure 14 shows the resistor–capacitor (RC) and proposed memristor–capacitor (MC)-based first-order high-pass filter (HPF), respectively. The values chosen for simulation are C = 10 pF, R = 13 MΩ for the cut of the frequency of 1.224 kHz. The frequency response of both the RC and MC-based filters is shown in Fig. 15. This shows that the proposed emulator works very well.

Fig. 14
figure 14

Circuits diagram of high-pass filter: a RC based, b MC based

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Fig. 15
figure 15

Cadence result showing the frequency response for a RC-based HPF, b MC-based HPF

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5 Comparison of proposed memristor emulator with other available in the literature

The detailed comparative analysis of the proposed circuit with existing memristor emulators available in the literature is given in Table 3.

Table 3 Comparison of the proposed memristor emulator with available literature
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It is concluded from Table 3 that

  1. 1.

    The topologies [12,13,14,15,16,17,18,19,20,21,22,23,24, 27,28,29, 33] use two or more analog building blocks, whereas the proposed emulator uses only one OTA.

  2. 2.

    The topologies [13,14,15, 17, 18, 20, 22,23,24, 27, 33] use the analog multiplier to obtain the nonlinear characteristics of the memristor emulator, and hence, circuits become complex and required precise adjustment with high accuracy. However, the proposed topology is designed without using multipliers.

  3. 3.

    The topologies [13,14,15,16,17,18, 20, 21, 23,24,25,26, 29] use passive floating components, whereas the proposed emulator topology uses only grounded components that are suitable for the IC fabrication point of view.

  4. 4.

    The reported memristor emulators in [12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27, 29, 32, 33] use resistors in the design, while the proposed topology is resistorless.

  5. 5.

    The maximum operating frequency achieved by the topologies [12, 13, 15,16,17,18,19,20,21,22,23,24, 30, 33] is in the range of kHz, while the proposed design can operate up to 1 MHz.

  6. 6.

    The topologies [13, 15,16,17,18,19,20,21, 23] have been realized using bipolar technology which is strictly temperature dependent, whereas the proposed emulator is MOS based.

  7. 7.

    The topologies [19, 29] use two different types of ABBs, which is not encouraged from an IC point of view, whereas the proposed emulator uses only a single ABB.

  8. 8.

    The topology [32] required more number of MOS transistors to implement ABB as compared to the proposed design that uses less transistors.

Therefore, based on the above discussion, it is concluded that the performance of the proposed memristor emulator is better than most of the designs available in the literature.

6 Conclusion

In this paper, we have proposed a new memristor emulator circuit using only one OTA as an active element and one grounded capacitor. The simple switching connection can be used to realize both the decremental and incremental types of memristor emulators. The proposed memristor emulator is simple and suitable for integrated circuit implementation. It provides the following advantageous features: (1) only one active component: OTA, (2) only one passive component: capacitor, (3) capacitor is grounded, which is suitable for monolithic integration, and (4) low power consumption. The pre-layout and post-layout simulation results of the proposed circuit are also included. All the theoretical concepts are verified using Cadence Virtuoso Analog Design Environment software with 180-nm generic process design kit (GPDK) technology parameters.