A VDTA-based robust electronically tunable memristor emulator circuit

Abstract

In this paper, a fully-integrated tunable grounded memristor emulator circuit based on voltage differencing transconductance amplifier (VDTA) has been proposed. The proposed memristor emulator circuit utilizes two VDTA active building blocks, two grounded resistors, a grounded capacitor and a four-quadrant analog multiplier. The working concept along with the detailed derivation of the mathematical model of the circuit has been discussed numerically and analytically to validate the operation of the proposed emulator. The operations of the proposed emulator circuit, as governed by the established model, have been verified by performing simulations in Cadence Virtuoso at 45 nm technology node. Robustness analyses performed, reveal significant process-variation tolerance at deep sub-micron technology node.

1 Introduction

The memristor, often attributed as the “Missing Element” was postulated by Chua [1]. This fourth circuital element serves to provide the missing link between flux and charge. The developed mathematical model of the memristor, depicted the memritor’s unique property of retaining the value of its resistance. Further, the memristor was first fabricated in 2008 by using TiO₂, by Hewlett-Packard (HP) laboratory [2]. The capability of the device to provide nonvolatile memory functionalities has attracted the attention of the scientific community for its potential in diverse fields of application. The discovery of the device has significantly impacted the advancement in neuromorphic circuits and their applications by featuring promising results in providing implementable compact synapses in neural networks. Extensive amount of research in this field has brought forth new resistive RAMs [3] and adaptive transistors [4, 5] which portray promising results in developing neuromorphic systems that can imitate the brain.

The TiO₂-based memristor, as described by Strukov et al. [2] is uniquely characterized by a frequency-dependent pinched hysteresis loop in its I–V plot for sinusoidal excitations. The resistance of this two-terminal device depends on the voltage across its terminals or the amount of charge that has flowed through it. The operation of the memristor can be expressed mathematically by two nonlinear functions M(q) and W(φ), which are referred as memristance and memductance respectively, [6] i.e.,

$$\frac{\delta \varphi }{\delta q} = M\left( q \right),\quad \frac{\delta q}{\delta \varphi } = W\left( \varphi \right),$$

(1)

where q is charge and φ is the flux.

From (1) we obtain a constitutive relationship between the memristor terminal voltage (v) and current (i), i.e.,

$$v = M\left( q \right) \cdot i,\quad i = W\left( \varphi \right) \cdot v$$

(2)

The relationships derived from (1) and (2) suggest that when φ–q curve is nonlinear, the resistance of the memristor will change with the variation in operating point q = q_o at time t. The operating point (q_o) does not change without applying any external voltage or current, thus the resistance of the memristor or the memristance (M) remains constant and consequently the signal is memorized.

The characteristic pinched hysteresis dependence between voltage and current are depicted for sinusoidal periodic excitations at relatively low frequencies. However, with increase in the frequency of excitation, the area of lobes of the hysteresis curve decrease and the whole curve gradually approaches the shape of a straight line. Thereby, at higher frequencies of operation, the memristor behaves like a linear resistor. Such unique features owe to its nonlinear properties which impart immense potential in high performance and high-density memory technology.

Despite its potential for widespread utilization, the TiO₂-based memristor is still not commercially available as a result of technological difficulties and cost in fabrication of nanoscale devices. Recently, significant research work has been observed in the area of memristor emulator circuits which can mimic the unique properties of the TiO₂ memristor and are also physically realizable [7,8,9,10,11,12,13,14,15,16,17,18]. Authors in these papers have proposed new memristor emulator circuits by using active building blocks (ABBs) and a number of passive elements. However, these emulators are lacking in certain novel features like, electronically tunable characteristics, occurrence of pinching of the hysteresis loop at relatively low-frequencies, range of operation and low power consumption, etc.

This paper presents a memristor emulator using CMOS-based voltage differencing transconductance amplifier (VDTA) as an active building block, which imparts characteristics like electronic tunability, improved range of frequency of operation, lower power consumption. Integration of the design with other VLSI circuits, while maintaining a simple structure and compatibility of the memristor characteristics with CMOS technology are the key features of the proposed circuit. Table 1 summarizes a comparative study between the proposed emulator circuit and pre-existing memristor emulator designs. The proposed memristor emulator utilizes two VDTA active elements, three grounded passive elements (i.e., two grounded resistors, a grounded capacitor) and an active analog voltage multiplier. The remainder of the paper is arranged as follows. Section 2 describes the operation of the VDTA and illustrates the CMOS implementation of it; followed by Sect. 3, which features the proposed emulator circuit along with the detailed mathematical explanation of its operation. Section 4 presents the results of various analyses performed and provides a brief explanation of the characteristics obtained. Section 5 concludes the paper by summarizing the various observations obtained.

Table 1 Comparative literary survey between the proposed memristor emulator and pre-existing memristor emulator designs

2 Circuit description of VDTA

The VDTA is a versatile active building block [19] that is primarily used for analog signal processing applications/circuit designing such as filter [20], oscillator [21] etc. This state-of-the-art analog building block is a transconductance amplifier with multiple outputs and has the capability of electronically tunable transconductances. The advantages of utilizing VDTA as an active device are as follows: (a) VDTA does not require the use of external resistors and are substituted by internal transconductances, (b) it exhibits two different values of transconductances, which are electronically controllable by external bias currents, (c) It has the capability of operation in voltage mode, current mode as well as transconductance mode as compared to other active devices reported (d) All the ports of VDTA exhibit high impedance, (e) VDTA-based filters allow independent controllability of resonant frequency and quality factor as compared to other active devices (f) VDTA-based designs also possess low active and passive component sensitivities. Further, no component matching conditions are also required for VDTA-based designs. Moreover, VDTA-based designs provide electronically tunable active synthesis.

The equivalent representation of the VDTA with transconductance amplifiers is shown in Fig. 1. This active building block has six- terminals (as in Fig. 1) which are labelled as p, n, z, zc, x⁺, and x⁻. It also has the flexibility of both voltage and current modes [19] of operation. The VDTA is composed of two cascaded transconductance amplifiers (T-I and T-II). The differential-input differential-output transconductance amplifier of the first stage (T-I) has two high impedance inputs terminals ‘p’ and ‘n’; the terminal ‘z’ generates an output current (i_z) which is proportional to the difference in the voltages at two input terminals ‘p’ and ‘n’ (i.e., v_p − v_n). The voltage drop at the ‘z’ (v_z) terminal produces output current at the terminals ‘x⁺’ and ‘x⁻’ of the second transconductance stage (T-II). The currents at the terminals ‘x⁺’ and ‘x⁻’, are equal and opposite in directions. The ‘zc’ terminal is used for producing multiple copies of i_z. Figure 2 illustrates the CMOS realization of the VDTA [22]. The mathematical equations that govern the relationship between the terminals are given as follows,

$$\left[ {\begin{array}{*{20}c} {i_{p} } \\ {i_{n} } \\ {i_{z} } \\ {i_{x} } \\ \end{array} } \right] = \left[ {\begin{array}{*{20}c} 0 & 0 & 0 \\ 0 & 0 & 0 \\ {g_{mf} } & { - g_{mf} } & 0 \\ 0 & 0 & {g_{ms} } \\ \end{array} } \right]\left[ {\begin{array}{*{20}c} {v_{p} } \\ {v_{n} } \\ {v_{z} } \\ \end{array} } \right],$$

(3)

where g_mf and g_ms are the first and second transconductances of the VDTA respectively and are termed as Arbel-Goldminz transconductances.

Fig. 1

Internal block diagram of the VDTA

Fig. 2

Transistor-level representation of VDTA

The transconductances can be adjusted electronically by the external DC bias current i_B and are approximated as,

$$g_{mf} = \frac{{g_{mp1} g_{mp2} }}{{g_{mp1} + g_{mp2} }} + \frac{{g_{mn1} g_{mn2} }}{{g_{mn1} + g_{mn2} }},$$

(4)

and

$$g_{ms} = \frac{{g_{mp3} g_{mp4} }}{{g_{mp3} + g_{mp4} }} + \frac{{g_{mn3} g_{mn4} }}{{g_{mn3} + g_{mn4} }},$$

(5)

where g_mni and g_mpi are the transconductances of the ith NMOS and PMOS transistors respectively and is equal to,

$$g_{mni} = \sqrt {i_{B} \mu_{N} C_{ox} \left( {\frac{{W_{mni} }}{{L_{mni} }}} \right)} ,$$

(6)

and

$$g_{mpi} = \sqrt {i_{B} \mu_{P} C_{ox} \left( {\frac{{W_{mpi} }}{{L_{mpi} }}} \right)} ,$$

(7)

where i_B denotes the bias current; μ_N,P is the mobility of the carrier for transistors (N = NMOS, P = PMOS), C_ox is the gate-oxide capacitance per unit area and (W/L) is the aspect ratio for the MOS transistors. The value of i varies from 1, 2…, 4.

3 The proposed memristor emulator circuit

The proposed emulator circuit emulates the change in the resistance of the memristor with the change in the applied input signal. This circuit consists of a two VDTAs, two grounded resistors, one grounded capacitor, a four-quadrant analog multiplier. The block-level representation and transistor-level representation of the proposed emulator circuit are shown in Figs. 3 and 4 respectively. The proposed emulator is simple, fully integrated and utilizes only on-chip elements. Nevertheless, most of the reported emulator designs use an off-chip multiplier circuit which increases the cost, power, area and the structural complexity for the integration of the entire circuit. The proposed design uses a MOS-based four quadrant analog multiplier circuit which is based on Gilbert cell architecture [23].

Fig. 3

Block level representation of proposed memristor emulator

Fig. 4

Transistor level representation of proposed memristor emulator

The multiplier circuit based on Gilbert cell architecture is composed of three NMOS differential pairs, two NMOS active loads and one active biasing resistor. The CMOS circuit diagram of the four-quadrant analog multiplier is illustrated in Fig. 5. Transistor M₁, M₂ acts as active biasing resistor and draws current i_B from V_DD. Transistors M₃, M₄ form a current mirror and behave like a tail current source. Transistors M₅, M₆, M₇, M₈, M₉ and M₁₀ form the three differential pairs for the applied differential inputs and transistors M₁₁, M₁₂ behave as active loads.

Fig. 5

Four quadrant analog multiplier incorporated in the proposed memristor design

As depicted in the schematic (Fig. 5), the symmetrical configuration of the circuit allows for large output voltage swings. Voltage signals (‘v_x’ and ‘v_y’) to be multiplied are applied to input terminals ‘x_p’, ‘x_n’ and ‘y_p’, ‘y_n’ respectively. The inputs ‘x_n’ and ‘y_n’ are complementary to ‘x_p’, ‘y_p’, respectively. Assuming that transistors M₅–M₁₂ have identical value of β (i.e. $\beta = \mu_{N} \cdot C_{ox} \cdot {W \mathord{\left/ {\vphantom {W L}} \right. \kern-0pt} L}$), the output voltage of the multiplier can be expressed as,

$$v_{{_{OUT} }} = \sqrt 2 \cdot \beta \cdot v_{x} \cdot v_{y} = \eta \cdot v_{x} \cdot v_{y}$$

(8)

where η is a constant for a definite value of β.

The operation of the proposed emulator can be explained mathematically by using the characteristic Eqs. (3) to (5). As shown in Figs. 3 and 4, VDTA₁ consists of ‘p₁’, ‘n₁’, ‘z₁’, ‘zc₁’, ‘x⁺₁’, ‘x⁻₁’ terminals and ‘g_mf1’, ‘g_ms1’ as the two transconductances. Similarly, VDTA₂ consists of ‘p₂’, ‘n₂’, ‘z₂’, ‘zc₂’, ‘x⁺₂’, ‘x⁻₂’ terminals and ‘g_mf2’, ‘g_ms2’ as the two transconductances. For VDTA₁, the current at the ‘x⁻₁’ terminal (i_x1) is given by,

$$i_{x1} = g_{ms1} v_{z1} = g_{ms1} v_{fb} .$$

(9)

where v_fb is the feedback voltage from the analog multiplier.

For VDTA₂, Fig. 3 reveals the following at terminal ‘p₂’,

$$v_{in} = (i_{in} - i_{x1} ) \cdot R_{s} = (i_{in} - g_{ms1} \cdot v_{fb} ) \cdot R_{s} .$$

(10)

From (10), the input current (i_in) is related to the input voltage as,

$$i_{in} = \left( {\frac{{v_{in} }}{{R_{S} }} + g_{ms1} \cdot v_{fb} } \right).$$

(11)

Further analysis of VDTA₂ using (3)–(5), we obtain the voltage at ‘p₂’ terminal (v_p2, v_n2 = 0) and the current at ‘z₂’ terminal (i_z2), v_p2, and i_z2 are given respectively as,

$$v_{p2} = v_{in} ,$$

(12)

and,

$$i_{z2} = g_{mf2} \cdot (v_{p2} - v_{n2} ) = g_{mf2} \cdot v_{p2} = g_{mf2} \cdot v_{in} .$$

(13)

From (13), the voltage at the ‘z₂’ terminal (v_z2) can be obtained as,

$$v_{z2} = \frac{1}{C} \cdot \int {i_{z2} } \cdot dt = \frac{{g_{mf2} }}{C} \cdot \int {v_{in} } \cdot dt.$$

(14)

Thereby, from (3) and (14), the currents at the ‘x⁺₂’ and ‘x⁻₂’ terminals of VDTA₂ is given as,

$$i_{x2} = g_{ms2} \cdot v_{z2} = \frac{{g_{ms2} \cdot g_{mf2} }}{C} \cdot \int {v_{in} } \cdot dt.$$

(15)

Hence, from (15), the voltage at ‘x⁺₂’ terminal (v_x2+) is as follows,

$$v_{{x2^{ + } }} = i_{x2} \cdot R_{M} = \frac{{g_{ms2} \cdot g_{mf2} \cdot R_{M} }}{C} \cdot \int {v_{in} } \cdot dt.$$

(16)

The voltages drop v_x2+ and v_p2 are applied at the input of the four-quadrant analog multiplier to obtain the voltage (v_fb) at the output of the multiplier. The feedback voltage (v_fb), is obtained from (8), (12) and (16) and is given by,

$$v_{fb} = \eta \cdot v_{p2} \cdot v_{{x2^{ + } }} = \frac{{\eta \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} }}{C} \cdot v_{in} \cdot \int {v_{in} } \cdot dt.$$

(17)

Substituting (17) in (11), the characteristic equation of the voltage-controlled memristor equation is revealed as,

$$i_{in} = v_{in} \cdot \left[ {\frac{1}{{R_{S} }} + \frac{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} }}{C} \cdot \int {v_{in} } \cdot dt} \right].$$

(18)

From (18), the memductance (G_M) of the proposed emulator circuit is given as,

$$G_{M} = {\raise0.7ex\hbox{${i_{in} }$} \!\mathord{\left/ {\vphantom {{i_{in} } {v_{in} }}}\right.\kern-0pt} \!\lower0.7ex\hbox{${v_{in} }$}},$$

(19)

and,

$$G_{M} = \frac{1}{{R_{S} }} + \frac{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} }}{C} \cdot \int {v_{in} } \cdot dt.$$

(20)

For a particular case where the transconductances of both VDTA₁ and VDTA₂ are equal i.e. g_mf1 = g_mf2 = g_mf, and g_ms1 = g_ms2 = g_ms, the value of G_M from (20) is given by,

$$G_{M} = \frac{1}{{R_{S} }} + \frac{{\eta \cdot g_{ms}^{2} \cdot g_{mf} \cdot R_{M} }}{C} \cdot \int {v_{in} } \cdot dt.$$

(21)

The dependence of G_M of the proposed memristor emulator on the bias current i_B is observed from Eqs. (4)–(7). The aforementioned equations govern the change in G_M for any change in i_B. Equations (20) or (21) suggest that, i_B can be utilized to modulate the memductance, thereby imparting electronically tunable nature to the proposed emulator.

4 Analysis and results

This Section presents the results obtained from our investigations.

4.1 Frequency behavior analysis

As established in the previous section, in Eq. (21), the proposed memristor emulator circuit depicts a tunable memductance whose value largely depends on the input voltage, ‘v_in’. From Faraday’s Law, we know that $\phi (t) = \int {v(\tau ) \cdot d\tau }$. Therefore, Eq. (20) can be interpreted as,

$$i_{in} (t) = v_{in} (t) \cdot \left[ {\frac{1}{{R_{S} }} + \frac{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} }}{C} \cdot \int_{{t_{o} }}^{t} {v_{in} (\tau )} \cdot d\tau } \right].$$

(22)

Further, from Faraday’s law, we obtain,

$$\phi_{in} (t) = \int_{{t_{0} }}^{t} {v_{in} (\tau ) \cdot d\tau } ,$$

(23)

and,

$$i_{in} (t) = v_{in} (t) \cdot \left[ {\frac{1}{{R_{S} }} + \frac{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} }}{C} \cdot \phi_{in} (t)} \right].$$

(24)

Thus, from (24), the memductance of the proposed flux-controlled memristor circuit can be presented as,

$$W\left( {\phi_{in} (t)} \right) = \frac{1}{{R_{S} }} + \frac{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} }}{C} \cdot \phi_{in} (t).$$

(25)

where $W\left( {\phi_{in} (t)} \right)$ expresses the memductance function of the proposed memristor, which suggests that the memductance can be controlled by applying an input voltage. Further, Eq. (25) reveals that, ${\raise0.7ex\hbox{$1$} \!\mathord{\left/ {\vphantom {1 {R_{S} }}}\right.\kern-0pt} \!\lower0.7ex\hbox{${R_{S} }$}}$ is the time-invariant portion of the memductance $W\left( {\phi_{in} (t)} \right)$.

The behavioral model of the proposed memristor derived in (25) can be used to gain an understanding of the frequency behavior of the circuit. In order to proceed with the study of frequency behavior of the emulator, let us assume that the proposed circuit is subjected to periodic sinusoidal excitations resulting in,$v_{in} = A_{m} \cdot \sin (\omega t)$; where, the amplitude is ‘A_m’, and the frequency of excitation is ‘f’ (which is given as,$\omega = 2 \cdot \pi f$). Therefore, we obtain,$\phi_{in} = - \left( {{{A_{m} } \mathord{\left/ {\vphantom {{A_{m} } \omega }} \right. \kern-0pt} \omega }} \right) \cdot \cos \left( {\omega t} \right)$. Substituting the expressions corresponding to the assumed excitation in (25), we obtain,

$$W\left( {\phi_{in} (t)} \right) = \frac{1}{{R_{S} }} - \frac{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} \cdot A_{m} }}{2\pi f \cdot C} \cdot \cos \left( {\omega t} \right).$$

(26)

Equation (26) reveals that, as the frequency of excitation (‘f’ or ‘ω’) gradually increases and approaches infinity, the time-varying portion of the memductance decreases and gradually approaches zero, thereby explaining the pinching effect of the characteristic hysteresis loop of the memristor emulator at very high frequencies. At high frequencies, the hysteresis loop pinches, areas enclosed by the hysteresis lobes decrease, and approaches the shape of a straight line. This behavior may be explained by (26), where the time-varying portion of $W\left( {\phi_{in} (t)} \right)$ has a reduced overall contribution due to its inversely proportional relationship with ‘f’ (i.e.$\left( {{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} \cdot A_{m} } \mathord{\left/ {\vphantom {{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} \cdot A_{m} } {2\pi f \cdot C}}} \right. \kern-0pt} {2\pi f \cdot C}}} \right) \approx 0$, at very high frequencies of excitation). Hence, at high frequencies, $W\left( {\phi_{in} (t)} \right)$ approaches the value of the time-invariant memductance, i.e.$W\left( {\phi_{in} (t)} \right) \approx {1 \mathord{\left/ {\vphantom {1 {R_{S} }}} \right. \kern-0pt} {R_{S} }}$; this explains the pinching of the hysteresis loop to that of a straight line, suggesting the behavior of emulator as a linear time-invariant resistor. The relationship between the time-invariant and time-varying portions of $W\left( {\phi_{in} (t)} \right)$, can be obtained from (26) as follows,

$$K = \eta \frac{{g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} \cdot R_{S} \cdot A_{m} }}{\omega \cdot C} = \frac{1}{\tau \cdot f},$$

(27)

where ‘τ’, is the time constant of the emulator circuit, and ‘f’ is the frequency of excitation. Further, from (27) the time constant of the proposed emulator circuit is given as,

$$\tau = \frac{2\pi C}{{\eta \cdot g_{ms1} \cdot g_{ms2} \cdot g_{mf2} \cdot R_{M} \cdot R_{S} \cdot A_{m} }}.$$

(28)

The frequency behavior of the proposed memristor emulator are governed by (27) and (28). The frequency analysis reveals three conditions relating K [in (27)] and the pinched hysteresis loop of $W\left( {\phi_{in} (t)} \right)$. These conditions are delineated as follows:

• i. K → 0, when f → $\infty$, the behavior of the memristor emulator is dominated by the influence of the linear time-invariant portion of memductance.

• ii. K → 1, when f → ${1 \mathord{\left/ {\vphantom {1 \tau }} \right. \kern-0pt} \tau }$, the emulator achieves the maximum pinched hysteresis loop.

• iii. K$\ge$ 1, when $f \le {1 \mathord{\left/ {\vphantom {1 \tau }} \right. \kern-0pt} \tau }$, the period of the excitation (${1 \mathord{\left/ {\vphantom {1 f}} \right. \kern-0pt} f}$) is greater than the time constant ‘τ’ of the proposed emulator circuit. This results in the loss of the hysteresis loop.

To ensure the behavior of the frequency-dependent pinched hysteresis loop, it can be concluded that, the value of K must lie in the range from 0 to 1, i.e.$0 \le K \le 1$. Further, the dependence of ‘τ’ on g_m shows that the time constant can also be varied by modulating the bias current i_B, thus tuning the characteristic hysteresis loop of the emulator circuit.

4.2 Analysis of simulation results

The proposed memristor emulator is simulated in Virtuoso Analog design Environment of Cadence at CMOS 45-nm CMOS process node. The supply voltage is taken as V_DD = − V_SS = 0.9 V. The transistor dimensions for the proposed memristor emulator are provided in Table 2. While conducting simulation analyses, all the VDTAs of the emulator have been identically biased with i_B = 50 μA. Thus, we have g_mf1 = g_mf2 = g_mf, and g_ms1 = g_ms2 = g_ms and from (21), (26), (27) and (28) we obtain the following expressions,

Table 2 Transistor dimensions

$$W\left( {\phi_{in} (t)} \right) = \frac{1}{{R_{S} }} - \frac{{\eta \cdot g_{ms}^{2} \cdot g_{mf} \cdot R_{M} \cdot A_{m} }}{2\pi f \cdot C} \cdot \cos \left( {\omega t} \right),$$

(29)

$$K = \eta \frac{{g_{ms}^{2} \cdot g_{mf} \cdot R_{M} \cdot R_{S} \cdot A_{m} }}{\omega \cdot C} = \frac{1}{\tau \cdot f},$$

(30)

$$\tau = \frac{2\pi C}{{\eta \cdot g_{ms}^{2} \cdot g_{mf} \cdot R_{M} \cdot R_{S} \cdot A_{m} }}.$$

(31)

The emulator was subjected to a sinusoidal excitation of 1 kHz with an amplitude of 30 μA in order to examine the operation of the circuit. The input voltage and current, ‘v_in’, ‘i_in’ respectively, corresponding to the excitation are shown in Fig. 6. The transient responses of the proposed emulator are observed to be stable.

Fig. 6

The transient response of the proposed emulator to a sinusoidal excitation having amplitude of 30 μA and frequency of 1 kHz

Further, Fig. 7 shows the frequency dependent pinched hysteresis loop for the same excitation, suggesting the stable operation of the circuit, where $0 \le K \le 1$ is satisfied and the memductance, $W\left( {\phi_{in} (t)} \right)$ has a dominant time-varying nature. To obtain the frequency range of operation of the memristor emulator, the frequency ‘f’, was varied from 800 Hz to 10 kHz. The hysteresis loop exhibited a decrease in the lobe areas as ‘f’ increased and approached a straight line at 10 kHz. Such observations are illustrated in Fig. 8, which suggest the frequency range of operation to be from 800 Hz (f_min) to 10 kHz (f_max).

Fig. 7

Pinched hysteresis loop for the same excitation at a frequency of 1 kHz as in Fig. 5

Fig. 8

Frequency depended hysteresis loop for excitations having an amplitude of 30 μA and frequency varying from 800 Hz to 10 kHz

As emphasized in Sect. 4.1, the operation range ($0 \le K \le 1$) of the memristor emulator circuit depends on the values of the different circuit elements [as in (29) and (31)]. Therefore, changing the values of the different circuital elements of the emulator can change the frequency range of operation. Table 3 enumerates the findings of such simulations by providing the different frequency ranges of operation for different values of i_B and C, while keeping the values of the resistances R_M, R_S, (1 KΩ each) and amplitude of excitation A_m constant.

Table 3 Tunable nature of the proposed memristor emulator

Table 3 asserts the tunable nature of the proposed memristor emulator, where, by varying the i_B the operating frequency range of the circuit may be varied. Figure 9 illustrates the time varying nature of the memductance for sinusoidal excitation of, A_m = 30 μA, and f = 50 kHz. The power dissipation of the memristor emulator when subjected to such excitations, has been found to be 3.956 mW. Furthermore, the variation of memductance by varying i_bias is depicted in Fig. 10 for different frequencies of operation. Thus, the G_M and the frequency range of operation of the proposed memristor emulator can be tuned by the bias current.

Fig. 9

Transient response of the memductance offered by proposed emulator for excitation of amplitude 30 μA and frequency 50 kHz

Fig. 10

The tunable nature of memductance offered by the proposed emulator circuit at f = 800 Hz, 1 kHz, 5 kHz, 10 kHz

4.3 Experimental results of proposed memristor emulator

This section presents the observations obtained from the experimental realization of the proposed memristor emulator circuit. The proposed VDTA based memristor emulator as in Fig. 3 has been implemented on breadboard using two commercially available LM13700 ICs, an analog multiplier AD633 IC, one capacitor (C) of 100 nF, two resistors of values 500 Ω (R_s), 5 kΩ (R_M), along with a DC supply source of ± 10 V and bias current of 1.35 mA. A single LM13700 IC is composed of two current controlled transconductance amplifiers. Therefore a single VDTA building block can be easily realized by utilizing one LM13700 IC [24, 25].

The two LM13700 ICs are used as there are two VDTA elements in the proposed circuit (Fig. 3) and they are connected via the analog multiplier, which is implemented by AD633 IC. The experimental setup is shown in Fig. 11, which illustrates the characteristic hysteresis loop obtained from the realized emulator circuit. Figure 12 illustrates typical pinched hysteresis loop and Fig. 13 shows the transient input voltage and current characteristics for an input waveform of amplitude 500 mV at a frequency of 1.46 kHz.

Fig. 11

Experimental setup consisting of the circuital realization of the proposed emulator on a breadboard, depicting the characteristic pinched hysteresis loop of a memristor obtained on a CRO

Fig. 12

Pinched Hysteresis loop of experimentally realized proposed memristor emulator circuit observed on CRO

Fig. 13

Transient input voltage and current wave forms of experimentally realized proposed memristor emulator circuit observed on CRO

The voltage-current curves gradually become narrower as the operating frequency is increased. For this reason, the behavior of the proposed emulator is analyzed at 2 kHz, 3.6 kHz, 4.3 kHz and 5.5 kHz frequency regions, as depicted in Fig. 14. The governing expression (25) can objectively explain this phenomenon; with increasing operating frequency, the linear time-variant portion of (25) decreases, thus the memristor emulator approaches linear characteristics at higher frequency regions. The experimental results presented here, suggests the memrisitve characteristics of the proposed VDTA based emulator circuit with variation in operating frequency. The simulation and exhaustive theoretical analyses along with the observations made in the experimental analyses reveals the feasibility of memristive behavior of the proposed emulator circuit in a packaged integrated MOS realization.

Fig. 14

Voltage-current hysteresis relationships for operating frequency of a 2 kHz, b 3.6 kHz, c 4.3 kHz and d 5.5 kHz

4.4 Reliability of proposed memristor emulator

Memristors exhibit unique nonvolatile memory characteristics, however they are profoundly impacted by variability, especially at highly scaled technology nodes [26, 27]. This has a profound impact on their operation especially at highly scaled technology nodes. With the current trends in aggressive scaling in order to keep up with the projections of Moore’s Law, it is important for memristive systems to retain their functionality even when subjected to extreme variations in device parameters. Keeping in view the importance to mitigate the impact of device variability, a study has been conducted to analyze the robustness of the proposed VDTA-based memristor emulator design.

The robustness of the proposed emulator has been assessed by subjecting the design to process variability. Due to the continued miniaturization of the MOS devices, process variation has a significant impact on performance of the circuit. Random variations in the wafer fabrication process, which include both intra-die and inter-die factors [28]; are responsible for variability in VLSI devices. Thus, the variation of any parameter x is,

$$\sigma_{x} = \sigma_{{x,intra{ - }die}}^{2} + \sigma_{{x,inter{ - }die}}^{2} .$$

(32)

Process sensitive MOS device parameters like the doping concentration N_CH, channel length L, gate oxide thickness t_ox, channel width W, and etc. are major contributors to process variability. Further, at highly scaled deep-submicron technology nodes, oxide thickness variations (OTV), metal-gate work-function fluctuation (WKF), random dopant fluctuation (RDF), line-edge and line-width roughness (LER, LWR) are sources of intrinsic variability [29]. To model such fluctuations the device parameters like L, W, t_ox are considered to have independent Gaussian distributions with 3σ variations of ± 10% as projected by the guidelines of the International Technology Roadmap for Semiconductor Industry (ITRS) [30]. The influence of the aforementioned device parameters has a correlated impact on the threshold voltage V_t of the MOS device, hence due to the statistical interdependence of the fluctuating components the total variation in V_t can be estimated by [29],

$$\left( {\sigma V_{t,total} } \right)^{2} \approx \left( {\sigma V_{t,RDF} } \right)^{2} + \left( {\sigma V_{t,WKF} } \right)^{2} + \left( {\sigma V_{t,PV} } \right)^{2} ,$$

(33)

where $\sigma V_{t,total}$ is the total fluctuation in V_t, $\sigma V_{t,RDF}$ is the fluctuation due to RDF, $\sigma V_{t,PV}$ and $\sigma V_{t,WKF}$ are the fluctuation components due to process variation- induced fluctuation in V_t and work-function respectively.

Hence, the overall impact of process variations resulting in device parameter fluctuations can be approximated by applying Gaussian distribution with 3σ variations of ± 10% only on the device threshold voltage V_t [31].

Monte Carlo simulation of 5000 iterations was carried out by applying Gaussian distribution to V_t and the memductance (G_M) of the proposed memristor emulator was estimated. The overall impact of such variations can be estimated by Pelgrom’s Law [32] related to the current factor (β),

$$\frac{{\sigma^{2} (\beta )}}{\beta } = \frac{{\sigma^{2} (L)}}{L} + \frac{{\sigma^{2} (W)}}{W} + \frac{{\sigma^{2} (C_{ox} )}}{{C_{ox} }} + \frac{{\sigma^{2} (\mu_{n} )}}{{\mu_{n} }}.$$

(34)

At deep-submicron CMOS technologies, the carrier mobility ($\mu_{n}$) saturates above the critical electric field (E_c) and very miniscule impact on the variation of β. Further, according to Pelgrom’s Law [32], the variance in any parameter P (ΔP) can be determined as,

$$\sigma^{2} (\Delta P) = \frac{{A_{P}^{2} }}{WL} + S_{P}^{2} \cdot D_{x}^{2} ,$$

(35)

where D_x is the separation between the matched devices and the area and spacing proportionality constants for P are represented as A_P and S_P respectively. From (35), the generalized expressions for variation in G_M may be modeled as,

$$\sigma^{2} \left( {G_{M} } \right) = \sum\limits_{i} {\left( {\frac{{\partial G_{M} }}{{\partial x_{i} }}} \right)} \cdot \sigma_{{x_{i} }}^{2} ,$$

(36)

where $\sigma_{{x_{i} }}$ is standard deviation of the device parameter x for the ith device.

The yield distribution for the meductance G_M has been illustrated in Fig. 15. It is observed from Fig. 15 that there is a standard deviation (σ) of 97.079 μ℧ around the mean (μ) 1.11624 m℧, resulting in variability (σ/μ) of 0.08697. A limited spread in memductance value of the emulator circuit translates into a narrow spread in other design metrics of the memristor emulator, thereby validating the proposed design to be variation aware.

Fig. 15

Yield distribution for the memductance of the proposed emulator circuit for a Monte Carlo simulation of 5000 iterations

5 Conclusion

A novel memristor emulator circuit utilizing VDTA as active building elements is presented. The proposed emulator circuit consists of one grounded capacitor, two grounded resistors, one four quadrant analog multiplier, and two VDTAs. The circuit presented offers a simple circuit-topology, with fully integrated configuration, low power consumption, and tunable capability by which the characteristics of the emulated memristor can be varied electronically. The mathematical model for the proposed memristor emulator has been established in order to explain the characteristics and novel features of the circuit. Thorough analyses have been performed at CMOS 45 nm technology node using Virtuoso Analog Design Environment of Cadence, whose findings reported in this paper, reveal that the proposed emulator circuit is robust and variation-resilient to fluctuations in process parameters at deep-submicron technology nodes.