1 Introduction

SAR ADCs have wide application in bio-electric signal conversion due to their low power consumption. A SAR ADC consists mainly of a comparator, double capacitive DACs, and SAR control logic. A dynamic latch comparator is often used to reduce power consumption. A scaling technology and a lowering power supply benefit digital SAR control logic. Thus, much attention has been being paid to reducing the switching energy of capacitive DACs, which focuses on energy-efficient switching techniques and reduction of DAC capacitor counts [1, 2, 4, 8, 9, 11, 13, 17, 21, 22, 24, 25, 29,30,31,32, 34, 37]. Capacitor-splitting switching scheme is proposed, reducing switching energy by 37% over the conventional one [8]. The monotonic switching method reduces energy consumption by 81% [11]. Switching techniques with two reference voltages (VREF and ground) are not energy-efficient because of a large number of unit capacitors required. So, the third reference voltage VCM, half of VREF, is introduced [13, 17, 22, 29, 31]. The unit capacitor count is reduced by at least 75% using VCM and top-plate sampling. The switching energy saves over 90%. To further decrease the switching energy, multiple switching methods are used, including the minus switching energy [24], the floating capacitor [1, 4, 25, 30, 32, 34], the charge recycling method [2], and the introduction of the fourth reference voltage Vaq [9, 21, 37], which is equal to VREF/4. Nevertheless, each has its disadvantages. [1, 4, 25, 30, 32, 34] need many more switches and higher DAC logic complexity; the DAC control logic is complicated [2]; the common-mode voltage fluctuates wildly [9, 21, 37].

This paper applies Vaq to four dummy capacitors to create a four-level capacitor-splitting DAC switching technique. It achieves 102.11% less switching energy than the monotonic one for a 10-bit SAR ADC, which is better than [7, 11, 17, 26, 29, 31, 34, 36, 37]. The area of the capacitor can be reduced by 75%, which is superior to the results obtained from [11, 17, 31] and comparable to those obtained from [7, 26, 29, 34, 37]. Besides, the common-mode voltage does not change until the last two bit-cycles, which is a significant improvement over those described in [7, 11, 17, 26, 29, 31, 37]. In addition, the DAC control logic is not difficult to implement, which makes it superior to those presented in [34] and [36] and on par with those shown in [7]. Last but not least important, it is crucial to note that VCM/Vaq does not have a significant impact on the accuracy of the SAR ADC, which is superior to [7, 17, 29, 31] and is on par with [26, 37]. Thus, it is a better trade-off in terms of energy efficiency, capacitor area, common-mode voltage variation, logic complexity, and accuracy. By utilizing the proposed switching scheme and careful circuit layout, the 10-bit SAR ADC consumes just 35.1 nW power at a sampling rate of 20 KS/s and achieves an ENOB of 9.57 bits.

The rest of this paper is organized as follows. Section 2 discusses the proposed Vaq-assisted capacitor-splitting switching scheme. In Sect. 3, non-ideal effects are investigated and evaluated. These effects include capacitor mismatch, parasitic capacitance, and reference voltage mismatch. Implementation of DAC control logic can be found in Sect. 4. Section 5 contains the post-layout simulation results. The conclusion is delivered in the final section.

2 Proposed V aq-Assisted Capacitor-Splitting Switching Scheme

Capacitor-splitting structure [8, 10, 12, 19, 20, 26, 27, 33, 35] is utilized, resulting in low power consumption and high linearity. The N-bit SAR ADC with the proposed capacitor-splitting structure is shown in Fig. 1, consisting of the MSB and the LSB parts. The MSB part is equivalent to the LSB part, which is binary-weighted. The input and DAC output signals on the positive and negative sides are denoted by VINP, VINN, VDACP, and VDACN. D[9:0] are digital output. There are four reference voltages VREF, VCM, Vaq, and gnd, with gnd serving as the ground. The fact that Vaq is only used for four dummy capacitors results in a significant reduction in switching energy and capacitor area.

Fig. 1
figure 1

Proposed Vaq-assisted capacitor-splitting structure

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2.1 Operation Principle

To explain the proposed switching technique in detail, the 5-bit example is presented in Fig. 2. During the sampling phase, the input signal is sampled on the top plates of the capacitors, and the bottom plates of the MSB part and the LSB part on both sides are reset to ground and VREF, respectively. Then, the sampling switches are off. The MSB (D4) is obtained without any switching power (E1 = 0) due to the top-plate sampling. All capacitor bottom-plates which are connected to VREF on the high voltage side is switched to VCM; meanwhile, all capacitor bottom-plates which are connected to the ground on the low voltage side are switched to VCM. The comparator input variation is got by Eq. (1)

$$ \Delta V_{{{\text{DAC}}}} = \Delta V_{{{\text{DACP}}}} - \Delta V_{{{\text{DACN}}}} = - \frac{1}{2}V_{{{\text{REF}}}} $$
(1)
Fig. 2
figure 2

Proposed switching scheme of 5-bit DAC

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The voltage on the low voltage side rises while the high voltage side falls by the same amount, VREF/4. This results in a variation of −VREF/2. By the second comparison, D3 is obtained. During this bit-cycle, the consumed switching energy is calculated by

$$ E_{{2,D_{4} = 1}} = - \frac{1}{2}{\text{C}}V_{{{\text{REF}}}}^{2} $$
(2)

Because the switching energy is negative, capacitors will discharge and return energy to the power supply [15, 18, 23]. As shown in Table 1, beginning with the third bit-cycle and excluding the last two, only two capacitors that are related but located in different parts on both sides are switched. If D4 =  = ‘1’, the corresponding capacitor switching occurs between VCM and ground in different parts on the VDACP side, while the switching on the VDACN side occurs between VCM and VREF. If D4 =  = ‘0’, the switching takes place between VCM and ground on the VDACN side, while it does between VCM and VREF on the VDACP side. In this bit-cycle, the switching energy is consumed by

$$ E_{{3,{\text{D}}_{3} = 1}} = \frac{1}{8}{\text{C}}V_{{{\text{REF}}}}^{2} $$
(3)
$$ E_{{3,{\text{D}}_{3} = 0}} = \frac{1}{8}{\text{C}}V_{{{\text{REF}}}}^{2} $$
(4)
Table 1 The related capacitor switching during the third bit-cycle for 5-bit SAR ADC
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During the last but one bit-cycle, a one-side double-level switching method is implemented. Only one dummy capacitor in MSB or LSB part on one side is switched between VREF and VCM. If D4 =  = ’1’, the switching occurs on the VDACN side; otherwise, the switching takes place on the VDACP side. The switching in detail is described in Table 2. If D4 and D2 are the same, the dummy capacitor in the MSB part is switched from VCM to VREF; If not, the dummy capacitor in the LSB part is switched from VREF to VCM.

Table 2 The dummy capacitor switching during the last but one bit-cycle for 5-bit SAR ADC
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During the last bit-cycle, only one dummy capacitor performs switching on the other side which differs from that of the former bit-cycle. If D4 =  = ’1’, the switching occurs on the VDACP side, while the switching happens on the VDACN side if D4 =  = ’0’. The switching in detail is described in Table 3. If D4 and D1 are the same, the dummy capacitor in the LSB part is switched from VCM to ground; If not, the dummy capacitor in the MSB part is switched from ground to VCM.

Table 3 The dummy capacitor switching during the last bit-cycle for 5-bit SAR ADC
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2.2 Output Voltage

The output waveform of the proposed switching scheme can be seen in Fig. 3. During the first four bit-cycles, the common-mode voltage is fixed at VREF/2; but during the subsequent bit-cycles, it varies, and the maximum varied value is VREF/32. The common-mode variation is so tiny that the induced non-linearity is negligible [3, 28].

Fig. 3
figure 3

Output waveform of proposed switching scheme for 6-bit SAR ADC

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2.3 Switching Energy

The proposed switching scheme focuses on a significant reduction of the switching energy. The behavioral simulations are performed in MATLAB. For a 10-bit SAR ADC, the average switching energy is only -5.40 CVREF2. It requires 10.61 CVREF2 if the minus energy dissipated during the second and last but one bit-cycles is not taken into consideration.

The reset energy is dissipated when the final conversion state switches to the following initial state. So, the reset energy is considered when calculating the total switching energy. The behavioral simulation of the reset energy is performed in MATLAB. The reset energy of the proposed switching scheme is 63.88 CV2REF. The total switching energy of different switching techniques is plotted against the output code in Fig. 4. If the reset energy is not calculated, the proposed one requires −5.4 CVREF2 average switching energy, 102.11% less than the monotonic one, which is the most energy-efficient; otherwise, the total switching energy is 58.48 CVREF2, 72.88% less.

Fig. 4
figure 4

Switching energy against output code

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3 Non-Ideal Effects

3.1 Capacitor Mismatch

The value of the unit capacitor C is usually determined by capacitor mismatch. C obeys Gaussian distribution with a nominal value of Cu and a standard deviation of σu. Thus, each capacitor in Fig. 1 can be expressed by the sum of the nominal value and the error term. CPM, CPL, CNM, and CNL are all equally binary-weighted, and for simplicity, only CPM is described.

$$ C_{{{\text{PM}},i}} = \left\{ {\begin{array}{*{20}l} {2^{i - 1} C_{{\text{u}}} + \delta_{{{\text{PM}},i}} } & {1 \le i \le N - 4} \\ {C_{{\text{u}}} + \delta_{{{\text{PM}},0}} } & {i = 0} \\ \end{array} } \right. $$
(5)

where all error terms obey independent, identically distributed (i.i.d.) Gaussian distribution. The total capacitance can be achieved

$$ C_{{{\text{total}}}} = C_{{P,{\text{total}}}} = 2^{N - 3} C_{{\text{u}}} + \left( {\sum\limits_{i = 0}^{N - 4} {\delta_{{{\text{PM}},i}} } + \sum\limits_{i = 0}^{N - 4} {\delta_{{{\text{PL}},i}} } } \right) \approx 2^{N - 3} C_{{\text{u}}} $$
(6)

So, their mean values and variances are

$$ \begin{gathered} E\left( {\delta_{{{\text{PM}},i}} } \right) = 0 \hfill \\ E\left( {\delta_{{{\text{PM}},i}}^{2} } \right) = 2^{i - 1} \sigma_{{\text{u}}}^{2} \hfill \\ \end{gathered} $$
(7)

Due to differential and capacitor-spitting structure, the worst integral nonlinearity (INL) appears at 1/2 (‘0,111,111,111’) of full-scale range VFS for a 10-bit SAR ADC with the proposed switching method. The DAC analog output for 1/2VFS is

$$ \begin{gathered} V_{{{\text{DAC}}}} (y = 0111111111) = V_{{{\text{DACP}}}} (y) - V_{{{\text{DACN}}}} (y) \hfill \\ = \left( {V_{{{\text{INP}}}} - V_{{{\text{INN}}}} } \right) + V_{{{\text{CM}}}} \frac{{\sum\limits_{i = 0}^{N - 4} {C_{{{\text{PM}},i}} - \sum\limits_{i = 0}^{N - 4} {C_{{{\text{PL}},i}} } + \sum\limits_{i = 0}^{N - 4} {C_{{{\text{NL}},i}} } - \sum\limits_{i = 1}^{N - 4} {C_{{{\text{NM}},i}} - \frac{{C_{{{\text{NM}},0}} }}{2}} } }}{{C_{{{\text{total}}}} }} \hfill \\ \end{gathered} $$
(8)

Then, the error term is yielded by subtracting the nominal value

$$ \begin{gathered} {\text{INL}}\left( y \right) = V_{{\text{DAC,err}}} (y) \hfill \\ = \frac{{\sum\limits_{i = 0}^{N - 4} {\delta_{{{\text{PM}},i}} - \sum\limits_{i = 0}^{N - 4} {\delta_{{{\text{PL}},i}} } + \sum\limits_{i = 0}^{N - 4} {\delta_{{{\text{NL}},i}} } - \sum\limits_{i = 1}^{N - 4} {\delta_{{{\text{NM}},i}} - \frac{{\delta_{{{\text{NM}},0}} }}{2}} } }}{{2C_{{{\text{total}}}} }}\frac{{V_{{{\text{REF}}}} }}{{{\text{LSB}}}} \hfill \\ \end{gathered} $$
(9)

where \({\text{LSB}} = \frac{{2V_{{{\text{REF}}}} }}{{2^{N} }}\). And its variance is

$$ E\left[ {V_{{\text{DAC,err}}} (y)^{2} } \right] = \left( {2^{N} - 3} \right)\frac{{\sigma_{{\text{u}}}^{2} }}{{C_{{\text{u}}}^{2} }} $$
(10)

Thus, the maximum INL variation is obtained

$$ \sigma_{{\text{INL,MAX}}} = \sqrt {2^{N} - 3} \frac{{\sigma_{{\text{u}}} }}{{C_{{\text{u}}} }} $$
(11)

The differential nonlinearity (DNL) is the difference between the voltage errors at two consecutive DAC outputs

$$ {\text{DNL}}\left( y \right) \approx \Delta V_{{\text{DAC,err}}} \left( y \right) = V_{{\text{DAC,err}}} \left( y \right) - V_{{\text{DAC,err}}} \left( {y - 1} \right) $$
(12)

The worst DNL is also expected to occur at 1/2VFS (from ‘1,000,000,000’ to ‘0,111,111,111’). Its variance is

$$ E\left[ {\Delta V_{{\text{DAC,err}}} \left( y \right)^{2} } \right] = \left( {2^{N} - 3} \right)\frac{{\sigma_{{\text{u}}}^{2} }}{{C_{{\text{u}}}^{2} }} $$
(13)

As a result, the maximum DNL variation is

$$ \sigma_{{\text{DNL,MAX}}} = \sqrt {2^{N} - 3} \frac{{\sigma_{{\text{u}}} }}{{C_{{\text{u}}} }} $$
(14)

Figure 5 depicts behavioral simulation results of 500 Monte Carlo runs of the proposed switching scheme for a 10-bit SAR ADC with σu/Cu = 0.01. The maximum DNL and INL root-mean-square (RMS) values are both 0.321 LSB, which occur at 1/2VFS. Thus, the proposed capacitor-splitting switching scheme shows good linearity performance.

Fig. 5
figure 5

The standard deviation of a DNL and b INL at each output code

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3.2 Parasitic Capacitance

As seen in Fig. 6, the parasitic capacitance exists between capacitor top- or bottom-plates and substrate [5,6,7]. To calculate the energy required for switching, parasitic capacitors must be considered. To be fair with [7, 9, 23], the top-plate capacitance Cpt and the bottom-plate capacitance Cpb are assumed to be 10% Ctotal and 15% C, respectively. The switching energy is shown in Fig. 7. When parasitic capacitance is considered, the proposed switching method has switching energy of 4.56 CVREF2, which is much higher than that without parasitic capacitance.

Fig. 6
figure 6

Parasitic capacitors

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Fig. 7
figure 7

The switching energy with parasitic capacitors

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3.3 Reference Voltage Mismatch

The ADC accuracy can suffer when there is a mismatch between VREF and VCM/Vaq [9, 14, 16]. If VCM varies by ΔV, then one side adds 2−i [VREF – (VCM + ΔV)] while the other side subtracts 2−i (VCM + ΔV). Thus, owing to the differential structure, inaccuracy of VCM does not affect the SAR ADC accuracy except for the last two bit-cycles. To evaluate the reference voltage mismatch effect, MATLAB behavioral simulation is performed. Under the case of mismatch between VCM/Vaq and VREF ranging from 0 to 1%, 500 run simulation results are shown in Fig. 8. All effective number of bits (ENOB), signal-to-noise-and-distortion ratio (SNDR), and spurious-free-dynamic-range (SFDR) have a very small shift. Because the mismatch between the reference voltages is often less than 0.3% [16], its effect on the accuracy of the SAR ADC can be negligible.

Fig. 8
figure 8

a ENOB, b SNDR, and SFDR VS reference voltage mismatch

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4 DAC Control Logic

DAC control logic of the proposed switching scheme for a 10-bit SAR ADC is shown in Fig. 9, which is implemented by gate logic design. \({\text{D}}_{i}\) and \(\overline{{{\text{D}}i}}\) are the comparison results, where 1 ≤ i ≤ 9. CPM,8-i, CPL,8-i, CNM,8-i, and CNL,8-i are all equally binary-weighted. Except for the last two bit-cycles, CPM,8-i/CNL,8-i or CPL,8-i/CNM,8-i is switched in pair depending on the first and former comparison result, shown in Fig. 9(a). To describe in brief, only CPM,8-i is analyzed. When i = 2, D10-i = D8 is obtained, then the second switching is working. CPM,8–2 (28–2−1C = 32C) pair or the other one is switched. For i = 8 and 9, CPM,8–8 = CPM,8–9 = C, where the dummy capacitor C is working, seen in Fig. 9(b). \(S\;and\;\overline{S}\) are the sampling signals. During the sampling period, \(S = 1\); otherwise, \(S = 0\). \(P\;and\;\overline{{P_{i} }}\) are the sequence control signals. From i-th to the last switching, \(P_{i}\) is always 1; otherwise, \(P_{i}\) is 0. Vaq is added to four dummy capacitors, whose control logics are easier to implement than those of VREF, VCM, and ground, shown in Fig. 9(b). Thus, the control logic is not complicated. A simple and direct technique for quantitatively evaluating the complexity of the DAC control logic is to count the average switched capacitors that are controlled by the DAC control logic during each bit-cycle. A piecewise function is used to express the logic complexity LC

$$ LC{ = }\left\{ {\begin{array}{*{20}c} {0} \\ {1} \\ {2} \\ \end{array} } \right.\;\;\begin{array}{*{20}c} {m \le 2} \\ {2 < m \le {4}} \\ {m > 4} \\ \end{array} $$
(15)

where m is No. of the average switched capacitors. If m is not greater than 2, LC is 0, which means low; If m is greater than 2 but less than or equal to 4, LC is 1, which is medium; If m is greater than 4, LC is 2, which means high. The logic complexity of the proposed switching scheme and others is shown in Table 4.

Fig. 9
figure 9

DAC control logic: a all capacitor switching except the dummy one b the dummy capacitor switching

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Table 4 Comparison of different switching schemes for 10-bit SAR ADC
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The control logic of Vaq is related to P9, D9, and the former bit D1. When the switching enters the P9 phase, only one of the four dummy capacitors is switched. To express the process in detail, a truth table is shown in Table 5. If the true value is ‘1’, Vaq switching occurs on this part while other parts remain unchanged.

Table 5 Vaq switching true table during the last bit-cycle
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5 Post-Layout Simulation Results

By using the proposed switching scheme, a 10-bit SAR ADC is designed in 0.18-μm 1P6M CMOS process with a sampling frequency of 20 KS/s and a supply voltage of 0.6-V. The SAR ADC layout occupies an area of about 340 × 380 μm2, as shown in Fig. 10. To avoid linearity degradation, a partial common-centroid layout strategy is performed. The MIM capacitor is chosen, and the capacitor floor plan is shown in Table 6.

Fig. 10
figure 10

SAR ADC layout

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Table 6 The floor plan of DAC
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The DNL and INL of the proposed ADC are shown in Fig. 11. The peak DNL is − 0.49/0.52 LSB, and the peak INL is -0.41/0.48 LSB, respectively.

Fig. 11
figure 11

DNL and INL

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Figure 12 illustrates the dynamic performance. SNDR and SFDR are 59.41 and 70.56 dB, respectively. Thus, ENOB is 9.57 bits. And the total power consumption of the proposed SAR ADC is 35.1 nW. The Walden figure-of-merit (FOMW) is defined as

$$ {\text{FOM}} = \frac{P}{{f_{{\text{s}}} \times 2^{{{\text{ENOB}}}} }} $$
(16)

where fs represents the sampling rate, and P is the power consumption of the SAR ADC. Therefore, the proposed SAR ADC achieves a FOM of 2.31 fJ/conversion step, which achieves good power efficiency. Besides, the SFDR and SNDR of the proposed SAR ADC versus the input frequency are shown in Fig. 13. Both of them are approximately unchanged over the entire bandwidth.

Fig. 12
figure 12

FFT spectrum

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Fig. 13
figure 13

SFDR and SNDR versus input frequency

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6 Conclusion

In this paper, a Vaq-assisted four-level capacitor-splitting switching algorithm is proposed. It is a better trade-off among energy efficiency, capacitor area, common-mode voltage variation, logic complexity, and accuracy. The proposed switching procedure achieves lower switching energy and a smaller capacitor area. The DAC output common-mode voltage keeps nearly constant. The capacitor and reference voltage mismatches have a little effect on the SAR ADC accuracy. The DAC control logic complexity is not high. A 0.6-V 10-bit 20 KS/s SAR ADC in 0.18-μm 1P6M CMOS technology is designed, which adopts the proposed switching scheme. It has a FOM of 2.31 fJ/conversion step and occupies an active area of about 0.13 mm2. Thus, simulation results demonstrate the power efficiency of the proposed switching scheme, which is suitable for low-power, low- or medium-speed SAR ADCs.