1 Introduction

In scale down CMOS technology and increasing demand of portable electronic circuits have encouraged researchers towards development of high performance low voltage mixed mode signal processing circuits. Compatibility with digital circuits integrated on one chip forces analog circuits to operate under low supply voltages. Several novel active elements such as Voltage Differencing Buffered Amplifier (VDBA), Voltage Differencing Transconductance Amplifier (VDTA), Voltage Differencing Current conveyor (VDCC), Current Differencing Buffered Amplifier (CDBA), Current Differencing Transconductance Amplifier (CDTA), Second Generation Current Conveyor (CCII), CFOA (Current Feedback Operational Amplifier) and others have been suggested by Biolek et al. [1] for analog signal processing applications. Apart from architecture of these active elements, there are many applications like filters, oscillators, multipliers and modulators based on these active elements have also been reported in the literature [2,3,4,5,6,7,8,9,10,11,12,13,14,15]. VDIBA is one of the recent active element introduced in [16] for analog signal processing applications. The CMOS implementation of VDIBA has been presented by Herencsar et al. [17]. The most important parameter of VDIBA is transconductance of OTA stage which directly controls various design parameters [such as pole frequency (ω0), quality factor (Q)] of filters and oscillators. Therefore, VDIBA with high transconductance (Gm) is required for high frequency applications. VDIBA block has inbuilt tunability feature which provides advanced electronic control of parameters, although it does not provide characteristics like low voltage, low power and high transconductance. In this paper programmable positive feedback loop consisting of cross-coupled MOSFETs is used to generate negative transconductance (− gm) which cancels positive output conductance of PMOS load transistors and NMOS differential pair. The proposed VDIBA is based on classical differential structure using PPF technique to enhance Gm of transconductance stage. The resistive compensation technique is used in transconductance stage to enhance bandwidth of proposed VDIBA structure. The combined effect of both techniques produce high transconductance cell, which can be used in more challenging analog signal processing applications. As an application example, the voltage mode universal biquad filter is designed to demonstrate effectiveness of proposed VDIBA circuit. The proposed biquad filter offers various attractive features such as (1) independent tunable filter parameters (ω0 and Q), (2) no matching constraints for realization of different filter functions, (3) capability to compensate for PVT (Process Voltage and Temperature) variations, (4) low active and passive sensitivities. The paper is organized as follows: After an introduction section, second section describes CMOS implementation of proposed VDIBA with detailed high frequency analysis. The third section describes voltage mode biquad filters based on proposed VDIBA. The simulation results of proposed circuit and its applications are presented in section four. Section five describes conclusion of work performed.

2 Circuit Design

2.1 Proposed VDIBA Circuit

The VDIBA is basically a combination of differential transconductance stage as first stage and the unity gain inverting voltage buffer as second stage which provides voltage output. The circuit symbol and CMOS implementation of existing circuit [17] are shown in Fig. 1a and b respectively.

Fig. 1
figure 1

Voltage differencing inverted buffered amplifier: a symbol, b existing VDIBA

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Using standard notations, characteristics of VDIBA (including non idealities) can be described in following hybrid matrix:

$$\left[ \begin{aligned} Ip \hfill \\ In \hfill \\ Iz + \hfill \\ Vw - \hfill \\ \end{aligned} \right] = \left[ {\begin{array}{*{20}c} 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 \\ {G_{m} \left( s \right)} & { - G_{m} \left( s \right)} & {sCz + \frac{1}{Rz}} & 0 \\ 0 & 0 & { - \beta \left( s \right)} & {Rw} \\ \end{array} } \right]\left[ \begin{aligned} Vp \hfill \\ Vn \hfill \\ Vz + \hfill \\ Iw - \hfill \\ \end{aligned} \right]$$
(1)

where Gm is transconductance of VDIBA and β (ideally unity) represents non ideal voltage gain between ports Z+ and ports W−. The VDIBA has low valued parasitic resistances Rw (ideally zero) at ports W−. It also has large valued parasitic resistances Rz (ideally infinity) in parallel with low valued parasitic capacitances Cz (ideally zero) at ports Z+. The proposed VDIBA is shown in Fig. 2. The first stage consists of transistors M1 and M2 forming input differential pair, transistors M5 and M6 act as active load transistors and transistors M3 and M4 generates negative transconductance (− gm). It uses cross coupled NMOS transistors between nodes a and b which provide local positive feedback for compensation of positive output conductance of the PMOS load transistors and NMOS differential pair. The advantage of proposed technique is that it does not limits output voltage swing, due to absence of MOSFET diode connected circuit at load side. Furthermore, the resistive compensation technique is used to enhance bandwidth of transconductance stage of proposed circuit [18,19,20]. An additional advantage of proposed transconductance stage is an inbuilt tuning current (Ic) that can be used for adjusting transconductance (Gm) of proposed VDIBA. The output stage (second stage) of proposed VDIBA is unity gain inverting buffer amplifier with PMOS load (see Fig. 2). Second stage is free from substrate bias effect because of PMOS load.

Fig. 2
figure 2

Circuit diagram of proposed VDIBA

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2.2 High Frequency Analysis of Proposed VDIBA

The small signal high frequency equivalent circuit of the novel transconductance stage (first stage) of the proposed VDIBA is shown in Fig. 3. In high frequency equivalent model gmi, r0i, Gi, Di, Si and Ci denote transconductance, output resistance, gate, drain, source terminals and gate to source capacitance of corresponding MOSFETs Mi respectively (where i = 1–10); Vn and Vp are magnitudes of input voltages applied at gate of transistors M1 and M2.

Fig. 3
figure 3

High frequency equivalent model for transconductance stage of proposed VDIBA

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By using high frequency equivalent model, the short circuit transconductance without compensation resistor R (assume gm1 = gm2, gm3 = gm4, gm5 = gm6, gm5 = gm7, gm6 = gm8, gm7 ≈ gm9, gm9 = gm10, C3 = C4, C5 = C6, C7 = C8, C9 = C10, go1 = go2, go3 = go4, go5 = go6, g07 = g08, g09 = g010) is given by

$$\frac{Iz + }{(Vp - Vn)} = \frac{{g_{m1} g_{m5} }}{{g_{m5} - g_{m3} + g_{01} + g_{03} + g_{05} + sC_{4} + sC_{5} + sC_{7} }}$$
(2)

Here go = go1 = go3 = go5. Under approximation go << gm, Eq. (2) can be simplified as

$$G_{m} (s) = \frac{Iz + }{(Vp - Vn)} = \frac{{g_{m1} g_{m5} }}{{g_{m5} - g_{m3} + sC_{4} + sC_{5} + sC_{7} }}$$
(3)

It is evident from (3), that differential transconductance gain at low frequency can be expressed as

$$G_{m} = \frac{{g_{m1} g_{m5} }}{{g_{m5} - g_{m3} }} = \frac{{g_{m1} }}{{1 - \frac{{g_{m3} }}{{g_{m5} }}}}$$
(4)

where gm3/gm5 is defined as the loop gain factor and its value depends on device sizes of circuit. If loop gain factor gm3/gm5 is less than one, amplification is enhanced by gain factor 1/(1 − gm3/g m ) which is greater than 1. Note that gm3 is fully programmable with tuning current (Ic) which can be useful for compensation of PVT. From (3) it is evident that − 3 dB frequency of transconductance stage of proposed VDIBA (assume Cgs = C4 = C5 = C7) is given by

$$\omega_{{ - 3\;{\text{dB}}}} = \frac{{g_{m5} - g_{m3} }}{{3C_{gs} }} = g_{m5} \left( {\frac{{1 - {{g_{m3} } \mathord{\left/ {\vphantom {{g_{m3} } {g_{m5} }}} \right. \kern-0pt} {g_{m5} }}}}{{3C_{gs} }}} \right)$$
(5)

It is clear from (5) that bandwidth of transconductance stage of proposed VDIBA is low. Therefore, for proposed VDIBA, resistive compensation technique of bandwidth extension is used to enhance bandwidth of transconductance stage. Compensation resistors are introduced between gates of MOSFETs M5–M7, M6–M8 and M9–M10 (see Fig. 2). The short circuit transconductance of proposed VDIBA with compensation resistor R is given by

$$G_{m} = \frac{{\frac{{g_{m1} g_{m5} }}{{C_{4} + C_{7} }}\left( {s + \frac{1}{{RC_{5} }}} \right)}}{{s^{2} + s\left[ {\frac{{C_{4} + C_{5} + C_{7} - g_{m3} RC_{5} }}{{RC_{5} (C_{4} + C_{7} )}}} \right] + \frac{{g_{m5} - g_{m3} }}{{RC_{5} (C_{7} + C_{4} )}}}}$$
(6)

Consider Cgs = C4 = C5 = C7, Eq. (6) can be written as

$$G_{m} = \frac{{\frac{{g_{m1} g_{m5} }}{{2C_{gs} }}\left( {s + \frac{1}{{RC_{gs} }}} \right)}}{{s^{2} + s\left[ {\frac{{3 - g_{m3} R}}{{2RC_{gs} }}} \right] + \frac{{g_{m5} (1 - {{g_{m3} } \mathord{\left/ {\vphantom {{g_{m3} } {g_{m5} }}} \right. \kern-0pt} {g_{m5} }})}}{{2RC_{gs}^{2} }}}}$$
(7)

However, due to connection of compensation resistor R in proposed circuit, the transfer function Gm becomes second order (see Eq. 7) with one zero and two poles. By choosing R = 1/gm5, Eq. (7) can be reduced as

$$G_{m} = \frac{{\frac{{g_{m1} g_{m5} }}{{2C_{gs} }}\left( {s + \frac{{g_{m5} }}{{C_{gs} }}} \right)}}{{\left( {s + \frac{{g_{m5} }}{{C_{gs} }}} \right)\left( {s + \frac{{g_{m5} (1 - {{g_{m3} } \mathord{\left/ {\vphantom {{g_{m3} } {g_{m5} }}} \right. \kern-0pt} {g_{m5} }})}}{{2C_{gs} }}} \right)}}$$
(8)

The zero in Eq. (8) cancels one of the poles, thereby reducing transfer function to a first order system with bandwidth given by gm5(1 − gm3/gm5)/2C gs , which is 1.5 times higher than Eq. (5). The input stage consisting of transistors M1–M10 forms the differential transconductance stage which converts differential input voltage into output current (Iz+). The output stage is formed by unity gain inverting buffer amplifier (M11–M12) with PMOS load. The frequency response of output stage (see Fig. 2) is given by [21].

$$\frac{{V_{w + } }}{{V_{z - } }} = \frac{{g_{m12} }}{{g_{m11} (1 + {{s(C_{gs11} } \mathord{\left/ {\vphantom {{s(C_{gs11} } {g_{m11} ))}}} \right. \kern-0pt} {g_{m11} ))}}}}$$
(9)

From (9) it can be seen that output stage has very high bandwidth. On the other hand bandwidth of transconductance stage (discussed above) is less as compared to output stage which in turn limits bandwidth of VDIBA. Therefore, the bandwidth of proposed VDIBA is mainly decided by bandwidth of transconductance stage only. However, overall bandwidth of proposed VDIBA circuit is increased by using resistor compensation technique.

3 Application Examples

3.1 Proposed Universal Biquad Filter

To describe effectiveness of proposed tunable high performance VDIBA circuit, a voltage mode universal biquad filter has been designed is shown in Fig. 4. The proposed filter can provide five types of standard biquad filter. The routine analysis of circuit (Fig. 4) gives following transfer functions shown in (10)–(14).

$${\text{If}}\;{\text{V}}_{1} = {\text{Vin}},\;{\text{V}}_{2} = {\text{V}}_{3} = 0,\;{\text{then LP:}}\;\frac{Vout}{Vin} = \frac{{{{G_{m1} G_{m2} } \mathord{\left/ {\vphantom {{G_{m1} G_{m2} } {C_{1} C_{2} }}} \right. \kern-0pt} {C_{1} C_{2} }}}}{D(s)}$$
(10)
$${\text{If}}\;{\text{V}}_{2} = {\text{Vin}},\;V_{1} = {\text{V}}_{3} = 0,\;{\text{then BP:}}\;\frac{Vout}{Vin} = \frac{{ - {{sG_{m2} } \mathord{\left/ {\vphantom {{sG_{m2} } {C_{2} }}} \right. \kern-0pt} {C_{2} }}}}{D(s)}$$
(11)
$${\text{If}}\;{\text{V}}_{3} = {\text{Vin}},\;{\text{V}}_{1} = {\text{V}}_{2} = 0,\;{\text{then HP:}}\;\frac{Vout}{Vin} = \frac{{ - s^{2} }}{D(s)}$$
(12)
$${\text{If}}\;{\text{V}}_{1} = - {\text{V}}_{3} = {\text{Vin}},\;V_{2} = 0,\;{\text{then BS:}}\;\frac{Vout}{Vin} = \frac{{s^{2} + G_{m1} G_{m2} /C_{1} C_{2} }}{D(s)}$$
(13)
$${\text{If}}\;{\text{V}}_{1} = {\text{V}}_{2} = - {\text{V}}_{3} = {\text{Vin}},\;{\text{then AP:}}\;\frac{Vout}{Vin} = \frac{{s^{2} - sG_{m2} /C_{2} + G_{m1} G_{m2} /C_{1} C_{2} }}{D(s)}$$
(14)

where D(s) is characteristic equation and given by

$$D(s) = s^{2} + \frac{s}{{RC_{2} }} + \frac{{G_{m1} G_{m2} }}{{C_{1} C_{2} }}$$
(15)

In Eqs. (10)–(14) Gm1 and Gm2 represents transconductance of VDIBA1 and VDIBA2 respectively. The pole frequency ω0 and quality factor Q can be computed from (15) as follows.

$$\omega_{0} = \sqrt {\frac{{G_{m1} G_{m2} }}{{C_{1} C_{2} }}} ,\quad Q = R\sqrt {\frac{{G_{m1} G_{m2} C_{2} }}{{C_{1} }}}$$
(16)
Fig. 4
figure 4

Circuit diagram of proposed voltage mode universal biquad filter

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It can be seen from (16) that Q can be tuned independently by different values resistor R.

Sensitivity analysis of proposed biquad filter with respect to active and passive components may be summarized as

$$S_{{G_{m1} }}^{{\omega_{0} }} = S_{{G_{m2} }}^{{\omega_{0} }} = \frac{1}{2},\quad S_{{C_{1} }}^{{\omega_{0} }} = S_{{C_{2} }}^{{\omega_{0} }} = - \frac{1}{2},\quad S_{{G_{m1} }}^{Q} = S_{{G_{m2} }}^{Q} = \frac{1}{2},\quad S_{{C_{1} }}^{Q} = - \frac{1}{2},\quad S_{{C_{2} }}^{Q} = \frac{1}{2},\quad S_{R}^{Q} = 1$$
(17)

It is concluded from (17) that the sensitivities of biquad filter are low and it lies within unity magnitude.

3.2 Non Ideal Analysis of Proposed Universal Biquad Filter

Now consider the effect of non ideal parameters of proposed VDIBA from Eq. (1) on biquad filter. As in a non-ideal VDIBA, parasitic capacitance Cz and parasitic resistance Rz appears between high impedance ports Z+ and ground. In proposed biquad filter circuit, parasitic impedances (Rz1||Cz1) and (Rz2||Cz2) appear in parallel with capacitor C1, C2 of VDIBA1 and VDIBA2 respectively. Routine analysis of biquad filter (Fig. 5), provides following non ideal transfer function.

$$Vout = \frac{{ - V_{3} \beta_{2} \left[ {s^{2} C_{2} C_{1}^{'} + sC_{2} Gz_{1} } \right] - V_{2} \beta_{2} G_{m2} \left[ {sC_{1}^{'} + Gz_{1} } \right] + V_{1} \beta_{1} \beta_{2} G_{m1} G_{m2} }}{{s^{2} C_{1}^{'} C_{2}^{'} + s\left[ {\frac{{C_{1}^{'} }}{R} + C_{1}^{'} Gz_{2} + C_{2}^{'} Gz_{1} } \right] + \beta_{1} \beta_{2} G_{m1} G_{m2} + Gz_{1} Gz_{2} + \frac{{Gz_{1} }}{R}}}$$
(18)
Fig. 5
figure 5

Circuit diagram of voltage mode universal biquad filter [14]

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In Eq. (18), βi, Gmi, C ’ i  = (C i  + Cz i ) and \(Gz_{i} = \frac{1}{{Rz_{i} }}\) are parameters of ith VDIBA (where i = 1, 2). The parasitic resistances (Rz) are of the order of several KΩs and thus their effect on the performance of biquad filter can be neglected. After neglecting parasitic resistances (Rz), the non ideal ω0 and Q of the proposed biquad filter can be rewritten as.

$$\omega_{0} = \sqrt {\frac{{\beta_{1} \beta_{2} G_{m1} G_{m2} }}{{C_{1}^{'} C_{2}^{'} }}} ,\quad Q = R\sqrt {\frac{{\beta_{1} \beta_{2} G_{m1} G_{m2} C_{2}^{'} }}{{C_{1}^{'} }}}$$
(19)

It is clear from characteristic Eq. (19) that the values of ω0 and Q are slightly modified due to parasitic capacitances. The parasitic capacitances Cz1 and Cz2 will be absorbed by external capacitances C1 and C2 because their values are very small as compared to external capacitors; hence do not contribute to any unnecessary pole. However, Eq. (19) shows that non ideal voltage gain β also slightly modifies pole frequency ω0 and quality factor Q of biquad filter. The parasitic resistance Rw is not considered due to its small value. Thus, proposed biquad filter circuit is almost insensitive to non ideal effects. Simulation results of biquad filter based on proposed VDIBA is discussed in the subsequent Sect. 4.

3.3 Voltage-Mode Universal Biquad Filter [14]

The voltage mode universal biquad filter reported in literature [14] has also been designed using proposed VDIBA which is shown in Fig. 5. The simulation result of biquad filter is presented in subsequent Sect. 4.

4 Simulation Results

To verify the theoretical analysis, all circuits are implemented by using TSMC 0.18 µm CMOS process technology and BSIM3 level 49 model devices with DC supply voltage equal to ± 0.6 V. The proposed VDIBA architecture is designed with optimal size to obtain small area, high transconductance, better frequency response and low power dissipation. The biasing of circuit is made in such a manner that all MOSFETs are operating in saturation region. Note that bulk of all NMOS transistors are connected to VSS and all PMOS transistors are connected to VDD. Table 1 shows aspect ratios of MOSFETs used in proposed VDIBA.

Table 1 Aspect ratios of transistors used in proposed VDIBA
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The AC response of transconductance stage for proposed VDIBA with compensation resistor R = 4 KΩ for tuning current (Ic) = 100 µA provides bandwidth extension up to 263 MHz at bias current IB = 150 µA as shown in Fig. 6. Figure 7 shows frequency response of transconductance stage for proposed VDIBA by varying Ic at fixed IB. The high transconductance (Gm) range of 1.24–10.6 mS can be achieved by varying Ic from 0 to 100 µA at IB = 150 µA (see Fig. 7a). The low transconductance range of 422 µS–1.24 mS can also be obtained from proposed VDIBA by varying Ic from 0 to 30 µA at IB = 40 µA (see Fig. 7b). It can be observed from Fig. 7a and b that range of transconductance controllability is wider in proposed VDIBA. Figure 8 shows DC response of transconductance stage for proposed VDIBA circuit. For transconductance stage, maximum range of input voltage without producing significant non-linearity at terminal Z+ is approximately ± 50 mV at Ic = 100 µA. The ac response of second stage for proposed VDIBA is shown in Fig. 9. The non ideal voltage gain (β) of inverting buffer for proposed VDIBA is 1.07 with operating frequency fβ = 3.9 GHz and transconductance Gm of proposed circuit at Ic = 100 µA is 10.6 mS with operating frequency fGm = 263 MHz. Hence, the operating frequency of proposed VDIBA circuit at Ic = 100 µA is f0max = {min (fGm, fβ)} = 263 MHz. Figure 10 shows DC response of second stage for proposed VDIBA circuit. The simulation results of proposed VDIBA at bias current IB = 150 µA is summarized in Table 2.

Fig. 6
figure 6

Transconductance plots of proposed VDIBA

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Fig. 7
figure 7

Frequency response of transconductance stage for different tuning currents (Ic) at a bias current (IB) = 150 µA and b bias current (IB) = 40 µA

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Fig. 8
figure 8

DC response of transconductance stage for proposed VDIBA

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Fig. 9
figure 9

Frequency response of second stage for proposed VDIBA

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Fig. 10
figure 10

DC response of second stage for proposed VDIBA

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Table 2 The summary of simulation results of proposed VDIBA
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Table 3 shows comparison between performance of proposed VDIBA and other VDIBA/VDBA circuits on basis of transconductance range, power dissipation, bandwidth and supply voltage. It is evident from Table 3, that proposed VDIBA operate at low supply voltage, higher transconductance, and higher bandwidth as compared to other VDIBA/VDBA circuits.

Table 3 The comparative results analysis of proposed VDIBA and other VDIBA/VDBA circuits
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4.1 Simulation Results of Proposed Voltage Mode Universal Biquad Filter

The voltage mode universal biquad filter (Fig. 4) is designed for pole frequency f0 = 10.1 MHz and Q = 1.27 by selecting Gm1 = Gm2 = 1.27 mS (Ic = 0 µA), external resistances R = 1 KΩ, and external capacitors C1 = C2 = 20 pF. The simulated magnitude responses of low pass, high pass, band pass, band reject and all pass filter as shown in Figs. 11 and 12 respectively. The tuning of Q for band pass response of proposed biquad filter (Fig. 4) as shown in Fig. 13. It is clear from curves that tuning of Q can be done by varying resistor R. The transient response of biquad filter is measured by applying a sinusoidal input voltage signal with amplitude of 25 mV at 10 MHz frequency. Figure 14 shows output signals of band pass response for biquad filter and total harmonic distortion (THD) for output signal is 0.4%. The power dissipation of proposed biquad filter is 1.14 mW. The variation of pole frequency for band pass response is obtained by varying Ic as shown in Fig. 15. The pole frequency is varied for f0 ≅  {10.5; 16.1; 23.8; 38.3; 83.4} MHz via tuning current (Ic) = {0; 25; 50; 75;100} µA respectively.

Fig. 11
figure 11

Frequency response of proposed biquad filter (LP, HP, BP, BR)

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Fig. 12
figure 12

Frequency response of all pass filter for proposed biquad filter

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Fig. 13
figure 13

Frequency response of Band pass filter with different value of resistor R

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Fig. 14
figure 14

Transient response of Band pass filter at 10 MHz frequency

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Fig. 15
figure 15

Pole frequency tuning of Band pass response

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4.2 Simulation Results of Existing Universal Biquad Filter [14]

The voltage mode universal biquad filter of Fig. 5 has also been simulated by using both existing VDIBA [17] and proposed VDIBA. The value of passive components are chosen as C1 = C2 = 20 pF and R = 1 KΩ for both cases. The value of transconductance (Gm) for existing VDIBA is 656 µA (at IB = 100 µA) which results in pole frequency of 6 MHz and power dissipation of 8.5 mW. Although, the value of transconductance (Gm) of proposed VDIBA is 4.8 mS (at IB = 150 µA and Ic = 75 µA) which results in pole frequency of 18 MHz and power dissipation of 0.74 mW.

Thus, it can be observed that pole frequency obtained by biquad filter designed with proposed VDIBA is approximately 3 times greater than pole frequency of biquad filter designed using existing VDIBA with power saving of approximately 7.76 mW. Figures 16 and 17 show responses of voltage mode biquad filter designed using proposed VDIBA and existing VDIBA respectively.

Fig. 16
figure 16

Response of biquad filter [14] designed using proposed VDIBA

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Fig. 17
figure 17

Response of biquad filter [14] designed using existing VDIBA

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5 Conclusions

This paper presents high performance tunable VDIBA based on programmable positive feedback transconductance enhancement and resistive compensation technique. It operates at lower supply voltage and provides high transconductance and consumes low power than other VDIBA/VDBA circuits. The bandwidth of proposed VDIBA is improved by using resistive compensation technique. The transconductance of proposed VDIBA circuit is enhanced up to 10.6 mS with 263 MHz bandwidth. To demonstrate the effectiveness of high performance of proposed circuit, voltage mode universal biquad filters are implemented and simulated. The pole frequency of proposed universal biquad filter is tunable in range of 10.5–83.4 MHz. Therefore, proposed VDIBA circuit may be useful in low voltage low power high performance analog signal processing applications.