Keywords

1 Introduction

The rapid improvements in VLSI designs have changed the dynamics of active elements. There is also a huge demand for active elements in applications such as oscillators and filters to consume as low power as possible. The operational amplifier has been the most prevalent and extensively used active block for a long time. New advances have also made it necessary for both analog and digital blocks to be implemented on the same IC.

Communication has witnessed a gradual evolution from analog-to-digital communication. However, practically signals are analog in nature. Speech signal, real time audio are all analog signals which should undergo digital communication. Analog signals are initially converted into digital signals using analog-to-digital (A/D) converters. The signals need to initially pass through an analog filter to achieve noise immunity. Analog filters, thus hold a high demand in the communication and signal processing domain.

Authors in [1] have presented the promising active elements and their future applications. In this paper, several active elements such as differential difference amplifier (DDA), four terminal floating nullor (FTFN), operational transconductance amplifier (OTA), voltage differencing inverting buffered amplifier (VDIBA), voltage differencing transconductance amplifier (VDTA), etc., were explained in brief. This paper proposes a new internal structure of the active element, VDIBA, along with its filter applications. Several operations of VDIBA, for-instance, inductor emulator [2], multifunctional filter [3], multiplier [4], oscillator [5], etc., are reported in literature. The intrinsic structure of VDIBA consists of a transconductance stage followed by an inverted buffered amplifier stage [6]. In this article, a VDIBA-based multifunctional filter configuration is proposed. The traditional transconductance phase present at the input of VDIBA is succeeded by an Arbel–Goldminz transconductance stage [7]. This Arbel–Goldminz transconductance stage eradicates the requirement for transistor matching and generates optimal outputs. Also, as in the Arbel–Goldminz transconductance stage, the transistors are placed symmetrically, this circuit is more immune to noise in contrast with earlier traditional transconductance stage. The output of the initial transconductance stage is supplied to an inverted buffer stage, which provides the necessary amplification to the circuit. A multifunctional filter can mimic the behavior of all different kind of filters. This article demonstrates the three filters namely high pass, low pass and band pass filter.

2 VDIBA Design

VDIBA is a four-port active element with block diagram depicted in Fig. 1. The functionality of VDIBA and its ports are mathematically represented by the subsequent matrix form [8]:

$$ \left[ {\begin{array}{*{20}c} {i_{{\text{p}}} } \\ {i_{{\text{n}}} } \\ {i_{{\text{z}}} } \\ {v_{{\text{w}}} } \\ \end{array} } \right] = \left[ {\begin{array}{*{20}c} 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 0 \\ {g_{{\text{m}}} } & { - g_{{\text{m}}} } & 0 & 0 \\ 0 & 0 & { - \,1} & 0 \\ \end{array} } \right]\left[ {\begin{array}{*{20}c} {v_{{\text{p}}} } \\ {v_{{\text{n}}} } \\ {v_{{\text{z}}} } \\ {i_{{\text{w}}} } \\ \end{array} } \right] $$
(1)
Fig. 1
A block diagram of V D I B A element. The block labeled V D I B A is connected to voltages, labeled V subscript p, V subscript n, V subscript w, and V subscript z at four terminals, labeled p, n, w, and z.

Block diagram of the VDIBA active element

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As shown in block diagram, there are four terminals, i.e., p, n, w and z. The voltages vp, vn represent the voltages at input terminals, ip, in represent the currents at input terminals. vz, iz and vw, iw represent the voltage and current at the intermediate terminal and the output terminal, respectively. The transconductance (gm) of the transconductance stage is given by

$$ g_{{\text{m}}} = \left( {\frac{{g_{{{\text{m}}1}} g_{{{\text{m}}2}} }}{{g_{{{\text{m}}1}} + g_{{{\text{m}}2}} }} + \frac{{g_{{{\text{m}}3}} g_{{{\text{m}}4}} }}{{g_{{{\text{m}}3}} + g_{{{\text{m}}4}} }}} \right) $$
(2)

The internal representation of presented VDIBA configuration is shown in Fig. 2. In the representation, the first stage is realized with Arbel–Goldminz transconductance stage. This first stage contains two NMOS (M1 and M2) and PMOS (M3 and M4) transistor pairs. This stage achieves the same functionality which is achieved in a differential amplifier. The first stage is followed by an inverted voltage buffer (IVB) stage. In the second stage, a common source (CS) amplifier with a NMOS transistor load is realized. The overall configuration is provided with suitable bias current source (Ibias) pairs, supply voltages VDD and VSS to bias the transistors in saturation region.

Fig. 2
A circuit of V D I B A has transistors, current source pairs, amplifiers, and voltages, labeled V subscript D D and V subscript S S.

Internal representation of proposed VDIBA

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The small-signal equivalent model of the presented VDIBA configuration is displayed in Fig. 3. Analysis of this equivalent model of the VDIBA configuration results in the subsequent expression of overall gain:

$$ A_{{\text{V}}} = - \left( {\frac{1}{{g_{{{\text{m}}1}} + g_{{{\text{m}}3}} }}} \right)\left( {\frac{{g_{{{\text{m}}1}} g_{{{\text{m}}2}} }}{{g_{{{\text{m}}1}} + g_{{{\text{m}}2}} }} + \frac{{g_{{{\text{m}}3}} g_{{{\text{m}}4}} }}{{g_{{{\text{m}}3}} + g_{{{\text{m}}4}} }}} \right)\left( {\frac{{g_{{{\text{m}}5}} }}{{g_{{{\text{m}}6}} }}} \right) $$
(3)
Fig. 3
A circuit diagram of VDIBA. It has input and output voltage sources and 6 dependent current sources labeled g m 1 V g s 1, g m 3 V g s 3, g m 2 V g s 2, g m 4 V g s 4, g m 5 V g s 5, and g m 6 V g s 6.

Small-signal equivalent model of proposed VDIBA

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Here, gmk is the transconductance of kth NMOS/PMOS transistor. The transconductance depends on bias current Ibias, oxide capacitance Cox, mobility μk and aspect ratio (W/L). The tunability of the proposed VDIBA design is provided through changing the value of Ibias.

$$ g_{{{\text{mk}}}} = \sqrt {I_{{{\text{bias}}}} \mu_{{\text{k}}} C_{{{\text{ox}}}} \left( \frac{W}{L} \right)}_{{\text{k}}} $$
(4)

3 Multifunctional Active Filter Configuration

The proposed multifunctional active filter configuration is shown in Fig. 4. In this design, two VDIBA blocks are connected in cascade. The Arbel–Goldminz stage in each VDIBA is configured to act as a feedback amplifier.

Fig. 4
A circuit diagram of the proposed multifunctional active filter. Two blocks, labeled V D I B A, are connected with 3 voltage sources, labeled V 1, V 2, and V 3, and 2 voltage output sources at the terminals, z and w.

Proposed multifunctional active filter configuration

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The output port of the first VDIBA block is connected to the input port of the second VDIBA block. Two capacitors (C1 and C2) are connected at both the intermediate ports.

As shown in Fig. 4, the voltage mode multifunctional filter has multiple input voltages (V1, V2, V3) and single output (Vout). For the purpose of implementing a particular filter configuration, i.e., lowpass, highpass and bandpass, the voltages are arranged as per the following:

  1. (1)

    If voltage VLP is assigned to V3 and V1 = V2 = 0, the configuration implements second-order low pass (LP) filter. The voltage transfer function of the configuration is evaluated as

    $$ \frac{{V_{{{\text{out}}}} }}{{V_{{{\text{LP}}}} }} = - \frac{{g_{{\text{m}}}^{2} }}{{s^{2} C_{1} C_{2} + sg_{{\text{m}}} \left( {C_{2} + C_{1} } \right) + g_{{\text{m}}}^{2} }} $$
    (5)
  2. (2)

    If voltage VHP is assigned to V1 = V2 and V3 = 0, the configuration implements second-order high pass (HP) filter. The voltage transfer function of the configuration is evaluated as

    $$ \frac{{V_{{{\text{out}}}} }}{{V_{{{\text{HP}}}} }} = \frac{{s^{2} C_{1} C_{2} }}{{s^{2} C_{1} C_{2} + sg_{{\text{m}}} \left( {C_{2} + C_{1} } \right) + g_{{\text{m}}}^{2} }} $$
    (6)
  3. (3)

    If voltage VBP is assigned to V1 and V2 = V3 = 0, the configuration implements second-order band pass (BP) filter. The voltage transfer function of the configuration is evaluated as

    $$ \frac{{V_{{{\text{out}}}} }}{{V_{{{\text{BP}}}} }} = - \frac{{sg_{{\text{m}}} C_{1} }}{{s^{2} C_{1} C_{2} + sg_{{\text{m}}} \left( {C_{2} + C_{1} } \right) + g_{{\text{m}}}^{2} }} $$
    (7)

The parameters of filter, namely cut-off frequency (ωc) and bandwidth (BW) for the multifunctional filter configuration can be expressed as:

$$ \omega_{{\text{c}}} = \sqrt {\frac{{g_{{\text{m}}}^{2} }}{{C_{1} C_{2} }}} , $$
(8)
$$ {\text{BW}} = g_{{\text{m}}} \left( {\frac{{C_{1} + C_{2} }}{{C_{1} C_{2} }}} \right). $$
(9)

From (8) and (9), it can be noticed that the cut-off frequency (ωc) and bandwidth (BW) for the multifunctional filter can be electronically controlled. Both the filter characteristics can be varied by changing the transconductance (gm) of the VDIBA. In addition, the proposed configuration is resistorless and employs only grounded capacitors, thereby validating its suitability for fully integrated circuit applications.

4 Simulation Results

Various analyses including AC, DC and transient were performed on the proposed design using Cadence. The performance is analyzed through simulations carried out at 45-nm CMOS. The bias supply current (Ibias) is fixed at 145 μA and the voltages, VDD and VSS, is fixed at + 950 mV and − 950 mV, respectively.

DC analysis of proposed VDIBA configuration is carried out and the result is depicted in Fig. 5. During DC analysis, the output currents, Iz and Iw, are plotted with respect to difference of two input voltages, i.e., (Vp − Vn). Further, the transient analysis of proposed VDIBA configuration is performed and the result is shown in Fig. 6. Figures 7, 8 and 9, respectively, represent the frequency response of band pass, high pass and low pass obtained during AC analysis. For AC analysis, a sinusoidal signal of 10 mV amplitude and 10 kHz frequency is applied. Figures 7, 8 and 9 show the phase magnitude and gain magnitude plots which validate the working of the proposed configuration. The power dissipation of the multifunctional filter design is measured as 2.3 mW.

Fig. 5
Two line graphs plot I z, and I w versus input voltage. The estimated values are as follows. I z, (negative 500, 21), (0.0, 0), (500, 0). I w, (negative 500, negative 11), (0.0, 4), (500, 4).

DC response of proposed VDIBA configuration

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Fig. 6
Two line graphs plot V w, and input voltage versus time. The estimated values are as follows. V w, (0, negative 130), (2, negative 140), (4, negative 140), (5, negative 120). Input voltage, (0, 0), (1.5, 1.2), (2.5, negative 1.1), (4, negative 1.1), (5, 0).

Transient response of presented VDIBA design

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Fig. 7
A multi-line graph plots B P F gain, and B P F phase versus frequency. The estimated values are as follows. Gain plot, (10 to the 0, negative 150), (10 to the 7, negative 0.5), (10 to the 12, negative 112). Phase plot, (10 to the 0, 80), (10 to the 9, 280), (10 to the 12, negative 120).

AC response of band pass filter configuration with cut-off frequency of 10 MHz

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Fig. 8
A multi-line graph plots the H P F phase, and H P F gain versus frequency. The estimated values are as follows. Gain plot, (10 to the 0, negative 170), (10 to the 7, 0.0), (10 to the 12, 0.0). Phase plot, (10 to the 0, negative 80), (10 to the 6, negative 160), (10 to the 12, 0.0).

AC response of high pass filter configuration with cut-off frequency of 10 MHz

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Fig. 9
A multi-line graph plots L P F phase and L P F gain versus frequency. The estimated values are as follows. Gain plot, (10 to the 0, 0.0), (10 to the 7, 0.0), (10 to the 12, negative 190). Phase plot, (10 to the 0, negative 190), (10 to the 6, negative 190), (10 to the 12, negative 600).

AC response of low pass filter configuration with cut-off frequency of 10 MHz

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5 Conclusion

This article proposes an active multifunctional filter configuration using an innovative and stable design of VDIBA. This circuit can be tuned with external current. The working of both VDIBA and the multifunctional filter are validated with the help of simulation results. The average power consumption of filter configuration is measured to be 2.3 mW with cut-off frequency around 10 MHz. This proposed configuration can be used in high performance signal processing applications which is required for analog and digital communications.