1 Introduction

As the channel length of Si complementary metal–oxide–semiconductor (CMOS)-based transistors approaches the sub-10-nm domain, various short-channel effects such as subthreshold leakage and drain-induced barrier lowering (DIBL) degrade the device performance [1]. One of the solutions to such Si CMOS scaling issues is the application of emerging materials to replace silicon [2]. Graphene, a sheet of carbon atoms in a two-dimensional (2-D) honeycomb lattice [3], is a good candidate in this regard because of its impressive properties such as high charge carrier mobility, high optical transparency, low Johnson noise, excellent mechanical strength, nanometer-scale electron mean free path, atomically thin planar geometry, and high electrical and thermal conductivities [4,5,6,7,8,9,10]. However, it cannot be used directly for the device channel because of its zero bandgap energy. To open up the bandgap, it can be patterned into one-dimensional (1-D) graphene nanoribbons (GNRs) with widths of less than 10 nm [11].

GNR field-effect transistors (GNRFETs) represent a better alternative to silicon transistors due to their high charge carrier velocity, faster switching, and lower energy–delay product (EDP) [12]. However, the impact of process, voltage, and temperature (PVT) variations on GNRFETs is very large due to their small dimensions [13]. Some limited studies have been carried out to evaluate the impact of such variations on these transistors in both analog and digital applications. In Ref. [12], a Schottky barrier (SB)-type GNRFET (SB-GNRFET)-based LC-tuned voltage-controlled oscillator (LC-VCO) was designed and simulated but only considering variations in the manufacturing process such as the oxide thickness, the number of dimer lines, and the channel length. In Refs. [11, 14, 15], various SB-GNRFET-based digital logic circuits including INV, NAND, NOR, and XOR were simulated under PVT variations in terms of their delay and power. SB- and metal–oxide–semiconductor (MOS)-type GNRFET (MOS-GNRFET)-based standard ternary INV, NAND, NOR, and static random-access memory (SRAM) circuits were designed and simulated without consideration of PVT variations in Ref. [16]. In Ref. [17], a GNRFET-based eight-bit arithmetic logic unit (ALU) was simulated and compared with a Si CMOS design in terms of their delay and power, revealing that the SB-GNRFET design offered better performance. The results in Ref. [18] show that the write ability of GNRFET-based SRAM is better than that of a Si-CMOS design due to its lower write trip power, whereas the Si CMOS-based SRAM is more stable because of its large static power noise margin. In Ref. [19], MOS-GNRFET, MOS-carbon nanotube (CNT)FET, and Si CMOS-based conventional six-transistor (6T) SRAM circuits were simulated and the N-curve method was employed to analyze their stability under supply voltage variations. The results indicated nearly equivalent stability of the GNRFET- and CNTFET-based SRAM circuits, being better than that of the Si CMOS design.

In this paper, a conventional static flip-flop is designed using SB-GNRFETs, then extensive HSPICE simulations are performed to evaluate and analyze the impact of PVT variations in terms of its timing parameters, leakage and dynamic powers, and EDP. Monte Carlo (MC) simulations are performed to statistically analyze the impact of these variations. Moreover, stability analysis of the SB-GNRFET-based SRAM circuit under PVT variations is performed.

The remainder of this manuscript is organized as follows: Section 2 provides an overview on the variability and its various sources for graphene nanoribbons and GNR-based field-effect transistors. In Sect. 3, the SB-GNRFET-based flip-flop and its timing parameters are described. The SB-GNRFET-based 6T SRAM and its noise margin measurement using the N-curve and butterfly curve methods are also explained in this section. The simulation results as well as the effects of PVT variations and the stability analysis are presented in Sect. 4. Finally, the conclusions are drawn in Sect. 5.

2 Background

2.1 Variability

Variability is the deviation of a device parameter from its nominal value [20]. The scaling down of process technology increases the variability of the device parameters, strongly affecting the performance, yield, power consumption, and energy characteristics [21]. There are several methods, including statistical models, for the precise evaluation of this effect of variability [22]. Generally, there are three types of source of such variation, viz. process variations, environmental variations, and aging variations or reliability issues [23]. The process variations, also known as spatial variations [20], correspond to changes during the device manufacturing process [24], which affect parameters such as the channel length and width, the gate oxide thickness, and the threshold voltage [25]. Meanwhile, environmental, or dynamic, variations arise during the operation of a circuit and include changes in the supply voltage or temperature [26]. As the fabrication technology for GNRFET-based devices is still in an early phase [13], the effects of such variability on them are greater. Moreover, the bandgap of GNRs depend on their width, increasing their propensity towards process variations. Therefore, studying the effects of PVT variations on transistor performance is important to verify GNRFETs as a potential replacement for silicon-based transistors.

2.2 Graphene nanoribbon field-effect transistors (GNRFETs)

Graphene is one of the allotropes of carbon, comprising a single atomic layer of graphite, which is structurally similar to a 2-D honeycomb lattice but is not a Bravais lattice [27]. Graphene acts as a metal because the bandgap between its conduction and valence bands is zero [28]. Hence, this material is unsuitable for application as a transistor channel. However, conversion of graphene into a 1-D GNR with sub-10-nm width opens up the bandgap [11]. The energy gap of a GNR is inversely proportional to its width [29]. GNRs can be categorized into two types: zigzag GNRs (ZGNRs) and armchair GNRs (AGNRs) [30], as shown in Fig. 1, differing in the type of edge or chiral angle or their orientation along the GNR lattice. ZGNRs are always metallic, while AGNRs are metallic or semiconductor depending on their width [31].

Fig. 1
figure 1

The structure of ZGNRs and AGNRs

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GNR-based transistors can be classified into two main types depending on their structure. MOS-GNRFETs have an n–i–n or p–i–p structure consisting of a GNR channel plus doped source and drain regions. SB-GNRFETs, on the other hand, have an m–i–m structure, consisting of a GNR channel plus a metallic source and drain [32]. MOS-GNRFETs exhibit monotonic I–V curves, as opposed to the ambipolar curve observed for SB-GNRFETs, which occurs due to the SB at the graphene–metal junctions. As a result, MOS-GNRFETs offer larger ION/IOFF ratios than SB-GNRFETs. Some of the benefits of SB-GNRFETs are as follows [11, 15]:

  • The lack of doping in the metallic drain and source regions, meaning that they are not very sensitive to process variations

  • The absence of contacts with high electrical resistance in vias within the drain and source

  • The lack of extra graphene–metal vias due to the metal-based interconnects and terminals

Figure 2 shows the schematic structure of a SB-GNRFET. Parallel AGNRs are used in this structure to increase the driving strength of the transistor [11]. The parameters Lch, Wgate, Lres, 2Wsp, and fdop denote the channel length, the gate width, the length of the reservoirs, the distance between two adjacent GNRs in the same device, and the doping level of the drain and source, respectively. Wch denotes the width of each GNR, which can be determined from the number of dimer lines N as follows:

$$W_{{{\text{CH}}}} = \sqrt 3 d_{{{\text{cc}}}} \frac{{\left( {N_{A} - 1} \right)}}{2},$$
(1)
$$W_{{{\text{GATE}}}} = \left( {W_{{{\text{CH}}}} + 2W_{{{\text{sp}}}} } \right) \times N_{{{\text{ribb}}}},$$
(2)

where \(d_{{{\text{cc}}}} = 1.42\, {\text{nm}}\) is the carbon–carbon bond distance and \(N_{{{\text{ribb}}}}\) is the number of ribbons. The index A in \(N_{A}\) represents the number of dimer lines of AGNRs.

Fig. 2
figure 2

The structure of a SB-GNRFET with four parallel armchair-type GNRs [14]

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3 Circuit design and specifications

3.1 The SB-GNRFET-based flip-flip and its timing parameters

Flip-flops (FFs) are one of the main building blocks used in digital system design, allowing the storage of data [33]. Figure 3 shows the transistor-level structure of the SB-GNRFET-based rising-edge-triggered FF. Most standard cell libraries employ this design due to its attributes of simplicity, compactness, robustness, and energy efficiency [34].

Fig. 3
figure 3

The transistor-level structure of the SB-GNRFET-based FF

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A FF operates correctly when its data and clock inputs satisfy basic timing limitations, e.g., on the setup and hold times. Thus, the input data should be held steady before and after the clock edge as long as the setup time and hold time, respectively [35]. Figure 4 qualitatively exhibits plots of the clock to output delay (tCQ) and the data to output delay (tDQ) versus the time from the arrival of the rising data to the rising edge of the clock (tDC).

Fig. 4
figure 4

Plots of tDQ and tCQ versus the time from the arrival of the rising data to the rising edge of the clock tDC [36]

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According to Fig. 4, tCQ has a constant minimum value [called the contamination delay (tccq)] and also tDQ, which is the sum of tDQ and tCQ (\(t_{{{\text{DQ}}}} = t_{{{\text{DQ}}}} + t_{{{\text{CQ}}}}\)), has a slope equal to −1 when tDC is very large. On the other hand, as tDC decreases, tCQ increases until reaching an asymptote, after which the FF cannot correctly capture the data while tDQ reaches a minimum (tDQ,min) at the point where tCQ has a slope of −1. The setup time (tsetup) and propagation delay (tpcq) are defined at tDQ,min [36]. The hold time (thold) is the minimum delay from the clock to data changing, such that \(t_{{{\text{CQ}}}} \le t_{{{\text{pcq}}}}\) [34]. The sum of tsetup and thold is defined as the possible minimum width of a data pulse. The setup time and the hold time can be both positive and negative, depending on the supply voltage, the circuit topology, and the simulation setup [37].

3.2 The SB-GNRFET-based 6T SRAM

The variations in the device parameters increase for deep-submicron technologies, which can seriously affect the stability of SRAM cells [38]. In the structure of the SB-GNRFET-based 6T SRAM shown in Fig. 5a, the pull-down transistors NM1 and NM2 and the pull-up transistors PM1 and PM2 form two back-to-back inverters. The output nodes of the inverters (Q and QB) are coupled with the bit lines (BL and BLB) by the access transistors NM3 and NM4. In standby mode, the word line (WL) has a logical value of “0” hence NM3 and NM4 turn off and only two inverters remain. In this mode, the static noise margin (SNM) can be determined by plotting the butterfly voltage transfer curve (VTC) for the input and output nodes of the two inverters. The SNM is the length of the side of the largest square that can be inscribed between these curves, called the hold margin (Fig. 5b). In read mode, the BL and BLB are initially precharged to VDD. The WL is high (VDD), and the output value of the two inverters is transferred to the bit lines (Q to BL and QB to BLB). The SNM obtained in this mode is called the read margin and is smaller than the SNM (Fig. 5c). In write mode, the WL is high while the BL can be high or low. The write margin is the size of the smallest square that can be drawn between the two VTCs (Fig. 5d) [34, 39, 40].

Fig. 5
figure 5

a The SB-GNRFET-based 6T SRAM and its b hold circuit and hold margin, c read margin circuit and read margin, and d write margin circuit and write margin

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To perform the stability analysis of the SRAM cell, three butterfly curves must be drawn in conjunction with the Iq–Vq N-curve. This plot is drawn for the following conditions: BL and BLB are precharged to VDD, the initial value of the nodes Q and QB is “1” and “0”, respectively, and the WL is high. Then, a voltage source Vin is swept from 0 V to VDD at the node Q and the current Iin is measured (Fig. 6a). This plot gives the static voltage noise margin (SVNM), the static current noise margin (SINM), the write trip voltage (WTV), and the write trip current (WTI), as shown in Fig. 6b. The N-curve crosses the horizontal axis at two stable points A and C, and a metastable point B. The SVNM is the maximum direct-current (DC) voltage that can be tolerated at the input of the 6T SRAM cell without changing its state, being defined as the voltage difference between the points A and B. The SINM is the maximum DC current that can be injected into the input of the SRAM before changing its state, being defined as the maximum current between points A and B. The WTV is the voltage that can be applied before varying the content of the internal node, being measured as the voltage difference between points B and C. The WTI is the minimum current between the points B and C that has to be applied to write into the cell [19, 41, 42].

Fig. 6
figure 6

a The experimental setup for the N-curve of the 6T SRAM cell and b the N-curve

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4 The Simulation Results

This section presents the simulation setup and results. The simulations are performed in HSPICE utilizing the SB-GNRFET model presented in Ref. [11] at 25 °C.

4.1 The SB-GNRFET-based flip-flop

The FF circuit shown in Fig. 3 is designed using the SB-GNRFET device parameters presented in Table 1. Using Eq. (2), the gate width of the SB-GNRFET is obtained as 21.59 nm. The data and clock inputs are passed through a buffer (two SB-GNRFET-based inverters in series) to produce realistic input signals. The FF is connected to a fanout-of-4 circuit as its load. To compare the results of the SB-GNRFET-based FF with a Si CMOS design, the Si CMOS transistor parameters are considered to be \(L_{{{\text{ch}}}} = 16\,{\text{nm}}\) and \(w_{{{\text{ch}}}} = 21.59\,{\text{nm}}\) with \(V_{{{\text{DD}}}} = 0.7\,{\text{V}}\). Figure 5 shows the plots of tCQ and tDQ versus the time from the arrival of the rising data to the rising edge of the clock tDC for both the SB-GNRFET and Si-CMOS-based FF. Their timing parameters, power consumption, power–delay product (PDP), and EDP are presented in Table 2. As can be inferred from this table, the minimum possible width of the data pulse, which is the sum of the setup and hold times, is obtained as 7.82 ps and 21.32 ps for the SB-GNRFET and Si-CMOS design, respectively. The power reported in Table 2 is the average power dissipated in the FF circuit during four operating cycles. The following equations are used to obtain the PDP and EDP values (Fig. 7):

$${\text{PDP}} = P_{{{\text{avg}}}} \times t_{{{\text{pcq}}}},$$
(3)
$${\text{EDP}} = {\text{PDP}} \times t_{{{\text{pcq}}}}.$$
(4)
Table 1 The design parameters of the SB-GNRFET device
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Table 2 The timing parameters, power consumption, PDP, and EDP for the SB-GNRFET and Si-CMOS-based FFs
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Fig. 7
figure 7

The plots of tDQ and tCQ versus tDC for the a SB-GNRFET-based FF and b Si-CMOS-based FF

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4.2 The effects of PVT variations

To study the performance of the SB-GNRFETs under PVT variations, the sensitivity of the main characteristics of the FF such as the timing parameters, power (leakage, dynamic, and total), and EDP to these variations is evaluated and analyzed. Here, the PVT variations include changes in the channel length, gate oxide thickness, number of dimer lines, line-edge roughness, supply voltage, and operating temperature. Figures 8,9,10,11,12,13, and 14 show the effect of the PVT variations on the selected FF characteristics. The impact of channel length (Lch) variations is shown in Fig. 8. Lch has a first-order influence on the delay and performance. The gate capacitance is directly dependent on Lch, which results in a longer delay for longer channel lengths. As the channel length is increased, the dynamic power also increases while the leakage power does not change considerably. Figure 9 shows the effect of gate oxide thickness (Tox) variations. Tox has a first-order effect on the delay, power, EDP, and performance. Increasing Tox causes a reduction of the power and delay due to a drop in the ON-current.

Fig. 8
figure 8

The effect of the channel length Lch on the a timing parameters, b powers, and c EDP of the SB-GNRFET-based FF

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Fig. 9
figure 9

The effect of the gate oxide thickness Tox on the a timing parameters, b powers, and c EDP of the SB-GNRFET-based FF

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Fig. 10
figure 10

The effect of the number of dimer lines N on the a timing parameters, b powers, and c EDP of the SB-GNRFET-based FF

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Fig. 11
figure 11

The effect of the line-edge roughness Pr on the a timing parameters, b powers, and c EDP of the SB-GNRFET-based FF

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Fig. 12
figure 12

The effect of the supply voltage VDD on the atsetup and tpcq, btccq and thold, c leakage power, d dynamic power, e total power, and f EDP of the SB-GNRFET and Si-CMOS-based FFs

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Fig. 13
figure 13

The effect of the temperature on the atsetup and tpcq, btccq and thold, c leakage power, d dynamic power, e total power, and f EDP of the SB-GNRFET and Si-CMOS-based FFs

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Fig. 14
figure 14

The effect of the transistor sizes on the atsetup and tpcq, btccq and thold, c leakage power, d dynamic power, e total power, and f EDP of the SB-GNRFET and MG Si-CMOS-based FFs

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As can be seen from Fig. 10, the number of dimer lines (N) has a periodic effect on the bandgap. The widest bandgap and highest ION/IOFF current ratio are obtained when the number of dimer lines satisfies \(N = 3p + 1\) (e.g., 7, 10, and 13). The results for \(N = 3p + 2\) (e.g., 8, 11, and 14) are not shown in Fig. 10 because of their very small bandgap and ION/IOFF ratio. Indeed, these GNRs are not suitable for digital circuit applications. For \(N = 3p\) (e.g., 6, 9, and 12), the bandgap is moderate. Simulations are performed for \(N = 6, 9, 12, 13, 16\) dimer lines, which can be ordered based on decreasing energy bandgap as 6, 13, 9, 16, and 12. The delay and power show a direct and inverse relation with the bandgap, respectively. As a result, the N corresponding to the longest delay will have the least power consumption, and vice versa.

Figure 11 shows the impact of the line-edge roughness using the parameter Pr. With increasing line-edge roughness, ION reduces while IOFF first increases then decreases [11]. However, the ION/IOFF ratio decreases. As shown in Fig. 11, the delay and power rise with increasing line-edge roughness. The effect of the supply voltage (VDD) on the SB-GNRFET and Si-CMOS-based FFs is shown in Fig. 12. The delay decreases with increasing supply voltage, while the power increases. The SB-GNRFET design consumes more power compared with the Si CMOS design, but it has a shorter delay. In the supply voltage range from 0.4 to 0.6 V, the SB-GNRFET design shows better performance than the Si CMOS design, since its EDP is lower. Figure 13 shows the influence of temperature on the SB-GNRFET and Si-CMOS-based FFs. The effect of temperature variations on these designs is quite different. For the Si CMOS design, increasing the temperature results in a longer delay and higher power, while for the SB-GNRFET design, it reduces both the power and delay. Moreover, variation of the temperature has only a small effect on the delay of the SB-GNRFET-based FF. Generally, the SB-GNRFET-based FF shows better performance than the Si-CMOS design due to its lower EDP.

4.3 The simulations at different technology nodes

To compare the performance of the SB-GNRFET-based FF versus conventional Si CMOS technology, different simulations are performed using a multigate Si CMOS predictive technology model (MG Si-CMOS PTM) [43] at the 7-, 10-, 14-, and 16-nm technology nodes, at nominal supply voltages of 0.7, 0.75, 0.8, and 0.85 V, respectively. The equivalent width of a MG Si-CMOS with n fins is defined by \(n \times \left( {T_{{{\text{fin}}}} + 2 \times H_{{{\text{fin}}}} } \right)\), where \(H_{{{\text{fin}}}}\) is the fin height of the transistor and \(T_{{{\text{fin}}}}\) is the fin thickness [44]. The number of dimer lines, the number of ribbons, and the spacing between two adjacent ribbons are chosen such that the gate width of the SB-GNRFET becomes equal to the effective width of the MG Si-CMOS device. Values of \(N = 12\) and \(2W_{{{\text{sp}}}} = 2 {\text{nm}}\) are chosen, thus determining the number of ribbons (Nribb). The transistor sizes in the different technology nodes are presented in Table 3. Figure 14 shows the timing, power, and EDP characteristics of both the SB-GNRFET and MG Si-CMOS FF designs. A reduction in the transistor size leads to a shorter delay and reduced power. As seen in Fig. 14f, the SB-GNRFET-based FF is better than the MG Si-CMOS design at the different technology nodes, since it has a lower EDP.

Table 3 The transistor sizes at the different technology nodes
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4.4 Monte Carlo simulations

The effect of varying each parameter one at a time is evaluated and analyzed in the previous section. However, more than one parameter may vary from its nominal value [13]. MC simulations are performed for statistical analysis of the sensitivity to the parameters, changing the supply voltage, number of dimer lines, gate oxide thickness, and channel length. The simulations are performed in two different cases, with and without the line-edge roughness effect. A uniform distribution function is used for the supply voltage. For the other parameters, a Gaussian distribution function with 3σ variation is applied. Since the number of dimer lines is an integer, the generated random value is converted to an integer. Each parameter is changed by ±10% around its nominal value reported in Table 1 using \(N_{m} = 1000{ }\) samples in the MC simulations. Figures 15,16,17,18, and 19 show the results for the distribution of the tCQ delay and EDP of the SB-GNRFET-based FF as histograms. Each of these figures also shows several distribution functions that best fit the results. The mean (µ) and standard deviation (std) of the data based on a normal distribution function are presented in Table 4. For example, the results for both the ideal (\(P_{\rm r} = 0\)) and nonideal (\(P_{\rm r} = 2.5\%\)) transistors indicate that varying VDD and N has the greatest and least effect on the total power. The effect of varying VDD and N is about +6.47% and −0.77% for \(P_{\rm r} = 0\) and +2.80% and −0.33% for \(P_{\rm r} = 2.5\%\), respectively. The results also show that the mean value of each of the powers does not change much with variation of the channel length. The last row of the table presents the results obtained under simultaneous variations of the target parameters.

Fig. 15
figure 15

The histograms of (a, c) tCQ and (b, d) the EDP obtained from the MC simulations with a uniform distribution of \(V_{{{\text{DD}}}} \pm 10\%\) and (a, b\(P_{\rm r} = 0\)) or (c, d) \(P_{\rm r} = 2.5\%\)

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Fig. 16
figure 16

The histograms of (a, c) tCQ and (b, d) the EDP obtained from the MC simulations with a Gaussian distribution of \(N \pm 10\%\) and (a, b) \(P_{\rm r} = 0\) or (c, d) \(P_{\rm r} = 2.5\%\)

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Fig. 17
figure 17

The histograms of (a, c) tCQ and (b, d) the EDP obtained from the MC simulations with a Gaussian distribution of \(T_{{{\text{ox}}}} \pm 10\%\) and (a, b) \(P_{\rm r} = 0\) or (c, d) \(P_{\rm r} = 2.5\%\)

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Fig. 18
figure 18

The histograms of (a, c) tCQ and (b, d) the EDP obtained from the MC simulations with a Gaussian distribution of \(L_{{{\text{ch}}}} \pm 10\%\) and (a, b) \(P_{\rm r} = 0\) or (c, d) \(P_{\rm r} = 2.5\%\)

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Fig. 19
figure 19

The histograms of (a, c) tCQ and (b, d) the EDP obtained from the MC simulations with the variation of all parameters and (a, b) \(P_{\rm r} = 0\) or (c, d) \(P_{\rm r} = 2.5\%\)

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Table 4 The mean (µ) and standard derivation (std) of the results obtained using the normal distribution function
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4.5 The SB-GNRFET-based 6T SRAM

In this section, the SB-GNRFET-based 6T SRAM cell depicted in Fig. 5a is simulated and compared with the Si CMOS design in terms of their stability. The transistor sizes of the 6T SRAM cell are obtained by satisfying the following two conditions: (1) ratio restrictions and (2) optimal layout density [34]. To satisfy these two conditions, the size of the pull-down transistors NM1 and NM2 should be greater than that of the pull-up transistors PM1 and PM2, while the size of the access transistors NM3 and NM4 should lie in between. Table 5 presents the transistor sizing for both the SB-GNRFET and Si-CMOS-based 6T SRAM cells. The simulations are performed at 25 °C with a nominal supply voltage of 0.5 V and 0.7 V for the SB-GNRFET and Si-CMOS design, respectively. The butterfly curve and N-curve of the 6T SRAM cells are shown in Fig. 20. All the noise margins are specified in these plots and are also presented in Table 6. The static power noise margin (SPNM) and the write trip power (WTP) are obtained using Eqs. (5) and (6). The SPNM and WTP are measures of the read stability and write-ability, respectively. A design with a high SPNM is more stable, while a design with a low WTP has better write-ability [19]. The SB-GNRFET-based 6T SRAM cell has better write-ability than the Si-CMOS design, but its stability is lower.

$${\text{SPNM}} = {\text{SVNM}} \times {\text{SINM}},$$
(5)
$${\text{WTP}} = {\text{WTV}} \times {\text{WTI}}.$$
(6)
Table 5 The transistor sizing for the 6T SRAM cells
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Fig. 20
figure 20

The butterfly curve and N-curve of the 6T SRAM based on a SB-GNRFETs and b Si CMOS

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Table 6 The noise margin values for both 6T SRAM designs
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The effect of varying VDD on the stability of the SB-GNRFET- and Si-CMOS-based 6T SRAM cells is shown in Fig. 21. The voltage margins (SVNM and WTV), the magnitude of the current margins (SINM and WTI), and the (hold, read, and write) noise margins increase with VDD. These margins decrease when the line-edge roughness Pr is increased, as shown in Fig. 22.

Fig. 21
figure 21

The impact of VDD on the stability of the SB-GNRFET- and Si-CMOS-based 6T SRAM cells in terms of the a voltage margins, b current margins, c noise margins, and d power margins

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Fig. 22
figure 22

The effect of Pr on the stability of the SB-GNRFET-based 6T SRAM cell in terms of the a voltage margins, b current margins, c noise margins, and d power margins

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5 Conclusions

The impact of PVT variations such as changes in the channel length, gate oxide thickness, number of dimer lines, and line-edge roughness on the timing parameters, power, and EDP of an SB-GNRFET-based FF is evaluated and analyzed. MC simulations are performed for statistical analysis of these variations. The results show that changing the number of dimer lines N from the nominal value of 12 to 13 has the greatest effect on the propagation delay (about +315.48%), while changing the operating temperature from its nominal value of 25 to 100 °C has the least effect. This variation affects the propagation delay and the total power by about −1.43% and −4.38%, respectively. With an increase of the supply voltage by 0.1 V above its nominal value, the total power changes by about  206.03% while the propagation delay decreases by about 13.44%. With scaling down of the technology node from 16 to 14 nm, the propagation delay and the total power decrease by nearly 2.25% and 18.52%, respectively. Moreover, the SB-GNRFET-based FF is better than the Si-CMOS and MG Si-CMOS designs in terms of the EDP. SB-GNRFETs have immense potential for use in digital circuit design. However, variations have a greater effect on SB-GNRFET circuits in the presence of line-edge roughness (LER); For example, the EDP increases by about 394.94%, 396.81%, 389.47%, 398.41%, and 375.09% when varying VDD, Tox, N, and Lch or all these parameters simultaneously, respectively.

The stability of the SB-GNRFET-based SRAM cell is evaluated under variations of parameters such as the supply voltage and line-edge roughness; For instance, a +20% change of the supply voltage from its nominal value of 0.5 V results in an increase of about 19.67% and 47.80% in the static noise margin and the static current noise margin, while these parameters decrease by about 22.25% and 65.66%, respectively, when the line-edge roughness is 2.5%. Based on these results, the SB-GNRFET-based 6T SRAM exhibits better write-ability than the Si CMOS design.