1 Introduction

The occurrence of short channel effects (SCE), leakage current, band to band tunneling (BTBT) and static power dissipation is due to the downscaling of planar Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) into the nanometer regime. The SOI FinFET devices are the best solution to this problem [1]. International Technology Roadmap for Semiconductors (ITRS) suggests various new materials for scaling the gate dielectric below 2 nm for preventing the high leakage current caused by the generation of direct tunneling gate leakage current [2]. Recently, several novel materials like Al2O3 (6 eV), HfO2 (6 eV), La2O3 (5.18 eV) and ZrO2 (5.8 eV) have come into existence in place of SiO2 (9 eV) which have high band gap value [3,4,5,6,7,8,9]. It has been noticed that a gate dielectric with k over 40 is preferred, and LaZrO2 has been recognized as an appropriate high-k gate dielectric material for sub-22 nm node FinFET devices [10,11,12].

SRAM comprises of many cell areas in the system on chip designs due to the massive requirement of transistors for a single SRAM cell array. The circuit designed with a scaled device and high-k gate dielectric material results in improved storage capacity, fast switching speed, increased efficiency of footprint and less power consumption. The use of high-k dielectrics in manufacturing has paved the way for their use in applications beyond traditional logic and memory devices. The studies of SNM for SRAM with SOI FinFETs have been contributing to technological advancement [13,14,15,16,17,18,19]. In this paper, performance analysis of FinFET device created with Lanthanum doped zirconium oxide (LaZrO2) as a compound gate dielectric was done in Technology Computer-Aided Design (TCAD) environment.

Further, SRAM cells were made with matched size n-FinFET and p-FinFET devices. The functionality of the SRAM cells for reading and writing operation was investigated using timing diagrams. The SRAM cell's voltage transfer characteristic (VTC) has been demonstrated by analyzing the SRAM read and write operations. The static noise margin (SNM) SRAM read mode and SRAM write mode were evaluated with the butterfly curve method. The impact of supply voltage fluctuations on circuit performance has also been analyzed.

This work has been organized into multiple sections, Sect. 2 discusses the FinFET device and SRAM cell design and simulation methodology. Section 3 illustrates the results of the device, discussions and their circuit using different operating modes and stability parameters. The impact of supply voltage variations on Stability parameters and leakage power is also discussed in this section. The last section summarizes the conclusion of the research work.

2 Design and Simulation Methodology

Nanoscale FinFET device simulations are accomplished in the TCAD simulator. It was noticed that a gate dielectric with k over 40 is preferred and LaZrO2 has been recognized as an appropriate high-k gate dielectric materials for sub-22 nm node FinFET devices [12, 20,21,22]. The novel high-k gate dielectric material is chemically stable in contact with Silicon and has high crystallization temperature, high dielectric constant (k=40) and wide energy band gaps (~ 6 eV) as compared to SiO2. The high-k gate dielectric material has been deposited on an active silicon channel by Atomic Layer Deposition and Chemical Vapor Deposition method at high temperature [11, 12, 23, 24]. The 3D structure of n-FinFET and p-FinFET devices with matched size, as outlined in Fig. 1, was used for devising the 6T SRAM cells. The device specifications for FinFET devices according to ITRS have been summarized in Table 1 [25]. Table 2 describes important TCAD device parameters of the 14 nm processes for 6T SRAM cell circuits [21, 22, 26,27,28,29].

Fig. 1
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Bird’s-eye view of FinFET structures

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Table 1 FinFET parameters used in simulation (as per ITRS [25])
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Table 2 Important TCAD designing parameters for FinFET based 6 T SRAM Cell
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The simulated devices are designed at 300K using models such as Drift diffusion model (DDM), Lombardi Surface mobility model, Shockley Read Hall Model and Kane’s Model [28]. Figure 2 illustrates the simulation procedure in Visual TCAD for devising FinFET. The simulator's validity was examined by matching its results with the published experimental data in the TCAD environment at 300 K as shown in Fig. 3 [30]. It proves that this paper's models and parameters are valid [28]. The proposed device was simulated using the following models:

  1. 1.

    DDM, which solves a certain set of Poisson equations as mentioned in Eq. (1).

    $$ \nabla \cdot\upvarepsilon \nabla \uppsi = - {\text{q}} \left( {{\text{p}} - {\text{n}} + N_{{{\text{D}} }}^{ + } - N_{{{\text{A}} }}^{ - } } \right) $$
    (1)

    where \({\uppsi } \) is the electrostatic potential of the vacuum level, n and p represent the electron and hole concentration, \({\text{N}}_{{\text{D }}}^{ + }\) and \({\text{N}}_{{\text{A }}}^{ - }\) represent the ionized doping concentration and q is an electron charge. The lattice temperature is kept uniform throughout the Drift Diffusion model.

  2. 2.

    Lombardi Surface mobility model has been introduced to address carrier mobility in the inversion layer of designed device. A cumulative carrier mobility is calculated from doping based bulk mobility (µB), mobility degradation, scattering due to acoustic phonon (µac) and scattering because of surface roughness (µSR) as follows:

    $$\upmu _{{\text{S}}}^{ - 1} = \upmu _{{{\text{B}} }}^{ - 1} + \upmu _{{{\text{ac}} }}^{ - 1} + \upmu _{{{\text{SR}}}}^{ - 1} $$
    (2)
  3. 3.

    Kane’s Model can explain the generation of carriers through Band to band tunneling (GBB) which is expressed as:

    where E denotes electrical field magnitude, EG represents the band-gap, A.BBT and B.BBT are experimental fitting parameters.

    $$ {\text{G}}^{{{{\rm BB}}}} { } = {\text{A.BBT.}}\frac{{{\text{E}}^{2} }}{{\sqrt {{\text{E}}_{{\text{g}}} } }} \exp \left( { - {\text{B.BBT.}} \frac{{{\text{E}}_{{{\rm G}}}^{\frac{3}{2}} }}{{\text{E}}}} \right) $$
    (3)
  4. 4.

    The carrier recombination process is elaborated by SRH Model which is defined in Eq. (4)

    $$ {\text{U}}_{{{\text{SRH}}}} = \frac{{{\text{pn}} - {\text{n}}_{{{\text{ie}}}}^{2} }}{{\uptau _{{\text{p}}} \left[ {{\text{n}} + {\text{n}}_{{\text{i}}} {\text{e}}^{{\frac{{{\text{E}}_{{\text{T}}} }}{{{\text{KT}}_{{\text{L}}} }}}} } \right] +\uptau _{{\text{n}}} \left[ {{\text{p}} + {\text{ n}}_{{\text{i}}} {\text{e}}^{{\frac{{{\text{E}}_{{\text{T}}} }}{{{\text{KT}}_{{\text{L}}} }}}} } \right]}} $$
    (4)
Fig. 2
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Flowchart of the simulation procedure involved in Visual TCAD

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Fig. 3
figure 3

Id–Vg characteristics of FINFET with reference [30] and simulation

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where \({\uptau }_{{\text{n}}} { }\) and \({\uptau }_{{\text{p }}}\) are carrier lifetime which are reliant on doping concentration, ni denotes the intrinsic carrier concentration, ET is energy trap level, TL is lattice temperature [22, 28].

The VI characteristics of FinFETs for input and output voltages are demonstrated in Fig. 4. It was found that both n- and p-channel FinFET devices exhibit identical characteristics for both input and output transfer characteristic curves.

Fig. 4
figure 4

VI characteristics of n-FinFET and p-FinFET devices

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3 Results and Discussions

3.1 Optimized FinFET Performance

Table 3 presents the performance of matched Pull Down (PD) and Pull Up (PU) FinFET devices adopted for devising Cell-I. The performance parameters such as on-current (ION), leakage current (IOFF), Subthreshold Swing (SS), Drain induced barrier lowering (DIBL) and Transconductance (gm) are extracted from VI characteristic curves, as illustrated in Fig. 4a. These metrics have been measured for two operating regions, such as the linear and the saturation region. Both devices showed almost similar characteristics for the two operating regions.

Table 3 FinFET I–V Targets
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3.2 Basic Operations in 6 T SRAM Cell

6T SRAM cell can cache one-bit data using two cross-coupled inverters, and it can keep its saved data as long as power is supplied. FinFET based 6T SRAM cells containing different fin configurations in TCAD implementation are shown in Fig. 5 and Table 4. It is observed from Table 4 that Cell-II consumes more area than Cell-I.

Fig. 5
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TCAD implementation of FinFET based 6 T SRAM cells containing different fin configurations

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Table 4 SRAM cells with different fin configurations
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The basic operations involved in 6T SRAM are elaborated below:

  • Hold operation During this operation, the wordline (WL) is connected to the ground (Gnd). The access devices T5 and T6 are switched off and the devices T1, T2, T3, and T4 are disconnected from bitlines, as shown in Fig. 6a. The stored data bit is retained as long as the devices are cut off from the bit-lines.

  • Read Operation WL is connected to Vdd for reading operations, and bitlines are pre-charged to Vdd. In this operation, access n-FinFET devices T5 and T6 are turned ON. Let us assume one condition: M = “1” and Mbar = “0” which causes the devices T1 and T4 to turn off and T3 and T2 are turned on. The bit-line current will flow through Bitbar-line, then passes to the ground through T6 and T2 as outlined in Fig. 6a. Therefore, the voltage at bitbar-line discharges while the energy at bit-line is maintained at Vdd, as indicated in Fig. 6b. Figure 6c outlines the read operation simulated in TCAD for FinFET based 6 T SRAM cell. The timing diagram for reading current is presented in Fig. 6d [16, 18, 31, 32].

  • Write operation The voltage levels of bitlines are opposite to each other as delineated in Fig. 7a, and the WL is connected to Vdd as outlined in Fig. 7b. This condition will turn on the transistors T5 and T6. In this situation, the voltage level of node M drops and the voltage level of node Mbar rises until the voltage level of M is enough to turn on T4 and turn off T2, or the voltage level at node Mbar is sufficient to turn on T3 and turn off T1. Subsequently, the voltage level of Mbar and M nodes will be turned over to “1” and “0” respectively, as displayed in Fig. 7c. Figure 7 outlines the write operation simulated in TCAD for FinFET based 6 T SRAM cell. The timing diagrams for bit-line, output M and write current are depicted in Fig. 7d, Fig. 7e, f, respectively [16, 18, 31, 32].

Fig. 6
figure 6

Read operation for FinFET based 6 T SRAM Cell-I in TCAD

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Fig. 7
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Write operation for FinFET based 6 T SRAM Cell-I in TCAD

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3.3 Stability Analysis of SRAM Cell-I and SRAM Cell-II

  • Read Static Noise Margin (RSNM): RSNM is the least amount of noise voltage level needed at the storage nodes of SRAM to flip the cell data [16, 31, 33]. The set-up utilized for measuring the RSNM parameter of SRAM Cell-I is outlined in Fig. 8. WL and bit-line are connected to Vdd in this set-up, and the feedback is disconnected from the cross-coupled inverters. The voltage transfer curve (VTC) of the inverter in the half circuit has been plotted with its inverse to form a butterfly curve. The largest side of the square fitted in the butterfly curve signifies as Read SNM. The extracted value of RSNM for 6 T SRAM Cell-I at Vdd = 0.8 V is 175 mV, as shown in a butterfly curve in Fig. 10.

  • Write Static Noise Margin (WSNM): Write Margin is another crucial parameter that ensures robust write operation and is calculated using a butterfly curve, as demonstrated in Fig. 10. During the write operation, the cross-coupled inverters are disconnected from each other. The WL joins Vdd, and the data is forced onto the bitlines from the cell, as shown in Fig. 9. The inverters' VTCs in half circuits has been plotted between M and Mbar, since the bitline is connected to Gnd and bitbar-line is connected to Vdd. Therefore, the VTCs of the two halves are not the same. The larger side of the fitted square, in between the two curves, as depicted in Fig. 10, is named as WSNM. A higher WSNM implies better write stability [16, 31,32,33,34].

Fig. 8
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Set-up for measuring RSNM of FinFET based 6 T SRAM Cell-I

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Fig. 9
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Set-up for measuring WSNM of SRAM Cell-I

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Fig. 10
figure 10

VTC for indicating RSNM and WSNM for SRAM Cell-I

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3.4 Impact on 6 T SRAM Cells Stabilities due to supply voltage variations

The impact of voltage variations on RSNM and WSNM was analyzed over 0.4–1.0 V for 6T SRAM Cell-I and Cell-II. Figure 11a illustrates that Cell-I shows improved results for RSNM and WSNM w.r.t Cell-II. It is also noted that RSNM enhances by 14.6× and 4.6× for Cell-I and Cell-II respectively, as the voltage varies from 0.4 to 1.0 V. The Cell-I and Cell-II demonstrated similar improvement for the lower voltage for RSNM. It is clear from Fig. 11b that the percentage change of WSNM of Cell-I over Cell-II increases from 20% at 0.4 V to 75% at 1.0 V. The area consumed by Cell-II is 14% more than Cell-I, as outlined in Table 4. Therefore, the proposed Cell-I achieves considerable improvement in the stability of FinFET based 6T SRAM cell [35, 36].

Fig. 11
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Impact of supply voltage variation on RSNM and WSNM for Cell-I and Cell-II

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3.5 Impact on 6 T SRAM Cells Leakage Power Due to Supply Voltage Fluctuations

The leakage power is the SRAM cell's power in the absence of any switching activity or during hold mode. The multiplication of supply voltage and leakage current signifies leakage power. Subthreshold current is the main contributor to leakage current that flows from drain to the source when the device is in the cutoff state [37, 38]. Figure 12a, b demonstrates that the leakage power of Cell-II is more (in nanowatts) as compared to Cell-I (in femtowatts) due to the large leakage current produced by the transistors of Cell-II. The leakage suppression can be done by minimizing supply voltage, as it has been observed that the supply voltage of 1 V has 2.5 times more leakage power than Vdd=0.4 V [39].

Fig. 12
figure 12

Leakage power estimation for SRAM Cell-I and SRAM Cell-II

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3.6 Comparison of Proposed FinFET Based 6 T SRAM Cell-I with Published Work

Carlson et al. [40] gave the values 175 mV and 0.358 µm2 for RSNM and area consumption of cell, while the proposed Cell-I demonstrates improvement of 37% and 78% respectively, for these metrics. The proposed cell presents about 1.5 × and 2 × enhancement for RSNM compared to results extracted by Li et al. and Lim et al. respectively [16, 17]. The proposed structure utilizes a comparable area as consumed by an Intel processor at the same technology node [41,42,43]. The progress of 3.3% for WSNM has been presented by current research when compared with the Carlson et al.'s results at 22 nm technology [40]. It has been realized that a 6T SRAM cell designed with proposed FinFET shows reduced area and improved stability because of the amalgamation approach of work function engineering (common gate material) and high-k gate dielectric oxide in the FinFET devices.

4 Conclusion

In this paper, the 14 nm gate length FinFET device using lanthanum doped zirconium oxide as high—k gate dielectric material has been proposed to improve SCEs, the leakage performance and SNM for 6 T SRAM cells. The diminished values of SS, IOFF, DIBL and enhanced values of ION & gm are observed after simulating the proposed devices. Further, two SRAM cells based on the improved devices were implemented with different fin configurations. The cell stability metrics such as RSNM and WSNM were evaluated for two types of fin configuration cells using the butterfly method. The SRAM Cell-I has presented better read static noise margin and write static noise margin in comparison to SRAM Cell-II. The Cell-II has almost 50% reduced RSNM and WSNM values at 0.8 V, and it also consumes 14% more area as compared to Cell-I. The effects of supply voltage variation on stability parameters and leakage power were also examined for 6 T SRAM cells. It has been realized that the proposed SRAM circuit has 9% larger RSNM and 3% more WSNM than the circuit designed by Sachid et al. (2008) [44]. The previous work presented the reduced leakage power in the range of 10–15 for designed Cell-I as compared to the later works (10–9). In the current work, the improvement of RSNM is 5x, reduction of WSNM is 2.7%, and declination of the leakage power is in the order of 10–3 when matched with the work done by Saun and Kumar [45].