Keywords

1 Introduction

Memristor, which is the abbreviation of two words “Memory” and “Resistor,” is a nonlinear two terminal element. Memristor theory is initially introduced by Leon Chua in 1971 [1]. Later in 2008, memristor fabrication was successfully carried out by Stanley Williams from the Hewlett-Packard Company using titanium oxide (TiO2) [2]. Before the introduction of memristors, there were three basic passive elements, i.e., resistor, capacitor, and inductor. As such, a linear resistor forms a relation between “voltage” and “current” and the two other fundamental elements capacitor and inductor form the relation between “voltage” and “charge” and “current” and “flux,” respectively. Similarly, the two terminal passive element, memristor, forms the missing relation between “flux” and “charge.” Memristor possesses memristance, which exhibits pinched hysteresis behavior. Memristance depends on the direction of current flow; i.e., when current is allowed to pass in one direction, the memristance increases whereas it decreases once the direction of current is changed. The memristor is a versatile element due to its non-volatile behavior and therefore is used in high-density memory circuits [3] and neuromorphic systems [4]. A memristor can also be employed in various analog and digital applications such as programmable sinusoidal oscillators [5], adaptive filters [6], chaotic circuits [7], logic gates [8], and digital multipliers [9].

Since the commercial viability of physical memristor is complex and expensive, researchers have focused their attention toward emulating the behavior of TiO2 memristor as the reference model. Several research papers have been published on memristor emulator circuits which can be physically implemented [10,11,12,13]. Nevertheless, such emulators lack certain features such as use of more number of passive elements, electronic tunability, pinch hysteresis loop at reasonably lower frequencies, lower power dissipation, etc. This paper proposes a fully integrated memristor emulator circuit which employs the active element as voltage differencing transconductance amplifier (VDTA). The proposed circuit reports desirable memristor features such as tunability, lesser number of passive elements, and lower power consumption.

2 VDTA

The active block used for realizing the memristor emulator circuit is voltage differencing transconductance amplifier (VDTA) [14, 15]. Figures 1 and 2 show block diagram of VDTA and its CMOS technology realized schematic. Basically, the VDTA consists of two operational transconductance amplifiers (OTAs) cascaded together as seen in Fig. 2.

Fig. 1
figure 1

Block diagram of VDTA

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Fig. 2
figure 2

Schematic of CMOS realized VDTA

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The following matrix equation shows the current and voltage relations of VDTA’s input–output terminals:

$$\left[ {\begin{array}{*{20}l} \hfill {i_{p} } \\ \hfill {i_{n} } \\ \hfill {i_{z} } \\ \hfill {i_{x - } } \\ \hfill {i_{x + } } \\ \end{array} } \right] = \left[ {\begin{array}{*{20}l} \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill 0 \\ \hfill {g_{\text{mf}} } & \hfill { - g_{\text{mf}} } & \hfill 0 \\ \hfill 0 & \hfill 0 & \hfill {g_{\text{ms}} } \\ \hfill 0 & \hfill 0 & \hfill { - g_{\text{ms}} } \\ \end{array} } \right]\left[ {\begin{array}{*{20}l} {v_{p} } \\ {v_{n} } \\ {v_{z} } \\ \end{array} } \right].$$
(1)

Here, vp, vn, vz, vx+, vx− and ix+, ix−, iz are potential drops and currents at their respective VDTA ports. Current in p and n ports equals to zero due to very high impedance across them. gmf and gms are effective transconductances of first and second OTAs, respectively, and are given as

$$g_{\text{mf}} = \frac{{g_{{\text{m}1}} g_{{\text{m}2}} }}{{g_{{\text{m}1}} + g_{{\text{m}2}} }} + \frac{{g_{{\text{m}3}} g_{{\text{m}4}} }}{{g_{{\text{m}3}} + g_{{\text{m}4}} }},$$
(2)
$$g_{\text{ms}} = \frac{{g_{{\text{m}5}} g_{{\text{m}6}} }}{{g_{{\text{m}5}} + g_{{\text{m}6}} }} + \frac{{g_{{\text{m}7}} g_{{\text{m}8}} }}{{g_{{\text{m}7}} + g_{{\text{m}8}} }}.$$
(3)

where gm1, gm2,…, gm8 are individual transistor transconductances and can be calculated by using following relation

$$g_{\text{mk}} = \sqrt {2\beta I_{\text{DS}} } ,$$
(4)

where

$$\beta = \frac{{\mu_{k} C_{\text{ox}} }}{2}\left( {\frac{W}{L}} \right).$$
(5)

Here, \(\mu_{k}\) is mobility of kth transistor, Cox is the ratio of oxide permittivity to its thickness, W and L are transistor dimensions, and IDS is drain-to-source current.

3 Memristor Emulator Circuit

The presented memristor emulator circuit introduces the change in resistance by changing the value of applied voltage, vin. The emulator circuit employs one VDTA as active element, two grounded passive elements, i.e., one resistor and one capacitor, an inverting/non-inverting buffer together with an analog multiplier. The configuration is shown in Fig. 3. The presented memristor emulator contains only active elements and grounded passive elements. Nonetheless, the earlier published emulator circuit comprises discrete multiplier circuits, which presents higher complexity, higher power, higher cost, etc. In this paper, the presented design consists of CMOS Gilbert cell-based analog voltage multiplier circuit which is fully integrated and consumes less power [16, 17].

Fig. 3
figure 3

Proposed VDTA-based memristor emulator

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Analyzing the circuit proposed Fig. 3 and using the current and voltage equations from [1], we obtain:

$$i_{z} = g_{\text{mF}} \left( {v_{p} - v_{n} } \right) = \mp g_{\text{mF}} v_{\text{fb}} ,$$
(6)
$$v_{\text{in}} = (i_{\text{in}} + i_{z} )R_{\text{s}} = (i_{\text{in}} \mp g_{\text{mF}} v_{\text{fb}} )R_{\text{s}} .$$
(7)

Using (6) and (7), the current at the x+ terminal is found to be:

$$i_{{x^{ + } }} = g_{\text{mS}} v_{z} = g_{\text{mS}} v_{\text{in}} = g_{\text{mS}} (i_{\text{in}} \mp g_{\text{mF}} v_{\text{fb}} )R_{\text{s}} .$$
(8)

The potential across capacitor C, i.e., vC, is given by the integral of \(i_{{x^{ + } }}\). From (8), vC is given as,

$$v_{\text{C}} = \frac{{g_{\text{mS}} }}{C}\int {v_{\text{in}} \text{d}t} .$$
(9)

The feedback voltage vfb is obtained through CMOS Gilbert cell-based analog voltage multiplier circuit and is given by the multiplication of vC and vin, i.e.,

$$v_{\text{fb}} = v_{\text{C}} v_{\text{in}} = \frac{{g_{\text{mS}} v_{\text{in}} }}{C}\int {v_{\text{in}} \text{d}t} .$$
(10)

Putting (10) in (7), we get

$$i_{\text{in}} = v_{\text{in}} \left[ {\frac{1}{{R_{\text{s}} }} \pm \frac{{g_{\text{mF}} g_{\text{mS}} }}{C}\int {v_{\text{in}} \text{d}t} } \right].$$
(11)

Therefore, the memductance GM is given by,

$$G_{\text{M}} = \frac{1}{{R_{\text{s}} }} \pm \frac{{g_{\text{mF}} g_{\text{mS}} }}{C}\int {v_{\text{in}} } \text{d}t.$$
(12)

From (12), the mathematical model of the presented memristor emulator shows incremental (+)/decremental (−) mode of operations.

4 Simulation Results

The presented emulator circuit has been implemented at CMOS 45-nm technology node using Virtuoso ADE of Cadence. VDD = − VSS; i.e., the power supply is considered as ±0.95 V. The passive component values are selected as RS = 1 KΩ, C = 10 nF. For a sinusoidal input signal (iin) with amplitude of 50 μA, the behavior of characteristic frequency-dependent pinched hysteresis loop of the presented memristor emulator with variations in frequencies, i.e., at f = 500 Hz, f = 1 kHz, f = 5 kHz, and f = 10 kHz is shown in Fig. 4(a)–(d), respectively. The power dissipation of the emulator is calculated to be 3.956 mW.

Fig. 4
figure 4

Characteristic pinched hysteresis loop I–V plot of the presented memristor for sinusoidal input at amplitude 50 μA and frequency a 500 Hz b 1 kHz c 5 kHz and d 10 kHz

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The controllability of bias current (IBIAS) on the transconductance (gm) is used for tuning the memductance presented by the presented memristor emulator. In accordance with (12), the memductance gradually increases/decreases with the increase in bias current. This tunable nature of the proposed memristor emulator circuit is advantageous for integrated circuit applications. Further, the change in memconductance when a train of pulse is applied across the presented memristor emulator circuits showing its incremental and decremental operations is shown in Fig. 5a–b, respectively.

Fig. 5
figure 5

Change in memconductance when a train of pulse is applied across the presented memristor emulator circuits a incremental b decremental memristor

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5 Conclusion

A VDTA-based fully integrated grounded memristor emulator circuit is presented and designed using one VDTA, one four quadrant analog multiplier, two grounded passive elements, i.e., one capacitor, one resistor, and one inverting/non-inverting buffer. The presented emulator has simple circuit topology, fully integrated configuration, and low power consumption. The simulations presented here support the theoretical derivations, thereby making it a robust and versatile emulator. Further, the tunability via varying the bias current overcomes the process mismatches that occur during fabrication.