Energy-efficient switching scheme for SAR ADC with only two reference voltages

Abstract

An energy-efficient switching method for successive approximation register analog to digital converter is presented in this letter. The proposed two-step switching scheme using the goblet architecture achieves 99.52% less switching energy and 21.09% area reduction over the conventional switching scheme. Moreover, owing to the application of the goblet architecture, the proposed scheme employs only two reference voltages without any requirements for stability or accuracy of the third voltage level.

1 Introduction

Successive Approximation Register Analog to Digital Converters are widely used in low-power electronic applications as their energy efficiency. However, the switching energy consumed by the DAC array is considerable during a SAR operating cycle. Thus, many new switching sequences have been presented to reduce the DAC energy. The Vcm-based [1] and monotonic [2] achieve energy reduction by 87.54%, 81.2%, respectively. A novel two advanced energy-back SAR ADC switching scheme proposed by Osipov and Paul [3] achieves an energy reduction more than 99%, however, the horrible reset energy cannot be neglected. The LSB split [4] achieves the same energy saving as the two advanced energy-back scheme with a lower reset energy, and Capacitor-spitting presented by Xie et al. [5] consumed zero reset energy, but both of them applied a third reference voltage. It is worth mentioning that although Wu and Wu [6] has presented an ultra-low voltage switching scheme with only two reference, the total energy is yet not satisfying. The novel schemes [7, 8] have the same problem as the Capacitor-splitting and the two advanced energy-back scheme, respectively. Besides, V-aq based tri-level [10] used Vref/4 to achieve more area reduction. While, The added voltage references will result in uncontrollable power and area consumption. Note that the incremental reference voltage means instability and inaccuracy, which should always be considered.

In this letter, a new switching scheme taking account of both energy-efficiency and the reference voltage requirement is presented. The proposed architecture achieves 99.52% energy reduction over conventional scheme with the two-step method. Applying the goblet architecture, redundant reference voltage has been eliminated. The rest of this paper is organized as follows: the introduction of proposed switching scheme is described in Sect. 2, and the implements and advantages of using tow reference voltages are presented in Sect. 3. Section 4 gives explanation on parasitic capacitance and calculation on gain error. The energy consumption based on the analysis of reset energy is raised in Sect. 5. Section 6 provides the analysis and simulation results about linearity, while Sect. 7 concludes the whole switching scheme.

2 Proposed SAR switching structure

2.1 Proposed architecture

Figure 1 shows the DAC structure of a 10-bit proposed SAR ADC switching scheme. It adopts the two-step architecture that the first (N-M) bits are decided in the first step at “MSBs”, while the rest (M) bits are decided in the second step at “LSBs” with a resolution of N-bits. What’s more, the proposed SAR ADC splits all the capacitors into the goblet structure which achieves better performance than other schemes with only two reference voltage.

Fig. 1

Proposed 10-bit SAR ADC switching scheme (M = 4)

2.2 SAR switching scheme

In Fig. 1, M is set to 4. In the sampling phase, all the switches are turned on (Sp1, Sp2, Sp3, Sn1, Sn2, Sn3), so the differential input signal is sampled onto the top plates of the PMSB (NMSB) capacitor arrays, and the top plates of the PLSB (NLSB) arrays sampled the voltage of Gnd. To both of the P-side and the N-side, the bottom plates of “C_L”(as is shown in Fig. 1) are connected to Gnd, while the bottom plates of “C_R” are connected to Vref. The voltage of “C_bench” which is applied to compensate the binary weighed capacitance array, should be set to Vref, and the voltage of “C_redundancy”, similarly, is supposed to be fixed at Gnd. After sampling, the Sp1 and Sn1 are off. And the whole structure can be simplified into Fig. 2.

Fig. 2

The simplified proposed 10-bit SAR ADC switching scheme during MSBs (M = 4)

Due to the top plates sampling, MSB is decided without any energy dissipation. Considering to give a more specific instruction, an example with M equals 4 is presented in Fig. 3. During the MSB-1 comparison, assume that Vip_N < Vin_N, that is, b_N equals 0, so Vin_N should be pulled down by Vref/2 with all the bottom plates of the capacitors in NMSBs connecting to gnd, which consumes zero energy. Two approaches are compared in Fig. 4 for a better understanding. If C_bench and C_unit are all replaced by the goblet structure and voltages are initialized as 0 and Vref, then Vref/2 shift can be achieved by setting all the Vref to gnd. However, the least shift in the first step should be Vref/32, which indicates that the last two goblets in MSBs (2C, C, C) are wasted. Utilizing C_bench and C_unit, the same voltage shift can be obtained with more area efficiency. In other words, C_bench and C_unit are employed to make up the amount of binary-weighed capacitors, so they don’t participate in the comparison cycles after MSB-1. From the MSB-2 comparison, only the voltages of the PMSBs’ capacitors change, the reference voltages connecting to the bottom plates of capacitors in NMSBs are unchanged. If Vip_(N−1) > Vin_(N−1), the bottom plate of “C_R-max” is pulled to Gnd and b_(N−1) equels 1. Otherwise the bottom plate of “C_L-max” is pulled up to Vref. This process continues until b(N-M) is obtained.

Fig. 3

The proposed SAR ADC switching scheme at MSBs

Fig. 4

Switching method of the DAC array in NMSBs during MSB-1

During the second step, switches Sp2, Sp3, Sn2, and Sn3 are all turned off. Thus, Fig. 1 can be simplified into Fig. 5. Because there is no charge or discharge process on the top plate of “C_unit”, in other words, the C_unit serves as a coupling capacitor which keeps the input signal all the time. Assuming Vip_(N−M−1) > Vin_(N−M−1), then all the top plates of “C_R” in PLSB (shown in Fig. 1) DAC array should be pulled down to Gnd, and b(N-M-1) equals 1, and the voltage of positive terminal of comparator decreases Vref/2^N−M. Since the following comparison, only the voltages of the NLSBs’ capacitors are supposed to be changed, which is similar to MSBs. If Vip_(N−M−2) > Vin_(N−M−2), the corresponding bottom plate of “C_R” is pulled to Gnd and b_(N−M−2) equels 1. Otherwise the bottom plate of “C_L” is pulled up to Vref. This process continues until b₁ is obtained.

Fig. 5

The proposed SAR ADC switching scheme at LSBs

In order to have a better understanding, the waveforms of the proposed SAR switching scheme and the clock signals are provided in Figs. 6 and 7, respectively. Three signals are demonstrate in the Fig. 7, clks, clkc, and RDY. When clks stays in high level, the circuits samples the input signal onto the top plates of the DAC array. After sampling, clkc begins to flow and the DAC array begins to switch. The RDY serves as a reset signal at each end of a comparison cycle.

Fig. 6

Waveform of the comparator inputs

Fig. 7

Timing waveforms of the clock signals for the SAR ADC operation

In the N-bit proposed SAR ADC switching architecture, the LSB size is Vref/2^N−1. Considering the charge redistribution of the goblet structure, the sum of PLSBs (or NLSBs) should be 2^N−2. Noting that the equivalent capacitance of the goblet architecture can be calculated from series and parallel connection as:

$$ C_{eq} (i) = \frac{{(C_{L} (i) + C_{R} (i))*C_{M} (i)}}{{C_{L} (i) + C_{R} (i) + C_{M} (i)}} $$

(1)

The value of C_redundancy is given as ($2^{N - 2} - \sum\nolimits_{i = 0}^{M - 1} {C_{eq} (i)}$)*C), with M equaling to 4.

3 The number of reference voltages analysis

3.1 The goblet architecture for two reference voltages switching scheme

In a typical switching scheme with two reference voltages (as VDD and GND), if a normal capacitor has been charged into Vref, it cannot be pulled up to a higher level, thus an extra voltage as V_cm is necessary to compromise this effect. While, applying the goblet architecture can solve the problem without using extra reference voltage. In a goblet architecture, “C_L” has the same value as “C_R”, and the value of “C_M” equals to the sum of “C_L” and “C_R” as shown in Fig. 8. During the sampling phase, the bottom plate of C_R is set to Vref and the bottom plate of C_L is set to gnd, thus the whole goblet architecture can be both pulled up and down. As a result, an extra reference voltage can be saved.

Fig. 8

Goblet architecture capacitor

3.2 The relationship analysis between reference voltage number and DAC performance

3.2.1 Linearity

The influence of introducing an extra reference voltage has been analyzed in [3]. For example, according to Osipov’s 50000 Monto-Carlo runs [3], if the adding voltage V_cm has 1% offset, the maximum DNL error rises 4 × times and maximum INL for 20x times. Therefore, the more reference voltages applied in the switching scheme the worse linearity will be obtained. However, most high power efficiency papers published recently didn’t take the influence of multi-reference voltages on linearity into account.

3.2.2 Power consumption

For the proposed goblet architecture, it can be calculated that both charge and discharge processes among DAC_ups consume zero energy because of the closed-loop charge recycling [9], thus the power terminal only needs to charge the bottom plate of C_M. As C_L is set from gnd to Vref (or C_R is set from Vref to gnd), the bottom plate of C_M only changes Vref/2, which provides more energy saving.

3.2.3 Logic complexity

Note that the operation states “on” and “off” of the two reference voltages (Vref, 0) can be easily achieved by a nand gate cell. However, if V_cm applied, more transistors are required to obtain the corresponding logic control. Which means more logic complexity and chip area. Therefore, the logic complexity of proposed switching scheme will be relieved.

4 Analysis of parasitic capacitances

In the proposed scheme, the parasitic capacitances cannot be ignored because of the series connection. Besides, there are supposed to be two different gain errors at the input terminal due to the utilization of the two step method. Figure 9 presents the parasitic capacitance in p-side in MSBs while Fig. 10 illustrates the parasitic capacitances in p-side during the second step, respectively. C_p1, C_p2 present the parasitic capacitances on the top plates of MSBs and LSBs, respectively. And the C_p3, C_p4 present parasitic capacitances on the top plates and bottom plates of the unit capacitor. If setting the C_L-1 from 0 to Vref, the voltage change in Ap should be (2).

Fig. 9

Parasitic capacitances in MSBs

Fig. 10

Parasitic capacitances in LSBs

$$ V_{ip2} - V_{ip1} = \frac{{C_{L - 1} Vref}}{{C_{L - 1} + C_{R - 1} }}*\frac{{C_{1} }}{{C_{1} + C_{2} + C_{3} }}*\frac{{C_{L - 1} + C_{R - 1} }}{{C_{L - 1} + C_{R - 1} + C_{pr1} }}*\frac{{C_{1} + C_{2} + C_{3} }}{{C_{1} + C_{2} + C_{3} + C_{p1} }} $$

(2)

From (2), we can find the Gain error in the first step as

$$ Gain1 = \frac{{C_{1} + C_{2} + C_{3} }}{{C_{1} + C_{2} + C_{3} + C_{p1} }}*\frac{{C_{L - 1} + C_{R - 1} }}{{C_{L - 1} + C_{R - 1} + C_{pr1} }} $$

Similarly, when the voltage of C_L-5 flows from 0 to Vref, the voltage change in Bp can be obtained as:

$$ V_{Bp2} - V_{Bp1} = \frac{{C_{L - 5} (Vref - 0)}}{{C_{L - 5} + C_{R - 5} }}*\frac{{C_{5} }}{{C_{5} + C_{6} }}*\left( {\frac{{C_{5} + C_{6} }}{{C_{5} }}*\frac{{C_{5}^{{\prime }} }}{{C_{5}^{{\prime }} + C_{6}^{{\prime }} + C_{eq} + C_{p4} }}*\frac{{C_{L - 5} + C_{R - 5} }}{{C_{L - 5} + C_{R - 5} + C_{pr2} }}} \right) $$

(3)

The Gain error in second step can be acquired from (3) as

$$ Gain2 = \frac{{C_{5} + C_{6} }}{{C_{5} }}*\frac{{C_{5}^{{\prime }} }}{{C_{5}^{{\prime }} + C_{6}^{{\prime }} + C_{eq} + C_{p4} }}*\frac{{C_{L - 5} + C_{R - 5} }}{{C_{L - 5} + C_{R - 5} + C_{pr2} }}*\frac{{C_{\_unit} }}{{C_{\_unit} + C_{p2} }} $$

(4)

If the value of parasitic capacitances on the top plates is linear to the total value of DAC arrays, defaulting the ratio as γ, we can get

$C_{p1} = \gamma (C_{1} + C_{2} + C_{3} )$, $C_{p4} = \gamma (C_{5} + C_{6} )$, $C_{p2} = \gamma C_{\_unit}$, $C_{pr1} = \gamma (C_{L - 1} + C_{R - 1} )$, $C_{pr2} = \gamma (C_{L - 5} + C_{R - 5} )$, $C_{pr3} = \gamma (C_{L - 6} + C_{R - 6} )$

The final expression of Gain1 and Gain2 after simplification is:

$$ Gain1 = \frac{{C_{1} + C_{2} + C_{3} }}{{C_{1} + C_{2} + C_{3} + \gamma (C_{1} + C_{2} + C_{3} )}}*\frac{{C_{L - 1} + C_{R - 1} }}{{C_{L - 1} + C_{R - 1} + \gamma (C_{L - 1} + C_{R - 1} )}} = \frac{1}{{(1 + \gamma )^{2} }} $$

(5)

$$ Gain2 \approx \frac{{C_{5} + C_{6} }}{{C_{5} }}*\frac{{(2\gamma + 1)C_{5} }}{{(C_{5} + C_{6} )(2\gamma + 1) + (\gamma + 1)\gamma (C_{5} + C_{6} )}}*\frac{C\_unit}{C\_unit + \gamma C\_unit}*\frac{{C_{L - 5} + C_{R - 5} }}{{C_{L - 5} + C_{R - 5} + \gamma (C_{L - 5} + C_{R - 5} )}} $$

(6)

In (6), note that

$$ C_{eq} = \frac{{C_{\_unit} C_{p2} }}{{C_{\_unit} + C_{p2} }} + C_{p3} < C_{\_unit} + C_{p3} < < C_{5} + C_{6} $$

Thus

$$ Gain2 \approx \frac{2\gamma + 1}{{\gamma^{2} + 3\gamma + 1}}*\frac{1}{{(1 + \gamma )^{2} }} $$

The analysis shows that owing to the parasitic capacitances, there will be two different Gain errors in the MSBs’ and LSBs’ bits cycle. Usually, the value of γ floats from 0.01 to 0.03 according to different process bias. Table 1 shows the value of Gain errors against γ. Note that the input signal has no error when Gain equals 1, it can be observed that both Gain1 and Gain2 have minimal impact on the accuracy of inputs when γ less than 0.018.

Table 1 Gain error against γ

5 Energy analysis

5.1 Reset energy

Recently published papers such as Osipov and Paul [3] and Baek and Lee [8] have been proved to have good performance in energy saving. However, power terminal still needs to charge the bottom plates of the DAC array when a complete comparison cycle finished which [3, 8] didn’t mention.

From Table 2, which presents principal characteristics of different switching schemes, we can find that the average switching energy of the proposed scheme for a 10-bit SAR ADC is 6.573Cvref², less than [1,2,3,4,5,6]. While if reset energy being considered, Xie et al. [5] and two-step [7] seem to perform better with zero reset energy, but the dissipation consumed by the circuits which generate the third voltage must be taken into account. Figure 11 shows the energy consumption without reset energy of different schemes against output code.

Table 2 Principal characteristics of different switching schemes

Fig. 11

Switching energy against output code

5.2 Optimal value of M

In order to find the optimal value of M, the behaviour simulation of different switching architecture for a 10-bits SAR ADC has been performed. Table 3 shows the different characteristics of proposed scheme about its cap-area, linearity, and switching energy. It can be observed that when M > 5, the linearity tends to be unstable, which will lead to errors such as code missing, Below 6, choosing M = 3 can get a modifying in linearity, but the capacitor area and the total energy consumption are undesirable. Thus, M is chosen to 4 with the lowest energy consumption, an acceptable linearity and relatively small area for capacitor.

Table 3 Principal characteristics of proposed switching scheme with M 3 ~ 7

6 Linearity

It is always the capacitors mismatch that determinate the minimum value of the unit capacitance. Assume that the unit capacitor takes a nominal value of Cu with standard deviation of σu which equals 0.01(σu(ΔC/C) = 0.01). Since the proposed switching scheme adopts the goblet architecture, the linearity of the SAR ADC can get a modicum of improvement. Provided a unit capacitor with a nominal value C and an error of ΔC, after using goblet structure (Fig. 12), the error of the unit capacitor can be described as:

Fig. 12

Mismatch of the goblet structure

$$ C_{C - 2C\_error} = \frac{(C + \Delta C + C + \Delta C)*(2C + \sqrt 2 \Delta C)}{(C + \Delta C + C + \Delta C + 2C + \sqrt 2 \Delta C)} - C = \frac{{(2 + \sqrt 2 )C\Delta C + 2\sqrt 2 \Delta C^{2} }}{4C + (2 + \sqrt 2 )\Delta C} $$

(7)

Because ΔC ≪ C, the the ΔC² in the formula can be neglected, then divide both top and bottom with C, we can get C_{goblet_error} ≈ (2 + √2)ΔC/4, which is lower than ΔC. The simulation results of 500 Monte Carlo runs of 10-bit SAR ADC with the proposed switching scheme is shown in Fig. 13.

Fig. 13

Linearity simulation result of proposed scheme

7 Conclusion

In this letter, an energy-efficient switching scheme with two reference voltages has been presented. Splitting all the capacitors into the goblet structure and reusing of the unit capacitor, the proposed switching scheme achieves an energy saving by 99.52% at 10-bit level. Even considering the reset energy, the proposed scheme performs better than recently published schemes. Simultaneously, the goblet structure also allows to benefit from using only two reference voltage which significantly reduces power and dependence on the requirements for stability or accuracy of the third voltage. In summary, the proposed scheme achieves a trade-off between energy-saving and the quantity of reference voltages.