1 Introduction

Reversible logic has attracted significant attention in circuit design. Reversible logic circuits are used because they do not waste energy. Irreversible logic circuits waste energy because of data loss. In 1961, Landauer proved that the loss of one bit of information results in KTLn2 joules of energy wastage in irreversible logical circuits, where K is Boltzmann’s constant [15]. In reversible circuits, this energy is not wasted, as proven by Bennet [2], and the number of inputs and outputs is equal. In addition, a one-to-one correspondence exists between the inputs and output. The input vector (Iv) represents the inputs of a reversible logic circuit, and the output vector (Ov) denotes the output of that circuit [27]. Equation (1) shows the Iv and Ov vectors.

$$ \begin{aligned} I_{\text{v}} \, & = \, \left( {I_{1} , \, I_{2} , \, I_{3} , \, \ldots , \, I_{n} } \right) \\ O_{\text{v}} \, & = \, \left( {O_{1} , \, O_{2} , \, O_{3} , \, \ldots , \, O_{n} } \right) \\ \end{aligned} $$
(1)

Using parity-preserving reversible blocks and gates is essential for a parity-preserving reversible circuit. A gate or block is considered as parity preserving when a balance is available between its inputs and outputs [7, 10, 19, 23, 27, 30, 31, 35].

Multiplication is considered as a popular arithmetic operation. In reversible logic, the design of unsigned and signed multipliers has been reviewed, some of which were parity preserving [3, 4, 8,9,10, 12,13,14, 18, 20, 28, 29, 31, 32, 35, 36].

We present a 4 × 4 parity-preserving reversible unsigned multiplier circuit. It has been proved that the best result can be obtained in terms of the number of CONSTANT INPUTs, number of GARBAGE OUTPUTs, and QUANTUM COST. Furthermore, we present a 5 × 5 parity-preserving reversible signed multiplier, unsigned multiplier circuits, as well as signed N × N ones.

The remainder of this paper is organized as follows. Section 2 presents some basic concepts of reversible logic. Section 3 describes previous studies. The proposed circuits are presented in Sect. 4. The evaluation and comparison results are demonstrated in Sect. 5. The conclusion is presented in Sect. 6.

2 Basic Concepts

In this section, the basic concepts of reversible logic are defined. Subsequently, a few reversible logic parity-preserving gates are analyzed. Finally, multiplier circuits are explained.

2.1 Reversible Logic

A gate is reversible if a one-to-one correspondence exists between the inputs and outputs values. To evaluate the efficiency of a reversible circuit, a few parameters can be used as benchmarks, including the CONSTANT INPUT, which involves a fixed value (of 0 or 1) [17], GARBAGE OUTPUT (useless output) [33], and QUANTUM COST (the sum of 2*2 reversible gates). Circuits larger than 2 × 2 should be converted to several 2 × 2 or 1 × 1 smaller circuits. The total QUANTUM COST of 2 × 2 circuits yields the QUANTUM COST of the larger circuits. In reversible logic, two quantum gates exist, i.e., V and V+. Another name for V is square root. Equation (2) is related to V and V+ gates [22].

$$ \begin{aligned} & V \times V = \, V^{ + } \times V^{ + } = {\text{ NOT}} \\ & V \times V^{ + } = \, I \\ \end{aligned} $$
(2)

2.2 Reversible Gates

The Feynman [5], Toffoli [34], and Peres gates [25] are examples of nonparity-preserving gates. Many reversible parity-preserving gates exist, including the Feynman double gate (F2G) [33], new fault tolerant (NFT) gate [5], and FRG [6].

The F2G is regarded as a reversible parity-preserving gate with three inputs and three outputs, as shown in Eq. (3)

$$ \begin{aligned} & I_{\text{v}} = (A,B,C) \\ & O_{\text{v}} = (P = A,Q = A \oplus B,R = A \oplus C) \\ \end{aligned}. $$
(3)

In Eq. (3), Iv and Ov are the F2G inputs and outputs, respectively. Figure 1 shows the F2G gate in the quantum structure. The F2G gate is used to produce a Fan-OUT in reversible parity-preserving circuits. The QUANTUM COST of the F2G gate is 2.

Fig. 1
figure 1

Parity-preserving reversible F2G gate

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The NFT gate is another reversible gate that includes three inputs and three outputs, which is a parity-preserving gate. The inputs and outputs of this gate are shown in Eq. (4)

$$ \begin{aligned} & I_{\text{v}} = (A,B,C) \\ & O_{\text{v}} = (P = A \oplus B,Q = B^{\prime}C \oplus AC^{\prime},R = BC \oplus AC^{\prime}) \\ \end{aligned}. $$
(4)

Figure 2 displays the NFT gate with a QUANTUM COST of 5.

Fig. 2
figure 2

Parity-preserving reversible NFT gate

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3 Related Studies

In this section, explanations are provided for the multiplication operation and analysis of reversible unsigned and signed multiplier circuits.

3.1 Irreversible Multiplier

Multipliers can be categorized into unsigned and signed groups from one viewpoint. Furthermore, multiplication circuits can be categorized into serial and array structures. Hitherto, many serial and array multiplier circuits have been presented. The serial multiplication operation can be performed using a shift to the left or right. Several methods can be used in array multiplier operations including the Dadda and Wallace tree. Multiplying operations in the array method are performed in two sections, including partial product generation and partial product addition [24]. Figure 3 illustrates the operation of an unsigned multiplication.

Fig. 3
figure 3

Unsigned multiply operation of two 4-bit numbers

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3.2 Parity-Preserving Reversible Multiplier

Thapliyal et al. [32] developed a nonparity-preserving reversible unsigned multiplier circuit using the TSG gate. In [8], Haghparast et al. presented a reversible unsigned multiplier circuit based on Peres gate (PG), Toffoli gate (TG), and HNG gates. In addition, Moghadam et al. formed a reversible multiplier circuit using PG and TG gates [18]. Furthermore, Jigalur et al. presented a reversible 4 × 4 unsigned multiplier circuit using PG and HNG gates [12].

In another study, a parity-preserving unsigned reversible multiplier circuit was designed [11]. Valinataj presented two parity-preserving reversible unsigned multiplier circuits [35].

Additionally, Qi et al. [31] presented a parity-preserving reversible signed multiplier circuit and Valinataj a parity-preserving reversible signed multiplier circuit [35].

Having a minimum GARBAGE OUTPUT is considered as one of the targets [1, 16, 21, 26]. These circuits reuse fixed inputs to reduce the number of circuit lines and redundant outputs. The study by [21] is regarded as the best study performed in terms of T-count, qubits, and CONSTANT INPUTs. Meanwhile, regarding the circuit design method presented in [1, 16, 21, 26], the QUANTUM COST of the circuit increased owing to the redundancy of the gates required to convert CONSTANT INPUTs to their original values. These circuits require a low number of CONSTANT INPUTs and yield a small number of GARBAGE OUTPUTs; however, they incur a high QUANTUM COST. Therefore, the QUANTUM COST and the number of CONSTANT INPUTs are inversely correlated. In fact, the QUANTUM COST increases when the number of circuit lines is decreased.

The abovementioned methods can be used when the importance of the QUANTUM COST is low [21]. Otherwise, the proposed designs can be used as the best designs to date.

4 The Proposed Parity-Preserving Reversible Multipliers

In the present study, four parity-preserving reversible multiplier circuits are presented. The first and second designs are parity-preserving reversible unsigned circuits. In the third and fourth plans, two parity-preserving reversible signed circuits are proposed.

4.1 First Block

The first proposed block is a parity-preserving circuit with four inputs and four outputs. Figure 4 illustrates the first block in the quantum structure, denoted E1. If C and D are 0, then AB appears in the R and S outputs. Furthermore, it is used as a Fan-OUT. The QUANTUM COST of the proposed block E1 is 6.

Fig. 4
figure 4

The first proposed parity-preserving reversible block (E1)

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4.2 Second Block

The second block comprises a parity-preserving circuit with five inputs and five outputs. Figure 5 shows the second block, denoted E2. If the D and E inputs are 0, then sum and carry values exist in the S and R outputs, respectively. The QUANTUM COST of the E2 block is 8.

Fig. 5
figure 5

The second proposed parity-preserving reversible block (E2)

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4.3 Third Block

The third block is a parity-preserving reversible circuit with five inputs and five outputs. The third block design provides a parity-preserving block for the synchronous part of the output functions of a 2 × 2 multiplication circuit. In designing the third block, we attempted to reduce the QUANTUM COST as much as possible. Figure 6 shows the third block in the quantum structure, denoted E3. The QUANTUM COST of E3 is 8.

Fig. 6
figure 6

The third proposed parity-preserving reversible block (E3)

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4.4 Parity-Preserving Reversible 4 × 4 Unsigned Multiplier

The reversible unsigned multiplier operation was categorized into two parts. First, the partial product generation (PPG) operation was performed, which generated AND results for multiplier operations. In the second section of the circuit, a partial product addition (PPA) circuit was used.

In the PPG section, 16 AND functions are required. These functions were developed using NFT gates and E1 blocks. Figure 7 illustrates the PPG circuit.

Fig. 7
figure 7figure 7

Partial product generation circuit in parity-preserving reversible unsigned 4 × 4 multiplier circuit

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The PPG design of the reversible unsigned multiplier circuit requires seven NFT gates and nine E1 blocks.

A significant improvement was achieved by separating the multiplier circuit into two sections. The first section of this design includes 2 × 2 multiplier circuits, and the second section encompasses the remaining multiplication parts.

In this circuit, an optimal parity-preserving circuit is presented using QUANTUM COST optimization blocks. Figure 8 shows the proposed PPA circuit in the reversible unsigned circuit.

Fig. 8
figure 8figure 8

Partial product addition circuit in the proposed parity-preserving reversible unsigned 4 × 4 multiplier circuit

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Four HAs and eight FAs are necessary for designing a PPA circuit in a reversible 4 × 4 unsigned multiplier circuit. In the suggested PPA circuit (Fig. 8), E2 blocks were used to generate a full adder. The results obtained in the PPG section should be considered in PPA computations. Hence, the E1(A), E1(B), E3(A), and E3(B) blocks and two other E1 blocks contribute to the final results of the 2 × 2 multiplier.

4.5 Parity-Preserving Reversible N × N Unsigned Multiplier

Designing a circuit in variable sizes is necessary for designing a 4 × 4 reversible unsigned multiplier circuit. Similar to the previous design, it contains two PPG and PPA sections. In this design, NFT gates and E1 blocks were used to for PPG. Figure 9 illustrates the PPG in an N × N unsigned parity-preserving reversible multiplier circuit.

Fig. 9
figure 9

Parity-preserving reversible unsigned N × N partial product generation circuit

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No additional gate or block is necessary for implementing half adders.

In this circuit, N blocks of HA and N × (N − 2) FA blocks are required. We used the E3 block in PPA to complete the results of PPG. The E2 block was used to create the FA function in an N × N design. Figure 10 displays the PPA generator circuit in N × N dimensions for producing a parity-preserving unsigned reversible multiplier circuit.

Fig. 10
figure 10

Parity-preserving reversible unsigned N × N partial product addition circuit

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As shown in Fig. 10, the E2 and E3 blocks were used to generate the PPA circuit.

The sum of QUANTUM COST of the PPA and PPG is illustrated in Eq. (5)

$$ {\text{QC}} = 14\left( {N^{2} - N} \right) + 1. $$
(5)

Equation (6) indicates the QUANTUM COST of the circuit with respect to N

$$ {\text{No}} .\;{\text{CI}} = 4N^{2} - 5N + 1. $$
(6)

Equation (7) represents the number of GARBAGE OUTPUTs.

$$ {\text{No}} .\;{\text{GO}} = 4N^{2} - 5N + 1 $$
(7)

4.6 Parity-Preserving Reversible 5 × 5 Signed Multiplier

In this section, a 5 × 5 parity-preserving signed reversible multiplier circuit is proposed; 17 ANDs and eight NANDs are required. We used E1 blocks and NFT gates to obtain PPG outputs. Because the NFT gate incurs less QUANTUM COST than block E1, NFT gates are preferable for the production of required ANDs and NANDs. Figure 11 illustrates the parity-preserving signed reversible multiplier PPG circuit.

Fig. 11
figure 11figure 11

Parity-preserving reversible signed 5 × 5 partial product generation circuit

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As shown in Fig. 11, seven NFT gates and 18 E1 blocks are required. One of the inputs must be set to logical 1 to obtain a NAND gate.

As illustrated in Fig. 12, two E3 blocks and 16 E2 blocks are required; the E3 blocks were used to complete the function of a 2 × 2 multiplier.

Fig. 12
figure 12figure 12

Parity-preserving reversible signed 5 × 5 partial product addition circuit

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4.7 Parity-Preserving Reversible N × N Signed Multiplier

An N × N parity-preserving reversible signed multiplier circuit is presented. Figure 13 illustrates the PPG circuit in the parity-preserving reversible signed N × N multiplier circuit.

Fig. 13
figure 13

Parity-preserving reversible signed N × N partial product generation circuit

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In the N × N PPG circuit, the number of E1 blocks is (N − 1)2 + 2 and the number of NFT gates is 2 N − 3.

Figure 14 shows the N × N parity-preserving reversible signed multiplier circuit.

Fig. 14
figure 14

Parity-preserving reversible signed N × N partial product addition circuit

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As shown in Fig. 14, the number of E2 blocks for an N × N multiplication is (N − 1)2. Combining the circuits in Figs. 13 and 14 produces the multiplication of the parity-preserving reversible signed N × N numbers.

The QUANTUM COST of the signed multiplier circuit is shown in Eq. (8)

$$ Q_{\text{c}} = 14N^{2} - 18N + 13 + 8 *\frac{N}{2}. $$
(8)

Equation (9) displays the number of CONSTANT INPUTs

$$ {\text{NO}} .\;{\text{CI}} = 4N^{2} - 6N + 8 + 2*\frac{N}{2}. $$
(9)

Equation (10) represents the number of GARBAGE OUTPUTs.

$$ {\text{NO}} .\;{\text{GO}} = 4N^{2} - 6N + 8 + 2 *\frac{N}{2} $$
(10)

5 Evaluation of the Proposed Reversible Multiplier Circuit

In this section, the proposed parity-preserving 4 × 4 and N × N reversible unsigned multiplier circuits are analyzed. Subsequently, the parity-preserving 5 × 5 and N × N reversible signed multiplier circuits are evaluated.

Table 1 shows a comparison between this parity-preserving reversible unsigned multiplier circuit and those of previous studies.

Table 1 Comparison of different parity-preserving reversible 4 × 4 unsigned multipliers
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As shown in Table 1, this parity-preserving 4 × 4 reversible unsigned multiplier circuit contains 45 CONSTANT INPUTs and 45 GARBAGE OUTPUTs; its QUANTUM COST is 169. This circuit is considerably better than those of previous studies in terms of the number of CONSTANT INPUTs, number of GARBAGE OUTPUTs, and QUANTUM COST.

Considering all the evaluation criteria, the 4 × 4 parity-preserving reversible unsigned multiplier circuit exhibited the best result compared with those of previous studies.

Table 2 shows a comparison between our N × N reversible unsigned multiplier circuit and those of previous studies.

Table 2 Comparison of different parity-preserving reversible N × N unsigned multipliers
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As shown in Table 2, the efficiency increased in three criteria related to the number of CONSTANT INPUTs, number of GARBAGE OUTPUTs, and QUANTUM COST.

Table 3 shows a comparison between the performances of the 5 × 5 signed multiplier circuit and state-of-the-art signed multiplier circuits.

Table 3 Comparison of different parity-preserving reversible 5 × 5 signed multipliers
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As shown, the 5 × 5 reversible signed multiplier circuit demonstrated the best result compared with those in previous studies.

Table 4 shows the results compared with those in [8].

Table 4 Comparison of different parity-preserving reversible N × N signed multipliers
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The results indicated improvements in terms of the QUANTUM COST and numbers of CONSTANT INPUTs and GARBAGE OUTPUTs compared with those in [35].

6 Conclusion

We herein presented parity-preserving reversible multiplier circuits. First, three parity-preserving reversible blocks were presented and a parity-preserving reversible 4 × 4 unsigned multiplier circuit was designed using these blocks. Based on the results, the proposed circuit demonstrated the best performance compared with those of previous studies. In addition, an N × N reversible unsigned multiplier circuit was proposed, along with relevant equations for computing the circuit costs. Regarding the number of CONSTANT INPUTs and GARBAGE OUTPUTs, the unsigned multiplier circuit demonstrated better results compared with those of previous studies. Furthermore, a parity-preserving reversible 5 × 5 signed multiplier was presented, along with an N × N parity-preserving one. The results proved that our circuit demonstrated the best efficiency. The performance evaluation of these designs indicated a significant improvement in terms of the QUANTUM COST and the numbers of CONSTANT INPUTs and GARBAGE OUTPUTs compared with previous studies.