Abstract
This paper presents an overview of sizing tasks in electronic circuit design and their corresponding formulations as optimization problems. We will start with the general multi-objective sizing problem. Then, the inclusion of statistically distributed parameters and of range-valued parameters into the scalar problems of yield optimization and design centering will be described. Finally, a problem formulation for considering these parameter tolerances by multi-objective Pareto optimization will be presented.
Access provided by Autonomous University of Puebla. Download to read the full chapter text
Chapter PDF
Similar content being viewed by others
References
Graeb, H.: Analog Design Centering and Sizing. Springer, Berlin (2007)
Massier, T., Graeb, H., Schlichtmann, U.: The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. Computer-Aided Des. Integr. Circ. Sys. 27(12), 2209–2222 (2008)
MunEDA: WiCkeD (2009). Www.muneda.com
Nagel, L.: SPICE2: A computer program to simulate semiconductor circuits. Ph.D. Dissertation, University of California, Berkeley (1975)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Gräb, H. (2012). From Sizing over Design Centering and Pareto Optimization to Tolerance Pareto Optimization of Electronic Circuits. In: Michielsen, B., Poirier, JR. (eds) Scientific Computing in Electrical Engineering SCEE 2010. Mathematics in Industry(), vol 16. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22453-9_4
Download citation
DOI: https://doi.org/10.1007/978-3-642-22453-9_4
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-22452-2
Online ISBN: 978-3-642-22453-9
eBook Packages: Mathematics and StatisticsMathematics and Statistics (R0)