Abstract
With technology scaling, the device characteristics fluctuate to a large extent due to process variations and can cause significant variations in wire delay (Wang and McNall, IEEE Workshop on Microelectronics and Electron Devices, pp. 64–66, 2004). Wire delay is also affected by other forms of interference such as supply bounce, transmission line effects, etc. (Chen et al., Proc. DAC, pp. 860–865, June 2002; Restle et al., IEEE Journal of Solid-State Circuits 33(4):662–665, 1998). As such delay variations can affect multiple bits simultaneously, special mechanisms are needed to handle timing errors. In this chapter, we present T-error, a timing-error tolerant mechanism to make the interconnect resilient against timing errors arising due to such delay variations on wires.
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© 2009 Springer Science + Business Media B.V.
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Murali, S. (2009). Timing-Error Tolerant NoC Design. In: Designing Reliable and Efficient Networks on Chips. Lecture Notes in Electrical Engineering, vol 34. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-9757-7_8
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DOI: https://doi.org/10.1007/978-1-4020-9757-7_8
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-9756-0
Online ISBN: 978-1-4020-9757-7
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