1 Introduction

Due to the recent significant increase in portable digital devices, which require high-efficiency processing in confined silicon areas, the design of integrated circuits (ICs) with optimum performance characteristics has become critical (Yousefi et al. 2022; Gulafshan et al. 2022). Low operating frequency and low supply voltage are two methods for lowering IC power consumption. However, regularly lowering the supply voltage causes the driver current to drop and the circuit delay to rise (Hasan et al. 2021a). Therefore, using efficient circuit design techniques is crucial for improving the performance of digital circuits. In order to improve the performance of modern digital circuits, researchers have recently demonstrated much interest in energy-efficient design techniques with optimal speeds (Chu 2290).

Most processors and complex gate arrays use the adder as a fundamental element. Furthermore, the addition operation will occupy all the fundamental arithmetic operations. The analytical modeling of all the digital blocks relies on adder modules. Complex addition operations are developed with the help of the fundamental 1-bit adder module. The overall block performance depends on the individually developed core 1-bit adder module, which, intern results in the overall application’s physical significance.

This article mainly focuses on the combination of conventional CMOS and GDI techniques. The full adder key metrics contrasted with ten (10) other cutting-edge FAs to support it. The proposed full adders are optimized to a maximum of 32 bits incorporating a non-CLS approach for performance measurement in more extensive systems. Compared to FA cells currently in use, the proposed FA cell performed superbly (Bhattacharjee et al. 2021; Véstias et al. 2022; Kumar et al. 2021; Maleki et al. 2021).

2 Full adders design using FinFET nodes

The compact applications of the digital blocks are merely realized with the help of individual full adder modules. FA is divided into single logic and hybrid logic depending on the logic design method. The Complementary Path Transistor Logic (CPL) FA is said to be the earliest FA design (Roy et al. 2022).

The problem of voltage degradation severely hinders the use of CPLs in modern electrical circuits. Because of the primary advantages of the conventional CCMOS, most of the applications are being developed with the help of this technique. High power consumption, many transistors, and excessive input impedance are still issues. The CPL and CCMOS methodologies use one full adder style and topology for realization (Mak 2022; Sardroudi et al. 2021; Velammal et al. 2021; Rafiee et al. 2021; Seyedi and Jafari Navimipour 2022; Fatemieh et al. 2021; Krishnaveni, et al. 2021; Soe et al. 2021).

Recently, hybrid FA designs have attracted attention. Hybrid FA improves performance using many logic strategies within the same circuit (Sardroudi et al. 2021). FAs mentioned in Ultra-Low ​​Power FA (ULPFA) (Velammal et al. 2021), Low-Power High Speed ​​(LPHS) FA (Rafiee et al. 2021), and (Seyedi and Jafari Navimipour 2022; Fatemieh et al. 2021; Krishnaveni et al. 2021; Soe et al. 2021) are included in the hybrid domain. ULPFA uses Branch Based Logic (BBL) and Path Transistor Logic (PTL) to implement FA (Velammal et al. 2021). Stable and robust drive capability of the carry generation circuit. However, the summing circuit has no driving power. The same is true for Mirzaee et al. (Fatemieh et al. 2021). The LPHSFA of Rafiee et al. (2021) has a very low TC, making it suitable for applications requiring a small footprint and low power consumption (15 transistors). The LPHSFA of Rafiee et al. (2021) has a very low TC (15 transistors) and is suitable for systems that require a small area and low power consumption. The pass-transistor and transmission gate logic has been adopted in Soe et al. (2021). The issue of voltage degradation in CPL is minimized with the proposed design, whereas the driving capability enhancement is still a primary requirement. The design (Velammal et al. 2021) used three various levels of signal enhancements (Dhariwal et al. 2022; Raj et al. 2022; Naghizade and Saghaei 2021; Zareei et al. 2021; Hasan et al. 2021b; Arunkumar et al. 2022; Ravula et al. 2022; Mahmoud et al. 2021).

The full adder properties of the designs given in the literature of Chu (2290); Bhattacharjee et al. 2021; Véstias et al. 2022; Kumar et al. 2021) are much more similar. Using GDI technology, Shoba et al. (Soe et al. 2021) presented three different FA designs. These FAs have modified his GDI gates that allow the full-scale operation to address the voltage sag problem. By using fewer transistors, GDI technology also enables the creation of energy-efficient logic gates. The GDI method has a severe stress degradation flaw preventing widespread adoption. The design (Kumar et al. 2021) can be made with a minimum of 14 transistor counts, but this design has the limitation of a threshold level of voltage is a significant issue.

3 Proposed full adder design

Besides the limitations of the GDI technique, the methodology offers high demand for power efficiency and increased speed of designs. This article presented a hybrid and advanced to that conventional technique, which is achieved with the CCMOS and GDI. To reduce TC, this work uses logic gates with GDI-based inputs. The required power rails are fed from VDD and the Gnd, respectively, from the CCMOS logic, which removes the limitation of the GDI methodology. The proposed FA modeling and critical specifications are presented in the following subsection.

3.1 Proposed adder cell logical modeling

The logical nature of the adder modules should be modeled first before its realization. Table 1 shows the FA truth table, which shows the FA adheres to the following requirements:

Table 1 The truth table of the full adder operation
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From this, it can be confirmed that the Sum is being generated from XOR–XNOR where, whereas Cout is developed with AND–OR logic.

3.2 Testbench setup

The testbench setup for the proposed models is given below in Figs. 1, 2. Using XNOR–XOR and NAND–NOR, the required adder blocks are realized in contrast to that of XOR–XNOR and AND–OR gates. GDI-based 2:1 multiplexers (MUX), NAND–NOR, and XNOR–XOR are cascaded to route the desired signal to the output port, depending on Cin. Cout and Sum are the outputs of the GDI-based network (the complement of Cout and Sum). In the final phase, the signal sent by the GDI network is used by the CCMOS inverter to generate Cout and Sum.

Fig. 1
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Full adder given in (Mak 2022)

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Fig. 2
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Full adder given in (Velammal et al. 2021)

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3.3 XNOR–XOR and NAND–NOR gate design using GDI

From the literature, the GDI method has been taken to implement the standard multiplexers with the help of conventional AND–OR logic. Figures 3, 4, 5, 6, 7, 8, 9, 10 shows the layout of a simple GDI cell. The P-channel CMOS (P-MOS) and N-channel CMOS source and drain terminals of the primary GDI cell are the same as the source and drain terminals of a CCMOS-based NOT gate, but the signal sent to these terminals works differently (NMOS). The connections of the power supply rails of VDD and Gnd are made across the inverter source and drain. The GDI cell input is the common point of the drain-source nodes. The required adder implementation using GDI methodology uses the available standard modules of XNOR, XOR, NAND, and NOR blocks (Table 2).

Fig. 3
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Full adder given in (Rafiee et al. 2021)

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Fig. 4
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Full adder given in (Seyedi and Jafari Navimipour 2022)

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Fig. 5
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Full adder given in (Fatemieh et al. 2021)

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Fig. 6
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Full adder given in (Krishnaveni et al. 2021)

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Fig. 7
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Full adder given in (Soe et al. 2021)

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Fig. 8
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Full adder given in (Soe et al. 2021)

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Fig. 9
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Full adder given in (Soe et al. 2021)

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Fig. 10
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Full adder given in (Dhariwal et al. 2022)

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Table 2 Mathematical modeling of the GDI-based adder cells
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4 Validation of the proposed adder cells using pre-layout and post-layout simulations

The proposed circuits are developed using the Cadence tool with 18 nm FinFET spectre models. Firstly, all the circuits are designed using Cadence Virtuoso using FinFET nodes to meet the desired functionality. The desired outputs of the circuits at their corresponding nodes are being validated using transient responses. Later, the circuits are verified for the required frequency of working using AC analysis. Secondly, by conducting Montecarlo analysis, pre-layout simulations, and performance metrics are taken for all the circuits with the testbench setup shown in Fig. 11.

Fig. 11
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Simulation test bench structure

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Buffer cells are added to the input ports in the actual test bench setup given in Fig. 11 for performing functionality checking. The parasitic resistance and capacitances are induced in the input terminals provided by the real-time usage of integrated circuits' interconnects and externally joined peripherals. Because of this phenomenon, the circuit exhibits distortions in the signal as well as they do cause a delay in the signals. In turn, the test bench for performing the simulation should have the input buffers to depict the real-time circuit performance. The amount of distortion that should be added to the circuit undergoing validation is at a minimum level almost equal to that practical occurrence in the deployment stages. In the same fashion, the testbench is connected with output inverters and followed by the capacitors with the utmost minimum level of 6 fF, leading to the form of the actual loads to the design.

The designs are simulated to measure their salient features with power dissipation, speed, power delay product (PDP), and energy-delay product (EDP). Moreover, these metrics were tabulated to evaluate one's meritorious advantages and limitations. The supply voltage varies from the minimum to maximum operating voltage of FinFET nodes. At every potential and by considering each test case of the cells, the designs have given different delay and power dissipation values from which the circuit’s total power dissipation has been measured. These power dissipation values at each VDD value are taken, and with the mathematical expression of average power given in Table 3, the designed circuit’s total power dissipation has been calculated. The prominent issue of leakage power of conventional MOS transistors at lower technology levels is being avoided, and the optimum performance levels are observed with the FinFET nodes of the designs by mitigating leakage power issues. The dynamic power occupies a significant portion of the overall power dissipation value. Specifically, the leakage power is developed at circuit nodes because of non-application of input test cases leads to an idle state of the circuit, and at this level, circuit power usage is treated as leakage power and, in other terms, named static power. The leakage power is measured by observing the designed Full adder cells’ power at the stand-still level. Among all the measured values of delay metrics, the delay with the highest value is taken as the final delay of the critical path of the design. In this manuscript, the delay metric is calculated at half of the overall applied VDD values of input and output responses.

The optimized layouts of the proposed circuits constructed in Cadence has given in Figs. 12, 13, 14, 15, 16, 17, 18, 19, 20, 21. The layouts are carried out using FinFET 15 nm technology. The proposed FA cells layouts LVS has matched and the RC extraction files are being added to the test bench to take post-layout results.

Fig. 12
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Layout of the full adder shown in Fig. 1

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Fig. 13
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Layout of the full adder shown in Fig. 2

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Fig. 14
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Layout of the full adder shown in Fig. 3

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Fig. 15
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Layout of the full adder shown in Fig. 4

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Fig. 16
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Layout of the full adder shown in Fig. 5

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Fig. 17
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Layout of the full adder shown in Fig. 6

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Fig. 18
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Layout of the full adder shown in Fig. 7

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Fig. 19
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Layout of the full adder shown in Fig. 8

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Fig. 20
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Layout of the full adder shown in Fig. 9

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Fig. 21
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Layout of the full adder shown in Fig. 10

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RC extracted file is being added to the test bench given in Fig. 11. The post-layout results are measured by varying the supply voltage from 0.1 to 1 V of VDD.

The sample response of the transient analysis of the proposed FinFET-based FA cell at VDD = 1 V for all the input test cases is given in Fig. 22.

Fig. 22
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Transient Response of the Designed full adders for the supply voltage VDD = 1 V

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To raise the actual voltage levels at the corresponding output levels for both Sum and Carry, the outputs of the designs are validated using Montecarlo analysis. The same Response is presented in Fig. 23.

Fig. 23
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Montecarlo analysis of the designed full adders sum and carry outputs

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The variation of delay, power consumption, PDP, and EDP values are given in Figs. 24 and 25 for all ten cells.

Fig. 24
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Vdd vs. Power consumption and propagation delay

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Fig. 25
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VDD vs. PDP and EDP

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4.1 The standard cell representation of the full adder module

Table 3 gives the experimental findings of the proposed circuits at a supply voltage of 1 V. Further simulations were run with the supply voltage varied between 0.6 and 1 V for a more thorough performance examination. The findings are displayed in Figs. 22, 23, 24, 25. All the proposed circuits are tested with the help of a test bench setup. The salient features of propagation delay, power consumption, power delay products, and energy-delay product have been calculated for all the proposed designs in addition to the variation of these three critical parameters at different supply voltages.

Table 3 Validation of the proposed full adder designs at VDD = 1 V
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Dynamic power is the amount consumed during the transition of signals from one to the other switching state. Besides, the leakage power is always focused on the involvement of a total number of transistors, but for the adopted designs, the leakage power is related to the other second-order effects too. From the given simulation results, it can be visualized that different adders with varied transistors have their unique performance metrics, and the power and delay constraints are too separate. Based on the number of internal nodes and active paths of signal routing, decide the required adder cell with the optimized performance factor.

5 Conclusion

This study describes a hybrid FA cell with good performance properties based on GDI and CCMOS circuitry. Ten different designs were compared to the recommended adder's design in an 18 nm spectre model of FinFET. The test bench adjustment for validation of the designed full adders is considered to meet the required specifications. The proposed designs are all tested individually and combined concerning the testbench results in improved performance of the designed circuits. Concerns about voltage degradation and the constrained driving capabilities of the GDI gates were also allayed by the addition of CCMOS logic-based inverters. Based on the elevated features of the designs, moreover scalability for application in a broader range of adders, the recommended FA design is a perfect replacement for the object of calculating units in existing ultra-large-scale computing systems.