1 Introduction

Advances resulting from new technologies and the high speed of light are important factors affecting the development of integrated optical devices. This approach will gradually result in the replacement of classical electronic systems by new-generation optical systems. Considering the importance of this issue, the rapid transfer, receipt, storage, and processing of information and most importantly all-optical logic computations using new-generation optical devices are the most important factors contributing to the realization of photonic integration technology and thus optical integrated circuits (OICs) [1]. In this context, new photonic materials with micro–nanometer sizes such as graphene, plasmon, and photonic crystals (PC) [2,3,4], which offer unique capabilities including the modulation of photon emission and control modes, and the diffusion and distribution of light in the structure, are considered to be significantly important for the development of such technologies. Moreover, among the mentioned photonic materials, PCs with aperiodic structure have attracted particular attention due to their range of photonic bandgap (PBG) [5], which plays a critical role in directing and controlling light, as well as their unique features such as small size and the ability to process and transfer data quickly, combined with a simple design that facilitates their construction and is considered to be one of the basic requirements regarding the implementation of OICs. Accordingly, PCs can be used in the design and implementation of various optical devices, including optical waveguides [6, 7], optical filters [8, 9], optical sensors [10,11,12], multiplexer/demultiplexers [13,14,15,16,17], optical converters [18], lasers [19], optical power dividers [20], optical logic gates [21,22,23,24,25,26], etc.

One of the most important and practical types of photonic structure, namely all-optical logic gates based on PCs, being considered to be one of the basic requirements for new-generation OICs, is designed herein. When all-optical logic gates are designed, parameters such as the contrast ratio (CR) [27], the response time to the input signal, the applicability, the output power, and the bit rate (BR) [28] are evaluated and compared, and the efficiency of the gate thereby determined. Optical logic gates based on PCs can be designed using three main mechanisms, namely the nonlinear Kerr effect, the self-collimation effect, and the interference effect in PCs. Herein, to optimize these parameters, the interference effect of waves in PCs is used to facilitate the design and implementation. The proposal is for an integrated structure which is not composed of different logic gates, resulting in a very compact footprint compared with previously proposed full adders. Also, the optical power intensity required at the input ports is lower than for previously proposed structures [21, 27, 29,30,31]. This approach also leads to the construction of a smaller structure with a higher CR than when using the other two mechanisms. Using the current method, the structure operates such that, if the light waves have a phase difference of about 2nπ (n = 1, 2, 3, etc.), constructive interference will occur and the logic gate output will be 1 or ON. However, if the phase difference between the waves is about (2n + 1)π with n = 1, 2, 3, etc., destructive interference will occur and the logic gate output will be 0 or OFF. Accordingly, using the phase difference between the waves, the output waves can be controlled using the structure of PC logic gates and a desired structure designed. For the proposed structure, the response time is calculated to be 1.1 ps while the CR for the Carry and Sum ports is 10.68 and 9.03 dB, respectively.

In general, various numerical methods can be used to analyze PCs, each having its own advantages and disadvantages. Such numerical methods can be divided into two general categories, namely those carried out in the frequency and time domain. Due to its compatibility with parallel processing and data extraction over a wide range of wavelengths, the finite-difference time-domain (FDTD) method [32] is applied herein to simulate the structure and derive the output spectrum results. Moreover, the optical devices are designed and constructed using PCs based on the range of the PBG and the plane-wave expansion (PWE) method. The PWE method has been applied to separate transverse electric (TE) and transverse magnetic (TM) modes and to calculate the frequency eigenvalues and PBG of the proposed structure [33].

The rest of this manuscript was organized as follows: Sect. 2 discusses the all-optical full-adder block and the design procedure for the proposed structure, while the simulation results are presented and discussed in Sect. 3. Finally, conclusions are drawn in Sect. 4.

2 All-optical full-adder block

Hybrid logic circuits are currently receiving much attention in the field of digital systems. These types of logic circuit generally have different inputs and outputs and can be designed and constructed using various gates. The full adder is among these important logic circuits. The structure of a full adder includes three inputs and two outputs. The two inputs A and B of this circuit represent the two most significant bits of the whole full adder, while the third input C represents the carry bit resulting from the least significant position. The two outputs in this circuit are denoted as the Sum and Carry, where the Sum represents the value of the least significant sum and the binary output variable Carry the output carry. The truth table of the whole binary full adder with its possible inputs is presented in Table 1, according to which the different modes of 1 or ON in the Sum and Carry outputs can be expressed as follows:

Table 1 The truth table for the full adder
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$${\text{Sum}} = {{A}} \oplus {{B}} \oplus {{C}} = {{A}}^{\prime } {{B}}^{\prime } {{C}} + {{A}}^{\prime } {{BC}}^{\prime } + {{AB}}^{\prime } {{C}}^{\prime } + {{ABC}},$$
$${\text{Carry}} = {{A}}^{\prime } {{BC}} + {{AB}}^{\prime } {{C}} + {{ABC}}^{\prime } + {{ABC}}.$$

In this work, 2D PC structures are used to design and simulate an all-optical full adder for use in next-generation digital systems. For this purpose, 23 dielectric rods along the x-axis and 21 dielectric rods along the z-axis are used. For design simplicity and to use silicon technology, the dielectric rods were made of silicon with a refractive index of nr = 3.46, placed in an air background with refractive index of ns = 1. The radius of the dielectric rods used was R = 0.2a, while the lattice constant was a = 630 nm, and the hexagonal lattice constant was selected. According to the desired structural parameters, the final size of the structure is estimated to be about 183 µm2. To take advantage of the unique properties of PCs for controlling and directing light in the design and construction of optical devices, the first priority is to analyze the range of the PBG and the amount of light scattering in these structures. The PWE method is thus used to determine the range of the PBG. According to the results obtained for the amount of light scattering within the given structure, the structure has three PBG ranges for the TE and TM modes (Fig. 1). The first PBG for the TM mode lies in the range of 0.285 ≤ a/λ ≤ 0.460, and the second PBG for the TM mode lies in the range of 0.575 ≤ a/λ ≤ 0.595, being equal to 1369 nm ≤ λ ≤ 2210 nm and 1058 nm ≤ λ ≤ 1095 nm, respectively. In addition, the PBG for the TE mode lies in the range of 0.830 ≤ a/λ ≤ 0.890, which is equal to 707 nm ≤ λ ≤ 759 nm. According to the wavelength ranges obtained for the proposed structure, the first PBG for the TM mode is considered to be optimal, due to its wide bandwidth.

Fig. 1
figure 1

The proposed PBG structure

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The basic structure of the desired all-optical full adder is designed based on the NRR and using the interference effects between the waves. The structure consists of 23 and 21 dielectric rods in the x- and z-direction, respectively. The proposed NRR is made of a 2D hexagonal lattice of silicon. The structure of the given NRR used in the design of the full adder is shown in Fig. 2. This basic structure comprises a square with diameter of 0.5 and rotation of 45° within a hexagon. The length of the sides of the hexagon is equal to a, while the diameter of the dielectric rods constituting the structure is equal to 0.08a. The length of the sides of the square is 0.353, while the radius of the dielectric rods constituting it is 0.04a.

Fig. 2
figure 2

A schematic of the proposed PC-NRR topology used in this paper

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The structure of the proposed all-optical full adder is shown in Fig. 3. In this structure, to create a full adder with three input ports (A, B, and C) and two output ports (Sum and Carry), five waveguides, four 120° bends, and a hexagonal NRR with a coupling rod are used to control and guide the light to implement the different logic states. The input Gaussian pulses enter the structure from each of the ports A, B, and C through the waveguides W1, W2, and W3, and depending on the interference between the waveguides and the hexagonal NRR, the output power in the various states of the SUM and Carry outputs exits through W4 and W5. The proposed NRR placed between the waveguides is described by parameters such as the refractive index and radius of the coupling rods, the radius of the internal rods, the relative positioning of the rods, the output wavelength range, the output power, and the quality coefficient of the output channel. The values of the main parameters and materials properties used in the simulations are presented in Table 2.

Fig. 3
figure 3

A sketch of the final proposed full-adder logic gate based on the PC-NRR

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Table 2 A summary of the values of the parameters used for the proposed full-adder logic gate based on the PC-NRR
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3 Results and discussion

In the proposed structure, depending on the power Pin entering waveguides W1, W2, and W3 from the input ports A, B, and C, the power exiting the Carry and Sum output ports varies between 0 and 1. When analyzing the different logic states at the outputs obtained from the simulations, powers between 0% and 30% correspond to logic state 0 while those between 70% and 100% correspond to logic state 1. Thus, according to the electromagnetic field distribution profile shown in Fig. 4a, when the power entering waveguides W1 and W2 is 0 and the power entering waveguide W3 is Pin, or in other words, A = 0, B = 0, and C = 1, the light coupled to the NRR is directed to the Sum output, and the Carry and Sum ports adopt logic state 0 and 1, respectively. In this case, the normalized power at a wavelength of 1550 nm for the Sum and Carry outputs is equal to 86% Pin and 6% Pin, respectively. These results are also shown in Fig. 4b, c.

Fig. 4
figure 4

The results for the all-optical full adder when A = 0, B = 0, and C = 1: a the electromagnetic field, b the output intensity, and c the output power level

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According to Fig. 5a, when the power entering waveguides W1 and W3 is 0 but the power entering waveguide W2 is Pin, i.e., A = 0, B = 1, and C = 0, the Carry and Sum ports adopt the logic state 0 and 1, respectively, considering the presence of a single pulse coupled to the NRR. In this case, the normalized power at a wavelength of 1550 nm for the Sum and Carry output is equal to 89% Pin and 7% Pin, respectively. These results are also shown in Fig. 5b, c.

Fig. 5
figure 5

The results for the all-optical full adder when A = 0, B = 1, and C = 0: a the electromagnetic field, b the output intensity, and c the output power level

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According to Fig. 6a, when the power entering waveguides W2 and W3 is Pin but the power entering waveguide W1 is 0, i.e., A = 0, B = 1, and C = 1, the Carry and Sum ports adopt logic state 1 and 0, respectively, considering the presence of two Gaussian pulses coupled simultaneously to the NRR. In this case, the normalized power at a wavelength of 1550 nm for the Sum and Carry outputs is 85% Pin and 5.5% Pin, respectively. These results are also shown in Fig. 6b, c.

Fig. 6
figure 6

The results for the all-optical full adder when A = 0, B = 1, and C = 1: a the electromagnetic field, b the output intensity, and c the output power level

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According to Fig. 7a, when the power entering waveguides W2 and W3 is 0 but the power entering waveguide W1 is Pin, i.e., A = 1, B = 0, and C = 0, similar to the two first cases, the Carry and Sum ports adopt logic state 0 and 1, respectively, considering the presence of a single pulse coupled to the NRR. In this case, the normalized power at a wavelength of 1550 nm for the Sum and Carry outputs is equal to 92% Pin and 4.5% Pin, respectively. These results are also shown in Fig. 7b, c.

Fig. 7
figure 7

The results for the all-optical full adder when A = 1, B = 0, and C = 0: a the electromagnetic field, b the output intensity, and c the output power level

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According to Fig. 8a, when the power entering waveguides W1 and W3 is Pin and the power entering waveguide W2 is 0, i.e., A = 1, B = 0, and C = 1, the Carry and Sum ports adopt logic state 1 and 0, respectively, considering the presence of two Gaussian pulses coupled to the NRR. In this case, the normalized power at a wavelength of 1550 nm for the Sum and Carry outputs is equal to 10.5% Pin and 85% Pin, respectively. These results are also shown in Fig. 8b, c.

Fig. 8
figure 8

The results for the all-optical full adder when A = 1, B = 0, and C = 1: a the electromagnetic field, b the output intensity, and c the output power level

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According to Fig. 9a, when the power entering waveguides W1 and W2 is Pin but the power entering waveguide W3 is 0, i.e., A = 1, B = 1, and C = 0, the Carry and Sum ports adopt logic state 1 and 0, respectively, considering the presence of the two Gaussian pulses coupled to the NRR. In this case, the normalized power at a wavelength of 1550 nm for the Sum and Carry outputs is equal to 9.7% Pin and 86% Pin, respectively. These results are also shown in Fig. 9b, c.

Fig. 9
figure 9

The results for the all-optical full adder when A = 1, B = 1, and C = 0: a the electromagnetic field, b the output intensity, and c the output power level

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Finally, as shown in Fig. 10a, when the power entering waveguides W1, W2, and W3 is equal to Pin, i.e., A = 1, B = 1, and C = 1, the Carry and Sum ports adopt logic state 1, considering the presence of the three Gaussian pulses coupled to the NRR. In this case, the NRR acts as a divider and the normalized power at a wavelength of 1550 nm for the Sum and Carry outputs is equal to 84.1% Pin and 82% Pin, respectively. These results are also shown in Fig. 10b, c.

Fig. 10
figure 10

The results for the all-optical full adder when A = 1, B = 1, and C = 1: a the electromagnetic field, b the output intensity, and c the output power level

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Note that, if the power entering waveguides W1, W2, and W3 is 0, there will be no output power due to the lack of coupling of the optical pulse to the NRR, and the Sum and Carry ports will adopt logic state 0.

Table 3 presents the truth table describing the performance of the proposed full adder, including the various logic states, the power sent to each input and waveguide, the power received by each of the Sum and Carry outputs and their logic states, as well as the response time in each of these states. According to these results, the response time of the proposed all-optical full-adder structure varies from 0.75 to 1.6 ps. Another important parameter in the design of all-optical logic gates is the contrast ratio, so the contrast ratio of 0 and 1 is also presented for each logic level. According to the following equation, the higher the power difference level between these two logic states, the better the performance of the logic gate [27].

Table 3 The simulation results for the proposed structure
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$${\text{CR}}\,\left( {\text{dB}} \right) = 10 \times \log \left( {\frac{{P_{\text{on}} }}{{P_{\text{off}} }}} \right),$$

where Pon is the power in logic state 1 or ON state and Poff is the power in logic state 0 or OFF state. According to this equation, the CR for the Sum and Carry outputs is 9.03 and 10.68 dB, respectively, for the proposed structure.

Table 4 compares the important parameters of the proposed structure with other (full- and half-adder) logic gates presented in recent years. According to this table, the response time and output CR of the proposed logic gate are highly desirable compared with those of structures presented in recent years. Additionally, the structure proposed herein is highly applicable due to the use of the interference principle between the waveguides and NRR, its very small structural size, as well as not requiring a change in the refractive index of materials. The maximum output delay of the proposed structure is 1.1 ps, which is very good compared with structures proposed in recent years.

Table 4 A comparison of the proposed full adder with recently reported devices
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4 Conclusions

We propose and design an all-optical full adder using a hexagonal NRR and five waveguides. In this design, the NRR between the waveguides controls the output parameters, depending on the refractive index and radius of the internal coupling rods as well as their relative positioning. The input Gaussian pulse enters the structure through three waveguides (W1, W2, and W3), and based on the principle of interference between the waveguides and NRR, the output power exits in various states from the output ports. Additionally, the management of the power entering the waveguides W1, W2, and W3 controls the power exiting the Carry and Sum ports between 0 and 1, corresponding to the OFF and ON states. The response time of the proposed full-adder structure varies from 0.75 to 1.6 ps. The maximum output delay of the proposed structure is 1.6 ps, and the CR for the Carry and Sum ports is 10.68 and 9.03 dB, respectively. To optimize the output parameters of the proposed structure, the interference effect in the PC is used, thereby simplifying its design.