Towards designing efficient reversible binary code converters and a dual-rail checker for emerging nanocircuits

Abstract

Reversible logic has attracted interest from many researchers in the area of quantum information science. Since there is no information loss in reversible logic, energy consumption is greatly reduced. However, realization of quantum equivalent circuits using cascading reversible gates is complex. Predominantly, this work targets implementation of quantum equivalent circuits using cascading reversible gates. In this work, novel code converters and a dual-rail checker with lower cost metrics such as gate count, garbage output, ancilla input, unit delay, logical calculation, and quantum cost are constructed. Several new reversible gates, namely BE (binary excess), BG-2 (binary Gray), GB-2 (Gray binary), and NG-R1 and NG-R2 (N $=$ new, R $=$ reversible), are designed and used to construct efficient code converter and dual-rail checker circuits. The main contribution of these novel circuits is the consideration of the gate-level schematics in the respective quantum equivalent circuit using our proposed algorithm. The performance results establish that the novel binary-coded decimal (BCD)-to-excess-3, binary-to-Gray, and dual-rail checker achieve improvement of 25 and 66.6 % in gate count and 44.4 % in quantum cost, respectively, compared with counterpart designs.

1 Introduction

The very large-scale integration (VLSI) industry is currently moving at high speed towards miniaturization, resulting in many challenges in terms of energy dissipation and quantum effects at the nanoscale. These problems are exacerbated when further downscaling the feature size of transistors [1]. To overcome this limitation, rigorous research is being carried out to identify prominent alternatives. One possible solution would be to develop a robust computational paradigm based on quantum technologies [2]. On the other hand, reversible logic is gaining in popularity due to its capability to implement quantum logic circuits [3]. Elementary quantum logic circuits can be designed using reversible logic gates due to their unitary behavior, in turn favoring more effective implementation of quantum computing [4]. Another prominent feature of reversible logic is zero information loss, which helps realization of energy-efficient circuits [4]. Reversible logic is popular for design of digital logic circuits with negligible power consumption, as proved by the famous researchers Landauer and Bennett [5, 6]. This concept provides strong motivation to choose reversible logic for digital logic circuit synthesis. The scope of reversible implementations extends to include thermodynamics and adiabatic complementary metal–oxide–semiconductor (CMOS) technology [7]. Thus, application of reversible logic is advocated in various fields, including quantum computing [8], nanoelectromechanical systems (NEMS) [9], low-power CMOS [10], optical computing [11], and nanotechnology [12].

A reversible logic gate provides a bijective mapping between its input and output vectors. Based on this bijective property, when knowing the output states, the input states should be recoverable, and the system shows no loss of information, resulting in reduced heat dissipation [13]. It is believed that reversible computing will become the dominant technology in the near future. Furthermore, increasing the computational speed of quantum circuits also increases their quantum cost, hindering synthesis of reversible logic circuits [14]. Hence, the quantum cost must be minimized by reducing the elemental quantum gates in a reversible circuit, providing strong motivation to synthesize reversible circuits with lower quantum cost. An important step in reversible circuit synthesis is the estimation of other reversible metrics such as the gate count (GC), garbage output (GO), ancilla inputs (CI), logical calculation (LC), and unit delay (UD), which we also calculate in this study. By achieving optimal reversible metrics, the performance of the reversible circuit can be enhanced.

Code converters are very common in electronic systems, being very important in electronic circuits to change information from one format to another. Furthermore, the importance of testing to enhance the reliability of VLSI circuits is well known in the digital world. The dual-rail checker (DRC) is a modest device for such testing. The operation of a DRC is verified when the outputs are complementary to each other.

Several reversible logic circuits have already been presented in literature, including an adder [15, 16], multiplier [17], arithmetic logic unit (ALU) [18], and sequential circuits [19]. However, few reversible circuits such as code converters and dual-rail checkers (DRCs) have been presented in literature [20,21,22,23,24,25,26,27]. Due to this lack of compact reversible code converters and DRCs in literature, we targeted these circuits in this work. An attempt was made to transform a cascaded gate-level circuit into a respective quantum equivalent (QE) circuit using our proposed algorithm, being especially useful to help beginners in the area of quantum computing to build quantum circuits from cascaded gate-level schematics. Elemental quantum gates (EQGs) such as CNOT, C-V, $\hbox {C-V}^{+}$, and NOT are adopted for the design of the QE circuits [28]. The quantum cost (QC) was successfully obtained using the RCviewer+ tool with some additional coding. The proposed code converters and DRC were very effective in terms of the reported cost metrics, namely gate count (GC), garbage output (GO), constant input (CI), unit delay (UD), logical calculation (LC), and quantum cost (QC). The quantum cost of our code converter and dual-rail checker circuits was calculated using the standard NCV library. The optimal quantum cost value of our proposed circuits was better than those of existing counterpart designs. Furthermore, use of the proposed gates strongly changes the cost metric values of the proposed circuits. The novelty of this work lies in the design of high-level blocks such as code converters and a DRC using quantum equivalent circuits in the quantum computing paradigm. The four major pillars of this work can be summarized as follows:

• We demonstrate synthesis of reversible circuits such as BCD-to-excess-3, BCD-to-Gray, binary-to-Gray, Gray-to-binary, and dual-rail checker in a quantum computing framework. In addition, we construct the quantum equivalent of these gate-level schematics using elemental quantum gates with the standard NCV library.

• We discuss elemental quantum gate-based qubit transitions in the quantum circuit of our three proposed reversible gates.

• We demonstrate and illustrate an algorithm for converting a cascaded gate-level schematic into the respective quantum equivalent circuit, which could be applied using criteria other than the quantum cost.

• We use several novel reversible gates to achieve circuit models for code converter and dual-rail checker circuits with low cost metrics, achieving optimal results compared with their best counterpart designs.

1.1 Organization and acronyms

The rest of this paper is organized as follows: Section 1.1 presents acronyms and a short explanation. Section 2 recalls the principles of reversible logic and quantum computing. Section 3 presents preliminary work on synthesis of code converters and a dual-rail checker, including details of the parameters and synthesis approach. Section 4 proposes synthesized circuits based on three reversible gates with low quantum cost. Section 4.5 includes a description of the elementary quantum gate-based qubit transitions in the quantum circuits. Section 5 presents the proposed circuits, gate level schematics, and quantum equivalent circuits. Section 5.1 contains a discussion of the proposed algorithm for transformation of a gate-level schematic into the corresponding quantum equivalent circuit. Section 6 presents our cost metric results as well as results for existing circuits identified based on a review of the state of the art. Section 7 summarizes the work, with conclusions and future prospects for research.

This work contains many acronyms, which are identified in Table 1 for better understanding of the paper. Quantum reversible acronyms have been surveyed in [1,2,3,4, 14, 28, 29].

Table 1 Acronyms with short explanation

2 Principles of reversible logic and quantum computing

We list below the basic principles that are essential to understand reversible circuits. The principles of reversible logic and quantum computing have been surveyed in [1,2,3, 15, 16, 28, 29].

2.1 Quantum computing and basic elemental quantum gates

Quantum computing In quantum computing, a bit is specified by a qubit. A quantum circuit is realized using EQGs. In fact, a quantum circuit is reversible and works with qubits. The state of a qubit can be explicitly stated as ${\vert }\Psi>=\alpha {\vert }0>+\beta {\vert }1>$, where ${\vert }1>$ and ${\vert }0>$, denote logic states 1 and 0, respectively. The complex numbers $\alpha$ and $\beta$ have the property $\left| \alpha \right| ^{2}+\left| \beta \right| ^{2}=1$.

Elemental quantum gate EQGs are the basic elements for constructing a quantum circuit. The quantum cost is a measure of the EQG count in a quantum circuit. In quantum computing, the state of a particle is depicted by a qubit. The computations using a qubit in a quantum circuit are just matrix computations. Elemental quantum gates can compute with matrices. The popular elemental quantum gates are controlled-V (C-V), controlled-$\hbox {V}^{+}$ ($\hbox {C-V}^{+}$), NOT, and CNOT (FG). A more interesting feature of controlled gates (V and $\hbox {V}^{+}$) arises if one uses V and $\hbox {V}^{+}$ on the same line, i.e., V $\times \hbox {V}^{+} =$ I. This tells us that, if one uses V and $\hbox {V}^{+}$ on the same line, one forms a quantum wire with zero quantum cost. A short discussion of all four EQGs is presented below:

• Controlled-V gate This gate implements the square-root-of-NOT, its basic feature being that the square of V is equivalent to an inversion.

• Controlled-$\hbox {V}^{+}$ gate This gate is the inverse of the controlled-V, known as the Hermitian of the NOT gate. Its basic feature is that the square of $\hbox {V}^{+}$ is equivalent to an inversion.

• CNOT The basic feature of this gate is that, if the control qubit $=$ 1, then the target qubit is inverted, whereas if the control qubit $=$ 0, then the target qubit is non-inverted. The CNOT is also known as the Feynman gate (FG).

• NOT A single qubit is inverted.

Fig. 1

Reversible circuits: a MCT, b CCNOT gate and QE, c CNOT gate, d NOT gate, e even number of CNOT, f odd number of CNOT, g IQG

2.2 Reversible logic

In a reversible gate, the defined Boolean function maps each input vector to a unique output vector. A reversible gate has the following characteristics: (1) there are equal numbers of input and output lines, (2) various operations (loops, feedback, and fanout) are not allowed, and (3) each input vector maps to a unique output vector.

Definition 1

An n-input n-output Toffoli gate has the first $n-1$ inputs equal to the control and the remaining input as a target (Fig. 1a). The target gate output is an Ex-OR with the control. A gate with two controls and one target gate is known as a CNOT gate (Fig. 1c). A gate with no control gate is known as an invert gate (Fig. 1d).

Example 1

A three-input three-output Toffoli gate (CCNOT) reversibly executes the operation $\left( {a, b, c} \right) \rightarrow \left( {a,b,a\oplus b} \right)$, where a and b are the controls, the notation $\oplus$ indicates the Ex-OR operation, and c is the target. If A $=$ B$=$ 1, the state of the target C is inverted (Fig. 1b).

Definition 2

A common technique used to reduce the QC of a quantum circuit is as follows: If there are an even number of CNOT gates with identical I/O stage, the QC is zero (In Fig. 1e). Similarly, for an odd number of CNOT gates with identical I/O stage, first consider the even number of CNOT gates with zero QC, then find the effective QC (Fig. 1f).

Definition 3

Another elemental gate that is helpful for reducing the QC is the IQG. Figure 1g shows the general arrangement of an IQG.

Definition 4

Quantum gate libraries such as MCT, NCV, NCT, and EQ are utilized for quantum circuit design and optimization. In the NCV library, four elements are included, viz. C-V, $\hbox {C-V}^{+}$, CNOT, and NOT. The MCT library includes NOT instead of CNOT, whereas the NCT includes NOT, CNOT, and square-root-of-NOT gates. In the EQ library, the basic elemental quantum gates are defined.

The performance of a reversible circuit is often estimated using cost metrics such as the gate count (GC), garbage output (GO), ancilla input (CI), logical calculation (LC), and unit delay (UD). To enhance circuit performance, these cost metrics must be minimized. A short discussion of the important cost metrics is presented below:

• Quantum cost In the quantum computing paradigm, the quantum cost (QC) is the sum of the EQGs.

• Garbage/unused or unwanted output The garbage output (GO) specifies the unused outputs.

• Constant/ancilla input Constant input (CI) is not needed in the structure of a reversible function in the quantum computing paradigm.

• Logical calculation/hardware complexity The total number of gates, e.g., AND, NOT, and Ex-OR, utilized to synthesize the logical function. In general, a logical calculation (LC) is written according to the following equation: LC $=$ number of gates (Ex-OR + AND + NOT) of the logical function $=$ number of gates ($\alpha +\beta +\delta$) of the logical function, where $\alpha$ is the two-input Ex-OR, $\beta$ is the two-input AND, and $\delta$ is the one-input NOT.

• Unit delay/critical path The unit delay (UD) is defined as the maximum number of reversible gates in a path from the input line to any output line.

2.3 Reversible circuit mapping library

The standard NCV library is very popular in current research [28]. It is complete; i.e., it enables a quantum logic circuit to be built for any reversible function. The NCV library comprises the NOT, CNOT, C-V, and $\hbox {C-V}^{+}$ gates. The goal of the NCV library is to synthesize a quantum circuit with set outputs and inputs [29]. To achieve this, only three elemental quantum gates, i.e., NOT, C-V, and $\hbox {C-V}^{+}$, are used in the quantum circuit. In this library, binding and optimization models are applied to construct the quantum circuit. Such structures are well known in quantum computing modeling. Most of the quantum circuit construction described herein is based on this library. The basic properties V $\times$ V $= \hbox {V}^{+} \times \hbox {V}^{+} =$ Inversion and $\hbox {V} \times \hbox {V}^{+} =$ I are applied to propagate the qubit (Fig. 2a). In the case of a Toffoli gate (CCNOT), the synthesis flow using the NCV library is shown in Fig. 2b.

Fig. 2

Basics of NCV library: a state transition of a qubit, b TG quantum circuit with qubit transition using NCV library

3 Related work

Previous syntheses of reversible code converters and dual-rail checker circuits assumed that the quantum cost depended only on the reversible gates used in the design. Existing designs, such as those proposed in [20,21,22,23,24,25,26,27], were therefore constructed from gate-level schematics, considering only the individual gates as the criteria for calculation of the quantum cost. However, when using a quantum computation model, the whole quantum equivalent circuit model must be used to determine the quantum cost. However, integration of circuits based on cascaded gates into the respective quantum circuit is an intricate process. In [20], the authors proposed a variety of reversible code converter circuits. The cost metrics of the BCD-to-excess-3 code converter were GC of 4, CI of 6, and QC of 24. The construction of a reversible dual-rail checker was described in [25], where new reversible gates were used for circuit construction. The circuit implementation had GC of 6, GO of 14, CI of 12, and QC of 54. However, none of these existing designs establish a framework for transformation of a gate-level schematic into a respective quantum equivalent circuit.

By a cost-efficient circuit, we mean the circuit implementation showing the best synthesis, i.e., with optimal metrics. The criteria determining these two concepts (best synthesis and optimal metrics) depend on the gate used and the algorithm applied to obtain the quantum equivalent circuit. This work proposes three reversible gates for construction of code converters and a dual-rail checker, along with a few existing reversible gates. We also demonstrate how elemental quantum gates can process the qubit transition in a reversible circuit and thereby produce the outputs. We used the NCV library to construct the quantum circuits. Important metrics are also evaluated for the synthesized reversible circuits, including GO, UD, LC, QC, and CI. The proposed approach for circuit synthesis leads to reduced cost metrics compared with counterpart designs.

4 Proposed reversible gates

For the construction and optimization of reversible circuits, we propose several reversible gates. The QE circuit for a single reversible gate is first illustrated in Sect. 4.1, for readability.

4.1 Illustration of the transformation from a single reversible gate-level circuit to a respective quantum equivalent circuit

In this subsection, the quantum circuit for a single reversible gate is illustrated. In the first step, we create a *.pla file for the reversible gate, based solely on its truth table. During the second step, a Toffoli block (in *.tfc code format) is created from the *.pla file. The third step includes decomposition of the Toffoli block into EQGs (in *.real code format) using the RCviewer+ tool. The EQGs are then used to construct the quantum equivalent circuit. This methodology was used in this work to construct a quantum equivalent circuit for a single reversible gate.

Fig. 3

Reversible BE gate: a schematic diagram, b truth table, c QE and BE.tfc code, and d snapshot of results

4.2 Reversible BE gate

A new $4\times 4$ schematic of the BE gate is presented in Fig. 3a. In the quantum equivalent of the BE gate, six CNOT, two C-V, and one $\hbox {C-V}^{+}$ gate are utilized to implement the logical function. Therefore, the QC is 9 (counting the primitive gates). The truth table of the BE gate is presented in Fig. 3b. The QE and BE.tfc code are presented in Fig. 3c. The BE.tfc code is then used to construct the QE circuit. The BE.tfc code is also utilized to evaluate the QC, as shown by the snapshot in Fig. 3d.

The synthesis expression was constructed from Fig. 3a. When setting the third and fourth input of the BE gate to low and high, respectively, the outputs are generated as $P=A\oplus B\oplus 1=\overline{A\oplus B}$, $Q=\overline{B} \oplus 1=B$, and $S=\left( {A+B} \right) \oplus 0=A+B$. For the aims of this study, we minimized the gate count in the BCD-to-excess-3 code converter, utilizing one BE, one PG, and one NG-R2 to construct the BCD-to-excess-3 converter (Sect. 5.2).

The LC of the BE gate was calculated as follows: The expression for S has LC $=$ 0. The expression for Q ($B\oplus D$) has $\hbox {LC} =1\alpha$. Then, we use signal duplication to obtain $A\oplus B$ for the expression for P. The final LC value can then be computed as: LC $(\hbox {BE}) = 1\alpha ({P}) + 1 \alpha$ (for the signal duplication operation in P) + $1\alpha ({Q}) + 1\alpha ({R}) + 0\alpha ({S}) = 4\alpha$.

Fig. 4

Reversible NG-R1 gate: a schematic diagram, b truth table, c QE and NG-R1.tfc code, and d snapshot of results

4.3 Reversible NG-R1 gate

The schematic diagram and truth table of the novel NG-R1 are shown in Fig. 4a, b. The QE and NG-R1.tfc code are shown in Fig. 3c. The QC and two-qubit gate result are both 10, as shown in Fig. 4d. The LC for the NG-R1 was calculated as $2\alpha +2\beta$.

The synthesis expression was constructed from Fig. 4a. When setting the fourth and fifth input of the NG-R1 gate to low, the required outputs of the NG-R1 gate are then $P=A$, $Q=B$, $R=C$, $S=A \cdot B\oplus 0=A \cdot B$, and $T=A \cdot C\oplus 0=A \cdot C$. For the aims of this study, we minimized the garbage output in the dual-rail checker circuit. In this work, we utilized two NG-R1 gates and two NG-R2 gates to construct the dual-rail checker circuit (Sect. 5.7).

Fig. 5

Reversible NG-R2 gate: a schematic diagram, b truth table, c QE and NG-R2.tfc code, and d snapshot of results

4.4 Reversible NG-R2 gate

The NG-R2 structure has five inputs and five outputs. Its schematic diagram and truth table are shown in Fig. 5a, b. The QE and NG-R2.tfc code are shown in Fig. 5c. Five two-qubit gates are considered to be present in the QE circuit, with QC of 5; we evaluated the LC as $2\alpha$. To check the QC of the NG-R2, the result is presented in Fig. 5d.

The synthesis expression was constructed from Fig. 5a, when setting the third input of the NG-R2 gate to be low. The required outputs of the NG-R2 are obtained as $P=A$, $Q=A\oplus B$, and $R=\left( {A+B} \right) \oplus 0=A+B$. For the aims of this study, we minimized the gate counts and garbage outputs in the code converters and dual-rail checker circuit (Sect. 5.7).

Fig. 6

EQG-based synthesis flow in a BE, b NG-R1, and c NG-R2

4.5 EQG-based synthesis flow with proposed reversible gates

The synthesis flow was investigated based on the outputs obtained with set inputs using the NCV library [29]. To achieve this, only four EQGs were used in the quantum circuit, such structures being well known in quantum computing. The basic properties $\hbox {V} \times \hbox {V}=\hbox {V}^{+} \times \hbox {V}^{+} =$ Inversion and $\hbox {V} \times \hbox {V}^{+} = \hbox {I}$ were used to propagate the qubit in the quantum circuit [30]. The inputs were all on the left side of the QE, with the corresponding outputs on the right side, and the quantum gate outputs in the middle. In the case of the BE synthesis flow, the input “1111” was taken for computing using the heuristic: a square of V and square of $\hbox {V}^{+}$ gives inversion, whereas if V and $\hbox {V}^{+}$ are combined, the identity results. These basic properties yield the output shown in Fig. 6a. The synthesis flow for the other proposed gates, such as NG-R1 and NG-R2, were obtained using the same procedure, as depicted in Fig. 6b, c. The target output was verified by studying the truth table of these gates (Figs. 3b, 4b, 5b). This test was conducted using only a few qubit states; a similar method could be applied for any other qubit states.

5 Proposed circuit models of reversible code converters and a dual-rail checker

In the field of computation, a circuit that converts information from one format to another can be regarded as a code converter. The most popular types of code converter are BCD-to-excess-3, BCD-to-Gray, binary-to-Gray, and Gray-to-binary. The operation of the BCD-to-excess-3 converter requires a BCD number (0 to 9). The conversion is done by adding the decimal number 3 to each BCD number. The working process of the BCD-to-Gray converter requires a four-bit BCD number (0 to 9). With increasing demands for circuit testing, the DRC has emerged as a new popular circuit. The QE circuit for the cascaded gate is illustrated in Sect. 5.1, in advance for readability.

5.1 Illustration of transforming cascaded reversible gate-based circuits into respective quantum equivalent circuits

In this subsection, we present a technique for converting a cascaded reversible gate circuit into a respective QE circuit based on EQGs. To the best of the authors’ knowledge, such QE circuits for code converter and DRC circuits are not discussed in literature. The steps to convert a cascaded reversible gate into the respective QE circuit is presented in Algorithm 1.

Algorithm 1:

Algorithm to convert cascaded reversible gates into the respective QE circuit.

• Step 1 Construct *.tfc code for the reversible gates involved in the cascaded gate-level circuit.

• Step 2 Assign input labels in alphabetical order to all the gates. The assigned alphabetical order just indicates the input pins. All the output pins also have the same alphabetical order that was assigned to the input pins. Then, check that the assigned input alphabets are the same as the output alphabets.

• Step 3 The *.tfc code is modified after combining each gate in the cascaded gate-level circuit.

• Step 4 The final combined.tfc code for the cascaded gate-level circuit is obtained using the RCviewer+ tool, ready for decomposition, optimization, and QC calculation.

Fig. 7

Flowchart for conversion of a cascaded gate-level circuit to a respective QE

The flow chart for constructing a quantum circuit is depicted in Fig. 7. The QE circuits proposed herein were constructed using this methodology.

5.2 The proposed reversible BCD-to-excess-3 code converter

A four-bit BCD-to-excess-3 circuit was synthesized using BE, PG, and NG-R2 gates. A schematic diagram of the proposed circuit is shown in Fig. 8a. We describe the construction of this circuit in Algorithm 2. The intermediate bits such as $\hbox {I}_{1}$ and $\hbox {I}_{2}$ are determined by the input bits B$_i$ ($i =$ 0–3). The result is achieved after a particular connection performed on the circuit. The construction of the Toffoli gate block and BCD-to-excess 3.tfc code is shown in Fig. 8b. The QE circuit was synthesized using the BCD-to-excess-3.tfc code by decomposition into EQGs as shown in Fig. 8c. The QC and two-qubit gates are presented in Fig. 8d.

Proposition 1

The LC of the BCD-to-excess-3 converter is LC(BCD-to-excess-3) $=$ $4\alpha (\hbox {BE}) + 2\alpha +1\beta (\hbox {PG}) + 2\alpha (\hbox {NG}-\hbox {R}2) = 8\alpha +1\beta$.

Fig. 8

BCD-to-excess-3 converter: a schematic diagram, b Toffoli gate block and BCD to excess-3.tfc code, c QE, and d snapshot of result

Fig. 9

BCD-to-Gray converter: a schematic diagram, b Toffoli gate block and BCD to Gray.tfc code, c QE, and d snapshot of results

Fig. 10

Binary-to-Gray converter: a the proposed BG-2 gate, b truth table, c schematic diagram, quantum equivalent, and BG-2.tfc code, and d snapshot of results

Fig. 11

Gray-to-binary converter: a the proposed GB-2 gate, b truth table, c schematic diagram, quantum equivalent, and GB-2.tfc code, and d snapshot of results

5.3 The proposed reversible BCD-to-Gray code converter

The BCD-to-Gray circuit is composed of three gates, namely NG-R2, FG, and F2G (Fig. 9a). In this circuit, the intermediate bits such as $\hbox {I}_{1}$, $\hbox {I}_{2}$, and $\hbox {I}_{3}$ are determined by the input bits. The Toffoli gate block and BCD-to-Gray.tfc code are shown in Fig. 9b. To construct the BCD-to-Gray converter, we propose Algorithm 3, which is named the BCD-to-Gray code converter construction algorithm. The BCD-to-Gray QE circuit is presented in Fig. 9c. The construction of this circuit required QC of 8 (Fig. 9d). To the best of the authors’ knowledge, this is the first BCD-to-Gray circuit to be proposed using state-of-the-art technology.

Proposition 2

The LC of the BCD-to-Gray converter is LC(BCD-to-Gray) $= 2\alpha (\hbox {NG}-\hbox {R}2) + 1\alpha (\hbox {FG}) + 2\alpha (\hbox {F2G}) = 5\alpha$.

5.4 The proposed binary-to-Gray and Gray-to-binary code converters

Binary-to-Gray code conversion can be considered to be a one-bit change between two successive numbers in the converter output. Existing circuits for binary-to-Gray and Gray-to-binary conversion usually have high GC, UD, LC, GO, and QC values, as studied in [20, 23, 24, 27]. This work is quite different in that one novel reversible gate can be used to construct this circuit. To reduce the cost metrics of these code converter circuits, new reversible gates without GO or CI were constructed.

5.5 The proposed BG-2 gate and binary-to-Gray code converter

The proposed BG-2 (binary-to-Gray) gate and its truth table are shown in Fig. 10a, b. The binary-to-Gray code converter was constructed with GC of only 1 and no GO or CI to synthesize the outputs. Figure 10c, d presents the schematic, QE, BG-2.tfc code, and snapshot of results. The LC for the BG-2 was calculated as $3\alpha$.

5.6 The proposed GB-2 gate and Gray-to-binary code converter

The GB-2 (Gray-to-binary) gate proposed herein and its truth table are shown in Fig. 11a, b. The presented Gray-to-binary code converter circuit is free from GO and CI, leading to a good fit with reversible circuit synthesis, as depicted in Fig. 11c. The circuit inputs are placed on the left side, and the outputs on the right. Figure 10c, d shows the schematic, QE, GB-2.tfc code, and snapshot of results.

The LC of the GB-2 gate was calculated as follows: The expression for P has LC $=$ 0. The expression for Q ($A\oplus B$) has $\hbox {LC} = 1\alpha$. We then apply signal duplication twice to obtain ($A\oplus B$) for use in the expressions for both R and S. Note that we utilize FG for reversible signal duplication. The LC of the FG is 1$\alpha$. Then, the LC can be computed as: $\hbox {LC} = 0\alpha$ (P) + $1\alpha$ (Q) + $2\alpha$ (for the two signal duplications for the expressions for R and S) + $1\alpha$ (R) + $2\alpha ({S}) = 6\alpha$.

5.7 The proposed reversible DRC

This subsection presents the construction and algorithm for the reversible dual-rail checker circuit. Such a DRC could be used for testing, although no parity bit checking is required. The DRC produces two outputs: $Z_1 =X_0 Y_1 +X_1 Y_0$ and $Z_2 =X_0 X_1 +Y_0 Y_1$, with complementary values. In this circuit, on the left, two NG-R1 gates are utilized to AND four-bit numbers, then the OR function is generated on the right using two NG-R2 gates. This circuit contains four gates (2$\times$ NG-R1, and 2$\times$ NG-R2), requiring 10 inputs and 10 outputs. The input includes four-bit numbers ($X_{0}$, $X_{1}$, $Y_{0}$, and $Y_{1}$) and six ancilla inputs, as depicted in Fig. 12a. Its reversible quantum equivalent circuit is presented in Fig. 12b, c. This circuit produces two outputs: $\hbox {Z}_{1}$, and $\hbox {Z}_{2}$, while the other eight outputs are garbage outputs. We use the DRC.tfc code to construct the Toffoli gate block, as shown in Fig. 12b. Meanwhile, Fig. 12d shows a snapshot of the results. Testing of the DRC circuit is possible using the two outputs $Z_1 =X_0 Y_1 +X_1 Y_0$ and $Z_2 =X_0 X_1 +Y_0 Y_1$. The DRC circuit was constructed herein using Algorithm 4.

Fig. 12

DRC: a schematic diagram, b Toffoli gate block and DRC.tfc code, c QE, and d snapshot of results

Proposition 3

The LC of the DRC is $2 (2\alpha +2\beta )$ (NG-R1) + $2 (2\alpha )$ (NG-R2) $=$ $8\alpha +4\beta$.

Table 2 Cost metric statistics for BCD-to-excess-3

Lemma 1

A DRC is a circuit that performs the complement of two outputs.

Proof

Since mathematical expressions are involved in the testing process of a DRC, the testing solution can even be obtained manually for a modest DRC approach. These manual calculations for the $\hbox {Z}_{1}$ and $\hbox {Z}_{2}$ outputs of the DRC are illustrated below: $\square$

Outputs expressions: $Z_1 =\left[ {X_0 X_1 } \right] \times \left[ {\begin{array}{c} Y_1 \\ Y_0 \\ \end{array}} \right]$, $Z_2 =\left[ {X_0 Y_0 } \right] \times \left[ {\begin{array}{c} X_1 \\ Y_1 \\ \end{array}} \right]$

Condition 1

Selecting inputs of $(X_{0}, X_{1}) = (1, 1)$ and $(Y_{0}, Y_{1}) = (0, 0)$, the computed outputs are $Z_1 =\left[ {X_0 X_1 } \right] \times \left[ {\begin{array}{c} Y_1 \\ Y_0 \\ \end{array}} \right] = 0, Z_2 =\left[ {X_0 Y_0 } \right] \times \left[ {\begin{array}{c} X_1 \\ Y_1 \\ \end{array}} \right] = 1$ (i.e., the complement of $\hbox {Z}_{1}$). Hence, no fault occurs.

Condition 2

Selecting inputs of $(X_{0}, X_{1}) = (1, 1)$ and $(Y_{0}, Y_{1}) = (1, 0)$, the computed outputs are $Z_1 =\left[ {X_0 X_1 } \right] \times \left[ {\begin{array}{c} Y_1 \\ Y_0 \\ \end{array}} \right] = 1, Z_2 =\left[ {X_0 Y_0 } \right] \times \left[ {\begin{array}{c} X_1 \\ Y_1 \\ \end{array}} \right] =1$ (not the complement of $\hbox {Z}_{1}$). Hence, fault occurs.

Fig. 13

Schematic presentation of testing circuits using DRC

Therefore, a DRC can take two pairs of inputs, i.e., $(X_{0}$, $X_{1})$ and $(Y_{0}, Y_{1})$, and the outputs are complementary.

5.8 Testing strategy using DRC cell

Testing of the DRC cell is presented in Sect. 5.7. The testable circuit#1 and testable circuit#2 were placed such that all the outputs (P, Q, R, and S) mapped to all the inputs of the DRC cell (Fig. 13). The steps to construct a testable circuit are illustrated in Algorithm 5. The task of testing is to place the DRC cell at the output of the circuit to be tested. Since all the outputs of the tested circuit that are correctly connected to the DRC must have the same logic, the DRC cell generates the complementary outputs according to the same procedure as presented in Lemma 3.

6 Experimental results and comparative evaluation

Quantum circuit construction was carried out using the RCviewer+ tool and results obtained on an Intel(R) core(TM) i5-6200U 2.40-GHz CPU with 4 GB RAM under Windows 10 Home (64 bit). The proposed circuits were first built using the *.tfc code, then processed using the RCviewer+ tool. The proposed circuits were compared with previously proposed circuits, in terms of GC, QC, UD, LC, and UD.

Cost metrics and statistics for the proposed versus counterpart designs are presented in Tables 2, 3, 4, and Table 5. A comparison of the reversible metrics for the proposed BCD-to-excess-3 versus existing designs is presented in Table 2, showing that the proposed design surpasses all existing designs reviewed in [19,20,21,22]. According to Table 2, the optimal circuit in [20] was selected and its cost metrics compared, revealing GC of 25 % less than [20], CI of 42.8 % less than [20], GO of 42.8 % less than [20], and QC of 5.26 % less than [20]. Note that our BCD-to-excess-3 code converter is competitive with existing works and offers improved metrics in all cases.

Table 3 Cost metric statistics for binary-to-Gray converter

Table 4 Cost metric statistics for Gray-to-binary converter

Table 5 Cost metric statistics for DRC

The binary-to-Gray and Gray-to-binary code converter circuits proposed using the described approach offer substantial improvements over reported counterpart designs with reversible metrics. Tables 3 and 4 present the performance of our binary-to-Gray and Gray-to-binary code converters versus counterpart works. The binary-to-Gray converter in [24] has lower quantum cost, but its design was 3-bit while the binary-to-Gray code converter presented herein is 4-bit and also has lower cost metrics such as GC, CI, GO, UD, and QC. The GC for the binary-to-Gray converter is 1 (66.6 %) less than that in [20], and the GC for the Gray-to-binary converter is also 1 (66.6 %) less than that in [20]. It is obvious that these novel circuits, including the binary-to-Gray and Gray-to-binary code converters, are much better in terms of these cost metrics.

From Table 5, it is evident that the reversible metrics for the dual-rail checker circuit presented herein are significantly lower compared with those of the best counterpart design in [25]. The constructed circuit has GC of 4 (33.33 %) less than [25], CI of 6 (50 %) less than [25], GO of 8 (42.8 %) less than [25], and QC of 30 (44.44 %) less than [25]. Hence, one can state that this novel DRC indeed has lower cost metrics. In fact, our DRC circuit is competitive with counterpart designs, with improvement in some cases.

7 Conclusions

We have constructed reversible code converters and a dual-rail checker circuit. We propose an algorithm to transform a cascaded reversible gate circuit into a respective quantum equivalent circuit. A primary advantage of this algorithm is the four-step process needed to obtain the quantum equivalent circuit. We targeted reversible designs for code converters and a dual-rail checker, aiming to optimize their cost metrics, including the gate count, ancilla inputs, garbage outputs, logical calculation, unit delay, and quantum cost. Use of particular types of reversible gate for a particular logical function is very effective for construction of the proposed circuits with minimal cost metrics. The proposed BCD-to-excess-3 circuit has 42.85 % less garbage output, 25 % less gate count, and 5.26 % less quantum cost compared with existing designs. The constructed dual-rail checker circuit shows 44.4 % improvement in quantum cost with respect to existing designs. Besides the design, the Toffoli gate block and quantum equivalent circuit of each design are also constructed by our proposed algorithm. Hence, the new code converters and dual-rail checker circuit offer improved performance, representing the best choice for low-cost quantum computing. In the future, any cascaded gate-level circuit can be quickly converted into a quantum equivalent circuit using the proposed algorithm, enabling development of quantum computing frameworks by anyone.