Keywords

1 Introduction

Nowadays at the transistor level, the designer uses CMOS but it has physical limitations such as current leakage, short channel effect, power consumption, large layout area and delay [1–4]. It is predicted that these physical limitations of CMOS will result at the end of conventional CMOS. The vision is towards QCA (Quantum dot cellular automata). It principally focuses on high device density, low delay and low power circuits. QCA performs computation using electric or magnetic field polarization [5]. The advancement in digital hardware systems and subsystems has emerged in higher computational density circuits and energy loss has been reduced.

In the early 1960s, Landauer [6] shows that each logic bit of information, KT ln2 joules of energy loss is due to missing bits of information. However, according to Bennett [7], there would be no energy loss and it can be avoided by using the digital hardware designed by reversible gates. Moreover, digital hardware systems are not only logically reversible but also physically reversible. In the design of logically reversible digital hardware system, gate level approach is used. The distinctive feature of the gate is one-to-one mapping between inputs and outputs and output logic can be recovered from input logic [8–11]. Physical reversibility of a digital system can be defined in a way such that if computation is in backward direction without energy loss, then that system design is fulfilling the criteria of physical reversibility. In the flow chart (shown in Fig. 1) of the designing approach, the various levels are shown; fifth level shows the logical reversibility and sixth level shows the physical reversibility.

Fig. 1
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Approach level of the digital hardware system

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The paper is organized as follows: Sect. 2 depicts the reversible logic and QCA terminology. Section 3 depicts the design of new code converters using two new types of 3 × 3 reversible gates. Sections 3.2 and 3.3 describe the Binary to Gray and Gray to Binary code converters with QCA block diagrams and layouts. Section 4 performs a simulation setup result and comparative performance analysis result with the existing approach for the proposed converters in terms of cell complexity, clock cycle and area occupancy. The last section concludes this paper.

2 Background Study

In this section, we present some preliminary knowledge about QCA, reversible logic and their behaviours along with lower bound parameters.

Basics of QCA: The fundamental unit of a QCA device is the QCA cell. These cells contain four quantum dots positioned near the corners of the cell, where another two free electrons can reside [5, 12–15]. Cells have two polarization states (Fig. 1a). These states permit the cells to represent binary value. By setting P = +1 polarization (binary 1), while a cell with P = −1 polarization (binary 0). The majority vote condition is most used frequently (shown in Fig. 2d). In this, the output is defined by Maj = (AB + BC + CA). If the set one input is at 1, it works as 2-input OR gate. If the set one input is at 0, it works as 2-input AND gate.

Fig. 2
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a QCA cell with two binary interpretations of the states. b QCA minority voter. c QCA inverter. d QCA majority vote. e QCA phase and clock cycle. f QCA binary wire

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Reversible logic gate: A reversible logic gate is an X-input and X-output logic gate that produces a unique output pattern for each possible input pattern [2, 3, 14, 16]. In reversible circuit design, the challenging task is to optimize parameters such as gate count, garbage outputs and quantum cost, otherwise the efficiency of circuit will degrade and also its cost.

Garbage outputs, sometime unwanted output, should be minimum.

Gate count and constant input should be minimum.

Total logical calculation and quantum cost should be minimum.

Fan-out is not allowed. That states each output can only singularly link to a preceding input.

3 Proposed Reversible Code Converters

In this section, we design an optimized and improved version of reversible 3-bit Binary to Gray and Gray to Binary code converters. Converters are design circuits in which a logic presented in one code is converted to another code.

3.1 New Type of Reversible Gates

In this subsection, we have designed two new types of 3 × 3 reversible gates that are used to construct the Binary to Gray and Gray to Binary code converters. BG-1 gate is a 3 × 3 type reversible gate and input vector corresponding to a unique output vector that can be uniquely determined. In Table 1, the input values are (0, 1, 2, 3, 4, 5, 6, 7) and the corresponding output values are (0, 3, 6, 5, 4, 7, 2, 1). Figure 3a, b depict the block diagram and equivalent quantum realization of the BG-1 gate. The quantum cost, of the BG-1 gate is 2. Another 3 × 3 type reversible gate is named as GB-1 (Gray to binary) gate. The corresponding truth table of GB-1 gate is shown in Table 2 in which the input values are (0, 1, 2, 3, 4, 5, 6, 7) and the corresponding output values are (0, 7, 6, 1, 4, 3, 2, 5). Figure 4a, b depict the block diagram and equivalent quantum realization of GB-1 gate. The quantum cost of the GB-1 gate is 2.

Table 1 Reversibility of the new type of BG-1 gate
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Fig. 3
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a Block diagram of BG-1 Gate. b Quantum implementation of BG-1

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Table 2 Reversibility of the new type of GB-1 gate
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Fig. 4
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a Block diagram of BG-1 Gate. b Quantum implementation of GB-1

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Fig. 5
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a Block diagram of BG-1 to Gray converter. b QCA layout of Binary to Gray code converter. c QCA block diagram of Binary to Gray code converter

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3.2 Architecture of the Proposed Binary to Gray Code Converter

The QCA layout and block diagram of BG-1 gate are depicted in Fig. 5b, c. In the QCA layout, BG-1 gate is composed of 46 cells. Three inputs (binary code) to the cell are labelled as B0, B1 and B2. The centre cell is the device cell (majority voter) that executes the operation of AND, OR with appropriate polarization. The other cell, labelled as G0, G1 and G2 synthesize outputs (gray code). From the truth table, Table 1, it is obvious that \( {\mathbf{G}}_{0} = {\mathbf{B}}_{0}\,\oplus\,{\mathbf{B}}_{1} \), \( {\mathbf{G}}_{1} = {\mathbf{B}}_{1}\,\oplus\,{\mathbf{B}}_{2} \) and \( {\mathbf{G}}_{{\mathbf{2}}} = {\mathbf{B}}_{{\mathbf{2}}} \). For setting (input A = B0, B = B1 and C = B2) in BG-1 gate (shown in Fig. 5a).

Fig. 6
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a Block diagram of GB-1. b QCA layout of Gray to Binary code converter. c QCA block diagram of Gray to Binary code converter

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The QCA block diagram of the Binary to Gray is drawn in Fig. 5c and can perform the majority of logic functions as

$$ \begin{aligned} & {\mathbf{G}}_{0} = {\mathbf{M}}({\mathbf{M}}(\overline{{{\mathbf{B}}_{1} }} ,0,{\mathbf{B}}_{0} ),{\mathbf{M}}({\mathbf{B}}_{1} ,0,\overline{{{\mathbf{B}}_{0} }} ),1), \\ & {\mathbf{G}}_{1} = {\mathbf{M}}({\mathbf{M}}(\overline{{{\mathbf{B}}_{1} }} ,0,{\mathbf{B}}_{2} ),{\mathbf{M}}({\mathbf{B}}_{1} ,0,\overline{{{\mathbf{B}}_{2} }} ),1), \\ & {\mathbf{G}}_{{\mathbf{2}}} = {\mathbf{B}}_{{\mathbf{2}}} \\ \end{aligned} $$

3.3 Architecture of the Proposed Gray to Binary Code Converters

The QCA layout and block diagram of GB-1 gate are depicted in Fig. 6b, c. The QCA layout of GB-1 gate is composed of 64 cells. Three gray code inputs G0, G1 and G2 are applied instantly into the device cell (majority vote) that executes the operation of AND, OR with appropriate polarization. The other cell, labelled as B0, B1 and B2 synthesize outputs (binary code). From the truth Table 2 we synthesis Boolean expressions as \( {\mathbf{B}}_{0} = {\mathbf{G}}_{0}\,\oplus\,{\mathbf{G}}_{1}\,\oplus\,{\mathbf{G}}_{2} \), \( {\mathbf{B}}_{1} = {\mathbf{G}}_{1}\,\oplus\,{\mathbf{G}}_{2} \) and \( {\text{B}}_{{\mathbf{2}}} = {\mathbf{G}}_{{\mathbf{2}}} \). For setting (input A = G1, B = G2 and C = G0) in GB-1 gate (shown in Fig. 6a). The QCA block diagram of the Binary to Gray converter is drawn in Fig. 6c and can perform the majority and minority logic functions as

$$ \begin{aligned} & {\mathbf{B}}_{0} = {\mathbf{M}}_{{{\mathbf{aj}}}} ({\mathbf{M}}_{{{\mathbf{aj}}}} ({\mathbf{M}}_{{{\mathbf{aj}}}} ({\mathbf{G}}_{1} ,{\mathbf{G}}_{2} ,1),\overline{{\mathbf{M}}}_{{{\mathbf{aj}}}} ({\mathbf{G}}_{1} ,{\mathbf{G}}_{2} ,0),{\mathbf{G}}_{0} ,0),\overline{{\mathbf{M}}}_{{{\mathbf{aj}}}} (({\mathbf{M}}_{{{\mathbf{aj}}}} ({\mathbf{G}}_{1} ,{\mathbf{G}}_{2} ,1),\overline{{\mathbf{M}}}_{{{\mathbf{aj}}}} ({\mathbf{G}}_{1} ,{\mathbf{G}}_{2} ,0),0),{\mathbf{G}}_{0} ,0),0) \\ & {\mathbf{B}}_{1} = {\mathbf{M}}_{{{\mathbf{aj}}}} ({\mathbf{M}}_{{{\mathbf{aj}}}} ({\mathbf{G}}_{1} ,{\mathbf{G}}_{2} ,1),\overline{{\mathbf{M}}}_{{{\mathbf{aj}}}} ({\mathbf{G}}_{1} ,{\mathbf{G}}_{2} ,0),0),\;{\mathbf{B}}_{{\mathbf{2}}} = \, {\mathbf{G}}_{{\mathbf{2}}} \\ \end{aligned} $$

4 Simulation Setup Results

The two different code converters have been laid out and simulated by using QCADesigner v2.0.3 tool. In this simulation, we used the bistable approximation and the following set parameters: (number of samples 12800, radius of effect 65 nm, clock amplitude factor 2, convergence tolerance 0.001000, relative permittivity 12.9, clock high and low are 9.8e22 and 3.8e23, respectively, maximum iterations per sample 100, cell size 18 nm × 18 nm and dot diameter 5 nm) (Figs. 7 and 8).

Fig. 7
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Simulation results for Binary to Gray code converter

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Fig. 8
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Simulation results for Gray to Binary code converter

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5 The Comparative Performance Tables 3, 4 and 5 of New Designs

The comparative performance Tables 3, 4 and 5 sketches the performance of our proposed designs with existing designs in terms of number of majority gate (MV), cell count and latency. The QCA layouts used the designs of L-shaped wire, majority vote (MV) and inverters. The stability and robustness of these designs can be tested based on cell count, area and latency.

Table 3 Comparative analysis of the various reversible Binary to Gray code converter
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Table 4 Comparative analysis of the various Gray to Binary code converters
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Table 5 Code converter designs comparison table
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6 Conclusion

This paper has presented the QCA implementations of a Binary to Gray and Gray to Binary code converters using two new types of reversible gates. For the first time ever proposed in the literature with an optimal approach and using emerging nanotechnology archetype QCA Designer tool. The new types of gates have a capability to optimize reversible parameters for the design of converters. The nanoscale Binary to Gray converter design requires, area (proposed design has 95,658 nm2 compared with 38.232 nm2 [17]), number of MVs used (proposed design has 6Majority + 3inverters compared with 6Majority + 4inverter [17]) and complexity (proposed design requires 46 cells compared with 118 [17]), whereas the nanoscale Gray to Binary converter requires, area (proposed design has 20,736 nm2 compared with 36.288 nm2 [17], number of MVs used (proposed design has 6Majority + 1inverter compared to 6Majority + 4inverter [17]) and complexity (proposed 64 cells compared with 112 [17]). Moreover, we have verified the functionality of the proposed converters in QCA-Designer tool. Finally, converter circuit reveals the major QCA advantages such as less area utilized, high device density and latency. The proposed design outperforms the existing ones in terms of scalability and efficiency. The proposed converter circuits will be useful in many applications such as inside computer operations, communication systems many digital circuits, etc.