1 Introduction

The use of circuits with more than two logic levels has been offered as a solution to the interconnection and routing problems. Such circuits, named as multiple-valued logic (MVL) circuits, have a potential for reducing the chip area consumed by interconnection wiring and functional units in very-large scale integration (VLSI). Applying signals having more than two levels to a single wire, reduces the number of wires for the same range of data, and this reduction results in a decrease in number of required IC pins. As the interconnection length and number of wires used is reduced, the space between any two wires increases without increasing the total silicon area, leading to a decrease in resistance and capacitance of contacts and interconnections.

Due to the limited supply voltages, higher radices cannot be obtained using voltage mode circuits. On the other hand, current mode circuits have the advantages of current scaling, copying and sign changing with a simple current mirror. So, the current-mode logic is chosen because of their potential in implementing higher radices.

However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. There are two important drawbacks of the current mode multi-valued circuits. These circuits consume a static DC power continuously, since the input or the output variable is a current and this current usually has non-zero values. The second disadvantage is the difficulty of finding circuits to implement the multilevel sequential circuits. With the addition of multilevel sequential circuits almost every type of binary logic circuits can be realized using the multiple-valued approach, like adder/multiplier circuits, memory circuits, sequential circuits, decoders/encoders, current/voltage comparators, programmable devices and etc. Some of these circuits may be compatible with their binary counterparts.

Flip-flops are well known basic elements of sequential circuits and can be realized using multiple-valued logic circuits. Characteristic equations and next-state tables of the multi-valued conventional flip-flops such as RS and JK are defined in the Ref. [1, 2]. Studies about implementation of these flip-flops can be found in the literature but they are very limited and complicated [3, 4]. In addition, these conventional flip-flops use input values, current state output and inverse of current state output for calculating the next-state output. In current-mode multi-valued circuits, inversion operation is performed by subtracting the input signal from (r−1) × I b , where r is the radix (number of logic levels) and I b is the reference current level and other logic levels are determined as integer multiples of this reference current. In this study, we use 4-level logic with the I b  = 5 μA reference current level. So the logic levels 0, 1, 2 and 3 correspond to 0, 5, 10 and 15 μA respectively. The inverter circuit needs to use the maximum current and it consumes a lot of power. Therefore it must be avoided to keep the power consumption at minimum level.

2 AB flip-flop

We propose a new flip-flop structure named as AB flip-flop due to its A and B inputs, and its next-state equation is defined as follows [5];

$$ Q_{n\, + \, 1} \, = \,A\, + \,B\, \times \,Q_{n} $$

the idea behind this definition is that, it does not involve any inversion operation. The inversion operation should be avoided in the current mode logic design, because it increases the power consumption of the circuit considerably. Because, inversion is performed by subtracting the current from the maximum allowable current.

The state transition table of the AB flip-flop is given in Table 1. Table clearly shows that the flip-flop can successfully change its state for any input combination.

Table 1 Transition table of the AB flip-flop
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Block diagram of the AB flip flop is shown in Fig. 1. It is composed of a MIN circuit to perform AND operation, a MAX circuit to perform OR operation and a LATCH/RESTORER circuit to hold the current state and to restore the output current.

Fig. 1
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AB flip-flop

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The MIN and MAX circuits are current-mode, multi-input circuits, working based on winner/loser-takes-all principle [6, 7]. (Fig. 2).

Fig. 2
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MAX and MIN circuits based on winner/loser takes all principle

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2.1 The new latch/restorer circuit

The main drawback of current-mode multi-valued logic circuits is that they are not self restored unlike the binary logic circuits. The predefined current levels can be deviate from their original values due to some variations in active element dimensions, power supplies, technology parameters, etc. This variation on the output signal is carried to next stages. It can be tolerated and output can be detected correctly for a range of value that is called noise margin (i.e., ±I b /2 for this application). But the signal must be restored to its original value before it exceeds this limit, in order to obtain a correct output. The flip-flop circuits have positive feedback in nature, which prohibits any variation from the predefined levels. Otherwise this variation forces the output to shift either to ground or power supply voltage. So it is necessary to use a restoration circuit in the flip-flop to avoid this problem.

The restoration circuit given in Fig. 3 is based on the upper threshold circuit given in Ref. [8, 9].

Fig. 3
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The new latch and restoration circuit

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$$ a |\begin{array}{*{20}c} c \\ b \\ \end{array} \, = \,\left\{ {\begin{array}{*{20}c} {c\quad {\text{if }}a\, \ge \,b} \\ {{ 0}\quad {\text{otherwise}}} \\ \end{array} } \right. $$

For a 4-level logic system (r = 4) the restoration algorithm may be expressed as follows:

$$ \begin{gathered} \left\langle {x_{1} } \right\rangle \, = \,\left. x \right|_{{{r \mathord{\left/ {\vphantom {r 2}} \right. \kern-\nulldelimiterspace} 2}}}^{{{r \mathord{\left/ {\vphantom {r 2}} \right. \kern-\nulldelimiterspace} 2}}} \, = \,x\; [ {\text{mod }}\;{{ (r} \mathord{\left/ {\vphantom {{ (r} 2}} \right. \kern-\nulldelimiterspace} 2} ) ]\hfill \\ \left\langle {x_{2} } \right\rangle \, = \,x_{1} \; [ {\text{mod}}\; \, {{ (r} \mathord{\left/ {\vphantom {{ (r} 4}} \right. \kern-\nulldelimiterspace} 4} ) ]\quad x_{1} \, = \, (x\, - \,\left\langle {x_{1} } \right\rangle )\hfill \\ \left\langle x \right\rangle \, = \,\left\langle {x_{1} } \right\rangle \, + \,\left\langle {x_{2} } \right\rangle \hfill \\ \end{gathered} $$

here x is the input, and <x> is the restored output.

The input current is first compared to I max/2 and if the current is greater than 15/2 = 7.5 μA the MSD of the restored signal <I 1> is set to logic 2 (i.e. <I 1> = 10 μA) otherwise it is set to zero. Then <I 1> is subtracted from the input current and the reminder is compared to 2.5 μA. If it is smaller than 2.5 μA the LSD of the restored signal <I 0> is set to zero, otherwise it is set to logic 1 (i.e. <I 0> = 5 μA).

We can summarize the operation of the restoration circuit as follows:

$$ \begin{gathered} <I_{ 1}> \, = \, 10\,\mu {\text{A}}\quad {\text{if}}\;I_{\text{in}} \, \ge \, 7.5\,\mu {\text{A}} \hfill \\ <I_{ 1}> \, = \,0\quad {\text{if}}\; I_{\text{in}} \, <\, 7.5\,\mu {\text{A}} \hfill \\ <I_{0}> \, = \, 5\,\mu {\text{A}}\quad {\text{if}}\;\left( {I_{\text{in}} \, - \, <I_{ 1}>}\right)\; \ge 2.5\,\mu {\text{A}} \hfill \\ <I_{0}> \, = \,0\quad {\text{if}} \;\left( {{\text{I}}_{\text{in}} \, - \, <{\text{I}}_{ 1}>}\right)\; < 2.5\,\mu {\text{A}} \hfill \\ I_{\text{out}} \, = \, <I_{ 1}> \, + \, <I_{0}> \hfill \\ \end{gathered} $$

Both HOLD and RESTORE operations are performed at the same time, by using the circuit given in Fig. 3. The restoration circuit is modified as latch/restorer circuit, by adding two pass transistors M2 and M11.

The opposite phase voltage mode clock signals (clk, \( \overline{clk} \)) stimulate the pass transistors and perform the timing of the flip-flop circuit. In order to keep the restored data, the first pass transistor M2 is turned off and the output current is mirrored to the input trough the second pass transistor M11 during the second half of the clock signal. Using current mode clock signals does not improve the circuit performance, but requires additional circuitry and increases the power dissipation.

The number of Q outputs (I out) can be increased by adding more current mirrors to the final stage.

The 4-valued AB flip-flop circuit is simulated using H-Spice, UMC 0.18um technology, level 49 transistor parameters and 1.8 V power supply voltage. Applied input signals and the resulting simulation output are given in Fig. 4 and it is fully compatible with Table 1.

Fig. 4
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The inputs and Q output signal of the AB flip-flop

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The new latch/restorer circuit is optimized for new application to obtain smooth transitions. Comparison of the previous [5] and the new circuit is given in Table 2. The layouts of 8-valued implementations are given in Figs. 5, 6 respectively. The new circuit uses 26 transistor for 4-valued implementation and 38 transistors for 8-valued multiple-level implementation. The previous latch circuit needs 29 transistors for 4-valued implementation and 53 transistors for 8-valued implementation. Although there is a slight advantage in terms of transistor count and the area for 4-valued circuits, but, the most important advantage of the new circuit is reducing spikes during the level transitions, which can be clearly seen in Figs. 9, 10. However, the area advantage also becomes evident in 8-valued circuit implementations.

Table 2 Comparison of the circuits in Ref. 5 and the new circuits
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Fig. 5
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The IC layout of the 8-valued latch circuit in Ref. [5]

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Fig. 6
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The IC layout of the 8-valued latch circuit in this paper

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Fig. 7
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Counting sequence for 2-digit modulo-16 counter

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Fig. 8
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The block diagram of the 2-digit modulo-16 counter

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Fig. 9
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Outputs of 2-digit modulo-16 counter with the restorer-latch circuit given in Ref. [5]

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Fig. 10
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Outputs of 2-digit modulo-16 counter with the new restorer-latch circuit

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3 Counter circuit

In order to show the usefulness of the proposed AB flip-flop, 2-digit modulo-16 counter is designed. The counting sequence is given in Fig. 7. The counter may be realized by either using two 4-valued AB flip-flops or a single 8-valued AB flip-flop. But it is necessary to use at least three D-type flip-flops if the voltage mode binary realization were used. Figure 8 shows 4-valued realization by using two AB flip flops.

Using this counting sequence and state transition table of the AB flip-flop, the next-state equations of the A and B inputs can be obtained by inspection and the counter circuit may be built as shown in Fig. 8. Although the output waveforms show the correct counting sequence, the waveform has large spikes during the transitions in the first circuit given in Ref. [5]. The number of transistors and the spikes are highly reduced with the new restorer-latch circuit presented here.

All the simulations are performed by using H-Spice, UMC 0.18 μm technology. Level 49 transistor parameters are used.

4 Conclusions

In this study, a new version of the current-mode, multi-valued sequential flip-flop circuit and its application to a synchronous 2-digit modulo-16 up counter are presented. The new circuit uses fewer transistors than the previously published flip-flop circuit and the output waveforms of the new flip-flop and counter circuit does not have very high spikes during the transitions as the previous version. The radix of the circuit is taken to be 4 in these applications, but it can be increased to 8 with minor modifications. It is not very useful to use more than 8-levels since the noise margin becomes very small.

Designing equivalent circuits in binary logic rather than the multiple-valued logic requires approximately 60 % increase in transistor count and 40 % increase in the area. On the other hand, current-mode multi-valued circuits have constant current consumption, regardless of the switching activity, which makes the power consumption higher than the binary circuits.

Multi-valued logic design is still an open area, especially the sequential design part. Unfortunately there are not available algorithms or methods for the simplification of multilevel logic equations and design of sequential circuits. This study is just a step to that open area and needs improvements in circuit level and extended system level implementation.