1 Introduction

High-speed low-to-medium resolution analog-to-digital converters (ADCs) are required in the communication receivers for Quadrature Amplitude Modulation (QAM), disk read channels and Ultra-Wideband (UWB) receivers [1]. The analog signal is sampled at Giga-Hertz and digitized to no more than 6 bits. At this relatively low resolution, the straight forward full-flash architecture seems best suited for the high speed data converter. However, flash ADCs in CMOS technology suffer greatly from random offsets in the comparators which can easily exceed the least significant bit (LSB) [2], defined as

$$ 3\sigma{\it{V}_{\text {os,comp}}} \le \frac{1}{2} {\text {LSB}}=\frac{\it{V}_{\text {FS}}}{2^{N+1}} $$
(1)

where σV os,comp is the mean square root value of the comparator offset, V FS is the full-scale range of the converter and N is the resolution. Although the dynamic offset generated by the clocked latch can be reduced by the preamplifier, the spread in the threshold voltages of the preamplifier always limit the overall performance [3]. Such spread error scales down inversely as the square root of the input transistors’ sizes [4] but at the expense of high parasitics which deteriorate available bandwidth. The key to realize good resolution at high speed ADC therefore lies in efficient methods to resolve such speed and resolution trade-off.

Offset averaging is one such method that can be applied to preamplifier array in flash ADCs [5]. Rational designed averaging network would improve the array offset performance by 3–4 times without enlarging preamplifiers area [6]. But any kind of averaging network generates boundary threshold offset due to the finite network configuration. More than 1bit linearity loss resulting from averaging edge stimulates various forms of averaging termination schemes to smooth out the random mismatch across the preamplifier array. Either dummy amplifiers with sufficient number to preserve an infinite character of array or special termination circuits to compensate edge offset are used in previous works [7–10]. But large number of dummies would waste the full scale range and consume too much power, on the other hand, special termination always requires delicate controlling of amplifier’s transconductance which is not very efficient.

The proposed termination technique generates an intended asymmetric spatial filter response matching the impulse response window width, W IR, to the active zero-crossing response window width, W ZX at the boundary of network [11]. Such way is composed of less active dummies and passive components, at the same time the boundary error is reduced as close as to 1%. The principle of such termination scheme is explained in the subsequent sections followed by an experimental 1 GS/s 4bit flash ADC prototype.

2 Averaging and spatial filtering

Infinite offset averaging was presented in an array of preamplifiers of flash ADC, whose load resistors R 0 connect to nearest neighbors with lateral averaging resistors R 1 as shown in Fig. 1 [5]. The difference between analog input and reference voltage generates the signal dependent output current to the averaging resistor network. Figure 2(a) is used to simplify the analysis. Here the full differential circuit is replaced by the single end configuration and zero-crossing current source is simplified to an ideal current source. Each zero-crossing branch I s(n + i) contributes to a certain output current I out(n). It is obvious that such contribution depends on the distance away from the node n. For eg., I s(n) contributes larger than I s(n ± 1, 2, 3…). Considering an arbitrary node n, Kirchhoff’s current law (KCL) requires that

$$ \begin{aligned} I_{\text{s}}(n)&=I_{\text{out}} (n)+(I_{\text{out}}(n)-I_{\text{out}}(n+1)) \frac{\it{R}_0}{\it{R}_1}\\ &\quad+(I_{\text{out}}(n)-I_{\text {out}}(n-1)) \frac{\it{R}_0}{\it{R}_1} \end{aligned} $$
(2)
Fig. 1
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Infinite resistor averaging network

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Fig. 2
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The symmetric spatial filter response of the resistor averaging network. a Branch current distribution. b Spatial filter response

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The z and inverse z transform yields the spatial impulse response as follows [11],

$$ \begin{aligned} h(n)&=b^{-|n|},\, b={e^{-|a {\text {cos}} h(1+R_1/(2\times{R_0}))|}}\\ H(n)&=\frac{h(n)}{\sum\limits_i h(i)} \end{aligned} $$
(3)

Here h(n) and H(n) are relative current distribution to the main current I out(n) and normalized response to the overall input current as plotted in Fig. 2(b). The current distributions outside the impulse response window, W IR, are all neglected. Until now the impulse response is only defined by the ratio of R 1/R 0. Although delicate analysis has proved that small R 1/R 0 improves the DNL/integral-nonlinearity (INL) better [3], a practical ratio about one is often chosen since preamplifiers gain shrinks with small R 1. Under such situation, the spatial filter has a decided characteristic with W IR equal to 5. Actually h(n) outside W IR decreases seriously resulting in the value less than 5%.

Considering a true analog input varying randomly across the full scale range, the preamplifiers in the front-end array have different operation states dependent on the voltage headroom between their reference voltages and the analog inputs. All the zero-crossing cells are implemented by differential pairs, their static V − I characteristic and zero-crossing response is shown in Fig. 3. Here zero-crossing window width, W ZX is defined by

$$ W_{\text {ZX}}\approx \frac{2\sqrt 2 V_{\text {ov}}}{\text {LSB}}+1 $$
(4)

where V ov is the overdrive voltage of input MOS transistors. The zero-crossing cells outside the W ZX only generate the tail current to the averaging network. For an ADC, whose resolution is decided, the W ZX is almost fixed because the overdrive voltage of MOS pair ranges from 150 to 300 mV in the typical applications due to both the speed and linearity requirements. Assuming the LSB is 25 mV, then the W ZX width approximates 15 which is much larger than the typical W IR.

Fig. 3
figure 3

Zero-crossing response

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3 Asymmetric spatial filter scheme for averaging termination

3.1 Averaging termination error analysis

The typical averaging network used in the flash ADC is the same as shown in Fig. 1 with finite number of preamplifiers. Such finiteness of the preamplifiers array poses unique problems at the boundaries when utilized in an averaging flash ADC. Usually the array reaches ends at the upper and lower limits of the full scale range. This will disrupt averaging at the last few amplifiers, because at the end nodes there is no longer equal zero-crossing current distribution into the resistor network from both left and right sides. To analyze the error at the averaging network edge, a 4-bit flash configuration is adopted and there are 15 preamplifiers at the front-end as shown in Fig. 4. There is no scheme to modify the edge error. Based on the analysis in Sect. 2, W IR equal to 5 and W ZX equal to 15 are assumed.

Fig. 4
figure 4

4-bit flash ADC front-end averaging map without any termination. a Circuit configuration. b Simplified map

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At the network edge, the effective W IR only include 3 preamplifiers and W ZX only comprise 8 preamplifiers. Both windows are not full as their own widths. Now let us focus on the current branch on the right end. Since W IR is 5, preamplifier A1, A2, A3 contribute current to the right end branch as follows:

$$ \begin{aligned} i_{\text {out}}(n)&=g_{\text{m}}(v_{\text {in}}-n\Updelta)H(0)\\ &\quad+g_{\text{m}}(v_{\text {in}}-(n-1)\Updelta)H(1)\\ &\quad+g_{\text{m}}(v_{\text {in}}-(n-2)\Updelta)H(2)\\ &=g_{\text{m}}\Updelta \times (H(0)+H(1)+H(2))\\ &\quad\times \left(\frac{v_{\text {in}}}{\Updelta}-n+\frac{H(1)+2H(2)}{H(0)+ H(1)+H(2)}\right) \end{aligned} $$
(5)

When output current becomes zero, the zero-crossing point is

$$ v_{\text{in}}=n\Updelta-\frac{H(1)+2H(2)}{H(0) +H(1)+H(2)}\Updelta $$
(6)

So the edge error (EDE) is

$$ {\text{EDE}}=-\frac{H(1)+2H(2)}{H(0)+H(1)+H(2)}\Updelta $$
(7)

Here \(\Updelta\) is the symbol of LSB, H(n) means absolute spatial filter response. This result shows that in the presence of the averaging resistors, those contributed positive currents to the edge node effectively pull the zero-crossing point toward the center of the array. Unless the positive current contributions are compensated by the negative ones from dummies or by distorting reference voltages, all the zero-crossings within the range of W IR/2 at each edge are pulled, resulting a systematic INL. Some active averaging termination techniques are published. However they are always complicated due to delicate controlling of the input transconductance [1, 7–9].

3.2 Asymmetric spatial filter scheme

Until now all of the termination techniques try to compensate the edge error based on the decided spatial filter scheme as shown in Fig. 2(a), which is symmetric. The proposed way modifies such scheme to an asymmetric style matching the finite averaging network which is asymmetric also. The new averaging circuit is shown in Fig. 5 as follows.

Fig. 5
figure 5

4-bit flash ADC front-end averaging map with asymmetric spatial filter scheme which extending the width of W IR. a Circuit configuration. b Simplified map

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There are three main differences from the original averaging network: 1) two dummies inserted, 2) two ends cross-connected, 3) termination resistor R T used to tune the spatial filter characteristics. It is clear that the impulse response window W IR is full again, meaning that new balance can be realized by including the two dummies D2 and D3, at the same time only D2 is added to the zero-crossing response window W ZX. The amplifiers A1, A2, A3 and D2 work in the linear region while D3 operates in the saturation state. The modified current distribution in the node n can be calculated as

$$ \begin{aligned} i_{\text{out}}(n)&=g_{\text{m}}(v_{\text{in}}-n\Updelta)H(0)\\ &\quad+g_{\text{m}}(v_{\text{in}}-(n-1)\Updelta)H(-1) \\ &\quad+g_{\text{m}}(v_{\text{in}}-(n-2)\Updelta)H(-2)\\ &\quad+g_{\text{m}}(v_{\text{in}}-(n+1)\Updelta)H(+1)\\ &\quad -I_{\text{TAIL}} H(2)\\ \end{aligned} $$
(8)

Here the sequence H(n) indicates the current contributions dependent on the symmetric spatial filter response and relative positions of the preamplifers. Using the same method as in the last section, the new EDE can be defined as

$$ {\text {EDE}}=-\frac{H(-1)-H(1)+2H(-2)-\frac{H(2)V_{\text {ov}}}{\Updelta}}{H(0)+H(1)+H(-1)+H(-2)}\Updelta $$
(9)

The new form of the EDE provides the possibility to cancel itself in a proper combination of the spatial filter response H(i). Considering the modern CMOS technology, the factor \(V_{\text{ov}}/\Updelta\) ranges from 5 to 10. Here the factor is assumed 5.5. Now the edge error is dependent only on the H(i), which is tuned by the ratio of termination resistor R T and R 1. In the ideal averaging network, the equivalent resistances seen at each node from both left and right sides are the same. If a different R T is inserted, this symmetric architecture is disrupted. Such effect can be plotted in Fig. 6. Using the same method in [3], the modified spatial filter response H(i) is listed in Table 1. The spatial filter response is not anymore symmetric and H(i) at the R T side keeps reducing as the increasing R T/R 1. It generates sufficient tuning space for adjusting the EDE as shown in Fig. 7. Simulation proves that a ratio of 7 corresponding to the error less than 1%. Moreover, the curve of Fig. 7 is quite flat around the optimum point which is good with respect to variation of R T/R 1 due to the CMOS technology.

Fig. 6
figure 6

Asymmetric spatial filter scheme with tuned R T/R 1

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Fig. 7
figure 7

Boundary resistance ratio tuning optimization

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Table 1 Asymmetric spatial filter response H(i)
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4 An experimental 1 GS/s 4-bit flash ADC using asymmetric spatial filter scheme

The proposed asymmetric spatial filter termination scheme is applied to a 1 GS/s 4-bit sub-sampling flash ADC to validate its performance, which is designed for UWB application with 400 mV full scale range. The experimental ADC is design in SMIC 0.13 μm CMOS technology with a 1.2 V power supply. A passive high pass filter operates for level shifting. A high speed Track and Hold Amplifier (THA) samples the input signal and its output goes through the averaging network to the comparators array. The circuit is designed with R 1 = 600 ohm, R 0 = 660 ohm, and R T = 4.8 Kohm. The utilized P+ Poly SAB resistor has 3-sigma value at 0.5% level, which is high enough for 4-bit resolution in our UWB application. At the same time, if high matching behavior is required, the mirrored shuffle layout pattern can be utilized as mentioned in [12]. The layout of the ADC is shown in Fig. 8 and it occupies an active chip area of 0.6 mm2. The ADC using and not using asymmetric filtering scheme is simulated both at the sub-sampling full swing input. Their output spectrum is depicted in Figs. 9 and 10 respectively. A 25.8 dB SNDR and 35.9 dB SFDR results in 4-bit ENOB at the first mode, at the same time 8.7 dB linearity loss happens without asymmetric termination. A short summary of the experimental results is listed in Table 2. It can be concluded that the proposed termination technique is a power efficient way to improve the low-to-medium resolution flash ADC.

Fig. 8
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The layout of the experimental ADC

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Fig. 9
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The spectrum of the flash ADC using asymmetric spatial filter scheme

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Fig. 10
figure 10

The spectrum of the flash ADC using no special termination

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Table 2 Summary of the experimental results
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5 Conclusion

A new averaging network termination scheme for flash ADC is presented that the edge error is relieved efficiently. This is implemented by adding less dummies than previous works and termination resistors in the cross-connection style, generating an asymmetric spatial filter response. The error source and improvement analysis is presented and a experimental 1 GS/s 4-bit flash ADC in 0.13 μm CMOS technology is designed to validate the scheme performance. The optimized error ratio is less than 1% while the ADC loses more than 1-bit linearity without the proposed scheme. Only two dummies are required which consumes much less power than the normal approaches.