Study of SVPWM control algorithm with voltage balancing based on simplified vector for cascaded H-bridge energy storage converters

Abstract

DC-side voltage balancing is a critical problem to be solved for cascaded H-bridge energy storage converters. Aiming at inner-phase voltage balancing problem, a space vector pulse width modulation (SVPWM) algorithm with voltage balancing based on simplified vector is proposed. Firstly, the number of voltage vector is simplified by the proposed algorithm. Secondly, the action time of each level is calculated based on the volt-second balance, and the output vector is determined by comparing the DC-side voltage magnitude. Furthermore, the change of module level is minimal at the time of level change, and leapfrog hopping of the module level is prevented. Then, the inner-phase voltage balance can be achieved using vector selection. Due to the simplified SVPWM with voltage balancing, the algorithm is simpler, the switching losses is smaller, and it is easy to extend to cascaded H-bridge converters with more modules. Regarding the mutual-phase voltage balancing problem, the additional power generated by the zero-sequence voltage injection changes the power distribution among the three phases, so that the mutual-phase voltages is balanced. Finally, the effectiveness of the proposed control algorithm is verified by simulation and experimental results.

1 Introduction

In recent years, the energy storage technology has gradually become an indispensable component in the stable operation of smart grid with the development of renewable energy [1, 2]. Currently, with the development of energy storage technology in the direction of high voltage and high power, it is of great significance to study high-capacity multilevel energy storage power converters. There are more advantages of CHB topology compared to CHB and other multilevel topologies [3, 4]. The CHB topology is more suitable to be used as a high-power energy storage converters structure due to its modularity, expandability, ease of meeting higher voltage and capacity design requirements, and grid-connectivity without the need for an additional transformer.

The CHB energy storage converters consist of multiple identical modules in cascade, each module consists of an energy storage unit and a full-bridge structure, and the energy storage unit is generally a lithium iron phosphate battery, a lead-acid battery, a supercapacitor, etc. In this paper, supercapacitor is used as an energy storage unit, due to the faster response, higher power density and longer service life compared to battery energy storage [5, 6]. However, considering the differences in capacity and internal resistance as well as losses in the production process of supercapacitors [7]. This can cause an imbalance in the DC-side voltage between modules, as well as over-charging and over-discharging phenomena, which can seriously endanger the service life of supercapacitors. Therefore, the balancing of DC-side voltage is especially critical for the energy storage system, which is a prerequisite for the safe and stable operation of the system.

Inner-phase balancing and mutual-phase balancing controls are commonly employed for DC-side voltage balancing problems in three-phase CHB energy storage systems. For the inner-phase balancing, there are mainly two kinds of hardware balancing and software balancing. In [8], a hardware balancing control by adding a DC–DC link on the DC-side is proposed, which has good control effect, but it is complicated to control and costly. Software balancing is more common than additional hardware balancing control, and software balancing can be subdivided into two categories: indirect control and direct control of voltage balancing. In [9, 10], each module is added an independent voltage balancing PI link in its control section, which is simple and easily scalable. In [11], it is proposed to inject a compensating component to change the modulating waveform to redistribute the module power and reach the voltage balance on the DC-side of the module, which is easy to implement and low cost. The above literatures are all based on carrier phase shifting-sinusoidal pulse width modulation (CPS-SPWM) indirectly controlled voltage balancing approach, which essentially adjusts the modulating waveforms of each module through independent voltage balancing control algorithms and thus changes the duty cycle to achieve the purpose of inner-phase balancing. But, the voltage balancing capability of this type of approach is weak and increases the burden on the system controller due to independent voltage balancing algorithm. Meanwhile, the control parameters of the algorithm are numerous and difficult to select.

For this reason, in [12,13,14], voltage balancing using SVPWM method with direct voltage control is proposed. This method can achieve voltage balancing by using the selection of redundant vectors, which has the advantages of strong voltage balancing capability, high-voltage utilization and simple control. In [15,16,17], SVPWM algorithms in different coordinate systems and the principle of redundant vector generation are studied. In [18] and [19], 1D-SVPWM on a one-dimensional straight line and 2D-SVPWM in a two-dimensional plane were proposed, respectively, which attracted more scholars to study SVPWM with voltage balancing algorithms. In [20,21,22], 3D-SVPWM with voltage balancing algorithm for three-module cascaded converters is proposed, which puts all the voltage vectors into a three-dimensional space for analysis. The above SVPWM algorithms are all able to achieve voltage balancing by selecting vectors, but they do not consider the case of module port level leapfrog hopping and simultaneous action, which will increase the switching losses. Also, with the increase of the number of cascades, the number of vectors will increase dramatically and the algorithm will be more complicated.

The main methods are negative-sequence current injection and zero-sequence voltage injection for mutual-phase balancing problem. In [23], mutual-phase balancing based on negative-sequence current injection is proposed but affects the input-side power quality due to the injection of negative-sequence currents, which is detrimental to the safe operation of the grid. In [24], a combination of hybrid modulation strategy and zero-sequence injection method is proposed for mutual-phase power balancing control, which has lower total harmonic distortion (THD) of the grid-side currents after balancing, but the control is more complicated.

Therefore, an easily scalable SVPWM algorithm with voltage balancing based on simplified vector is proposed in this paper using a three-phase CHB energy storage converters as the study topology. And the problems of high switching losses in the above literature and the sharp increase in the number of voltage vectors with the increase in the number of cascades are overcome by this algorithm. At first, the algorithm simplifies the voltage vectors with the goal of strong voltage balancing capability and low switching losses and selects the output vectors according to the magnitude of the DC-side voltage. Moreover, the change of module level is minimal when the level changes, and leapfrog hopping of the module level is prevented. Then, the inner-phase voltage balancing can be achieved using the selection of vectors. After that, the zero-sequence voltage injection method is used to achieve mutual-phase balancing control for more complex problems of mutual-phase voltage control. Finally, the correctness of the proposed method is verified by simulation and experimental results.

2 Modeling and power control

2.1 Mathematical modeling of energy storage converters

The topology of the CHB energy storage converters is shown in Fig. 1. The three phases of this converter are connected in star-arrangement with each phase consisting of n modules in cascade, and it is connected to the AC grid through filter reactors. In Fig. 1, u_sa, u_sb, and u_sc are the three-phase grid voltages, u_a, u_b, and u_c are the three-phase output voltage of the converter, i_a, i_b and i_c are the three-phase current of the converter, L is the grid-side filter reactor, R is the equivalent losses, U_dca1, U_dca2, and U_dcan are the voltages of the supercapacitor of the energy storage unit, and C is the DC-side filter capacitance of the H-bridge of equal size. For example for phase A, U_a1b1, U_a2b2, and U_anbn are the output voltages of module 1, module 2, and module n, respectively, and the output phase voltage of the AC-side of phase A can be obtained as u_a = U_a1b1 + U_a2b2 + U_anbn. When the DC-side voltage of the CHB converter is balanced, i.e., U_dca1 = U_dca2 = U_dcan = U_dc, different switch combinations can be used, and the phase voltage u_a will have $2n + 1$ levels from $- n \cdot U_{dc}$ to $n \cdot U_{{{\text{dc}}}}$.

Fig. 1

Topology of a cascaded H-bridge energy storage converters

The upper and lower switching devices operate in complementary states, for a single H-bridge module. Take the i-th module of phase A as an example, define the switching function S_ai as:

$$ S_{ai} = \left\{ {\begin{array}{*{20}l} 1 \hfill & {(S_{{{\text{ai}}1}} ,S_{{{\text{ai}}4}} {\text{ ON}})} \hfill \\ 0 \hfill & {((S_{{{\text{ai}}1}} ,S_{{{\text{ai}}3}} {\text{) or }}(S_{{{\text{ai}}2}} ,S_{{{\text{ai}}4}} ){\text{ ON)}}} \hfill \\ { - 1} \hfill & {(S_{{{\text{ai}}2}} ,S_{{{\text{ai}}3}} {\text{ ON}})} \hfill \\ \end{array} } \right. $$

(1)

where $i = 1 \sim n$.

Then, the mathematical model of the CHB energy storage converters in the abc three-phase stationary coordinate system is obtained as:

$$ \left\{ \begin{gathered} L\frac{{di_{a} }}{dt} = u_{sa} - i_{a} R - \sum\limits_{i = 1}^{n} {S_{{{\text{ai}}}} } U_{{{\text{dc}}}} \hfill \\ L\frac{{di_{b} }}{dt} = u_{sb} - i_{b} R - \sum\limits_{i = 1}^{n} {S_{bi} } U_{{{\text{dc}}}} \hfill \\ L\frac{{di_{c} }}{dt} = u_{sc} - i_{c} R - \sum\limits_{i = 1}^{n} {S_{ci} } U_{{{\text{dc}}}} \hfill \\ \end{gathered} \right. $$

(2)

where U_dc is the supercapacitor output voltage when each module is balanced.

2.2 System power control

The various physical quantities to be determined for the time-varying alternating current due to the abc three-phase stationary coordinate system, which is more complex to analysis. Thus, the mathematical model under the abc coordinate system is converted by coordinate transformation to under the dq-axis synchronous rotating coordinate system, as in Eq. (3):

$$ \left\{ \begin{gathered} L\frac{{di_{d} }}{dt} = u_{sd} - Ri_{d} - U_{{{\text{dc}}}} S_{d} + \omega Li_{q} \hfill \\ L\frac{{di_{q} }}{dt} = u_{sq} - Ri_{q} - U_{{{\text{dc}}}} S_{q} - \omega Li_{d} \hfill \\ \end{gathered} \right. $$

(3)

where u_sd, u_sq and i_d, i_q and S_d, S_q denote the state quantities of the three-phase grid voltage and grid current and switching function of the AC-side in the dq coordinate system, respectively.

Neglecting the three-phase circuit equivalent losses and decoupling i_d and i_q to achieve independent control of active and reactive power, the system power control block diagram of the CHB converters can be obtained, as shown in Fig. 2. P^* and Q^* are given for active and reactive power, and then, the reference voltage signals v_d and v_q in dq coordinate system are obtained through the current inner loop decoupling control; then, the output voltage modulated waveforms v_a^*, v_b^* and v_c^* in abc coordinate system are obtained through the inverse Park’s transformation. Finally, the SVPWM algorithm with voltage balancing based on simplified vector can be used to obtain PWM signals, which can be distributed to each module to complete the overall control of the system.

Fig. 2

Power control block diagram of the energy storage converter system

3 SVPWM algorithm with voltage balancing based on simplified vector

3.1 Principle of SVPWM algorithm with voltage balancing

For a multilevel converter, each of its phase outputs can output a multilevel phase voltage with different phases and the same level. The phase voltage u_a as the reference phase can be compared to a reference vector $\vec{V}$, whose Y-axis is always zero, and its trajectory is plotted in a planar diagram. The principle of the three-module seven-level CHB, for example, is shown in Fig. 3, assuming that the voltage on the DC-side of the converter is balanced. In Fig. 3, the seven-level [− 3U_dc, − 2U_dc], [− 2U_dc, − U_dc], [− U_dc, 0], [0, U_dc], [U_dc, 2U_dc], and [2U_dc, 3U_dc] intervals are denoted as the R₁, R₂, R₃, R₄, R_5, and R₆ regions, respectively. When $\vec{V}$ is moving in the positive half-axis of the X-axis, the corresponding phase voltage is positive, and its modulus represents the proportion of time that it acts in a given region (how long the vector operates in a given region is equal to the amount of time the phase voltage acts in that level interval). The motion of $\vec{V}$ running from 0 increasing to 3U_dc and then decreasing to 0 is equivalent to the period when the phase voltage is positive. The principle is the same when the vector moves in the negative half-axis of the X-axis as when the vector is in the positive half-axis of the X-axis.

Fig. 3

Schematic diagram of SVPWM algorithm with voltage balancing for A-phase seven-level

Specifically, it is sufficient to determine that the reference vector $\vec{V}$ is running in a certain region, and output the level of that region. Assuming that the vector $\vec{V}$ is running in the R₄ region, this causes the system to issue commands for levels 0 and U_dc. The principles for phases B and C are the same as for phase A.

3.2 Calculation of leveling time

Taking the A-phase three-module cascade as an example, let the output phase voltages be -3U_dc, − 2U_dc, − U_dc, 0, U_dc, 2U_dc, and 3U_dc with the action times T_a−3, T_a−2, T_a−1, T_a0, T_a1, T_a2, and T_a3, and the switching period is T_s. When the reference vector $\vec{V}$ is in the interval of [0, U_dc], it can be obtained according to the volt-second balance:

$$ \left\{ \begin{gathered} T_{a0} \times 0 + T_{a1} U_{{{\text{dc}}}} = {\text{VT}}_{s} \hfill \\ T_{a0} + T_{a1} = T_{s} \hfill \\ \end{gathered} \right. $$

(4)

Then, T_a0 and T_a1 can be solved as shown in Eq. (5):

$$ \left\{ \begin{gathered} T_{a0} = \frac{{T_{s} }}{{U_{{{\text{dc}}}} }}(U_{{{\text{dc}}}} - V) \hfill \\ T_{a1} = \frac{{T_{s} }}{{U_{{{\text{dc}}}} }}V \hfill \\ \end{gathered} \right. $$

(5)

Similarly, the action time of $\vec{V}$ when it is in the region of R₁, R₂, R₃, R₄, R₅, and R₆ is shown in Table 1.

Table 1 Acting time of each level interval in phase A

The time allocation can be done after calculating the action time for each level interval, and a three-stage allocation is used in this paper. The R₁ to R₆ area allocation is the same, take R₅ as an example, as shown in Fig. 4. The carrier wave is a triangular wave, T_s is the carrier period, so the carrier amplitude is also T_s because of T_a1 + T_a2 = T_s. The smaller number of levels T_a1 is used as the modulating wave to compare with the carrier wave. The control signal T_PWM is 0 and outputs the U_dc level when the modulating wave is greater than or equal to the carrier wave. The control signal T_PWM is 1 and outputs the 2U_dc level, when the modulating wave is smaller than the carrier wave.

Fig. 4

Three-segment vector distribution diagram for the R₅ region

3.3 Principles of optimization for simplified vector algorithms

Knowing that each module can output a total of three states of 1, 0, and − 1, which correspond to three levels of U_dc, 0, and − U_dc, respectively, the A-phase three-module cascade converters can output 27 voltage vectors. Taking the output level number U_a1b1/U_dc of the first module of phase A as L_a1 axis, the output level number U_a2b2/U_dc of the second module as L_a2 axis, the output level number U_a3b3/U_dc of the third module as L_a3 axis, the total phase voltage output level number is L_a, then:

$$ L_{a} = L_{a1} + L_{a2} + L_{a3} $$

(6)

where L_a, L_a1, L_a2, and L_a3 are integers and L_a $\in [ - 3,3]$.

All the voltage vectors are located in the three-dimensional space of L_a1, L_a2, and L_a3 axes and form a cube, and the vector points with equal values of L_a can form a tangent plane, and the coordinate origin (0, 0, 0) is located in the center of gravity of the cube. Therefore, the A-phase seven-level converter space voltage vector diagram can be established, as shown in Fig. 5. It can be seen that the equal values of L_a are redundant vectors, which have the same output level but different voltage balancing effects; there are 27 voltage vectors distributed in a total of seven cuts of L_a = − 3, − 2, − 1, 0, 1, 2, 3, and the region between every two cuts corresponds to the level intervals and regions defined in Fig. 3. Where the voltage vector is not only at the boundaries of the cuts but also at the inner center of the cuts when L_a = 0, that is, the center of gravity of the cube.

Fig. 5

A-phase seven-level converter space voltage vector diagram. a u_a ≥ 0, b u_a ≤ 0

From Fig. 5, it can be seen that the number of voltage vectors is large, and with the increase of the number of cascades, the voltage vectors will increase more, which makes it very difficult to choose the optimal vector for voltage balancing. To solve this problem, this paper simplifies the voltage vectors with the goal of strong voltage balancing capability and low switching losses, so that the computational difficulty and switching losses are greatly reduced, and it is easier to extend to more number of cascaded converters.

3.3.1 Strong voltage balancing capability

The voltage of the supercapacitor energy storage converters can be balanced by varying the charging and discharging speeds when the optimal voltage balancing effect is the goal. Modules with large voltages are charged less and discharged more, modules with small voltages are charged more and discharged less, and modules with faster charging and discharging speeds in a certain time have more power input or output. Therefore, the charging and discharging speed of the module can be controlled indirectly by controlling the power on the DC-side, which in turn changes the DC-side voltage of each module.

Assuming ideal conditions, the power on the AC-side of the i-th module of phase A of the converter is equal to the power on the DC-side of the module:

$$ \left\{ \begin{gathered} P_{{{\text{ai}}}} = U_{{{\text{aibi}}}} i_{a} \cos \varphi \hfill \\ P_{{{\text{dcai}}}} = U_{{{\text{dcai}}}} i_{a} S_{ai} \hfill \\ P_{{{\text{ai}}}} = P_{{{\text{dcai}}}} \hfill \\ \end{gathered} \right. $$

(7)

where P_ai is the AC-side power of the i-th module of phase A, P_dcai is the DC-side power of the i-th module of phase A, φ is the power factor angle, and $i = 1 \sim 3$.

From Eq. (7), it can be seen that the module DC-side and AC-side currents are equal, and the AC-side voltage U_aibi can be changed to balance the DC-side voltage U_dcai of the module. Assuming that the R₄ region is initially (0, 0, 0) at a certain point in time, since the output in the R₄ region alternates between the 0 level and the U_dc level, if the U_dca1 voltage is to be increased at the next point in time, one of the three vectors (1, − 1, 1), (1, 0, 0), and (1, 1, − 1) on the AC-side can be selected for voltage balancing by selecting the U_dc level. Therefore, among the many vectors of the seven levels, the vector with high-voltage balancing capability represents the most input or output power and the largest input or output voltage on the AC side. It can be made that m is the voltage balancing capability as in Eq. (8):

$$ m = \left| {\frac{{U_{a1b1} + U_{a2b2} + U_{a3b3} }}{{U_{{{\text{dc}}}} }}} \right| > 0 $$

(8)

As L_a1 = U_a1b1/U_dc, L_a2 = U_a2b2/U_dc, L_a3 = U_a3b3/U_dc, therefore:

$$ m = \left| {L_{a1} + L_{a2} + L_{a3} } \right| > 0 $$

(9)

where m is a nonzero integer.

The larger m represents the strong voltage balancing capability, while the redundant vector at level 0 can be eliminated in a seven-level energy storage converter, but the internal voltage vector at level 0 should be retained in order for the converter to operate properly.

3.3.2 Low switching losses

Reduced switching times should be considered to prevent module level leapfrog hopping when aiming for low switching losses. For example, when in the R₄ region, a jump from level 0 (− 1, 0, 1) to level 1 (1, − 1, − 1) may occur; although the voltage balancing capability may be good, module 1 has undergone leapfrog hopping from a − U_dc level change to a U_dc level, and module 3 has undergone leapfrog hopping from a U_dc level change to a − U_dc level; And the three-module switching tubes will act at the same time, and the bridge arms need to be subjected to large voltage stress. Secondly, when the level of phase voltage changes, one of the three modules should be made to change the level of one of the modules, and the other two remain unchanged, to meet this requirement, can greatly reduce the switching losses. If the change from level 0 to U_dc level is initially (0, 0, 0), the next moment may be one of (0, 0, 1), (1, 0, 0), (0,1, 0) rather than one of (1, − 1, 1), (1, 1, − 1), (− 1, 1, 1).

Therefore, in combination with the goal of strong voltage balancing capability and low switching losses, (0, − 1, 1), (1, − 1, 0), (1, 0, − 1), (0, 1, − 1), (− 1, 1, 0), (− 1, 0, 1) should be removed at level 0 and (0, 0, 0) should be retained; at U_dc levels (− 1, 1, 1), (1, − 1, 1), (1, 1, − 1) should be removed; at − U_dc levels (− 1, − 1, 1), (1, − 1, − 1), (− 1, 1, − 1) should be removed; ± 2U_dc levels and ± 3U_dc levels are all retained. The 27 vectors in phase A can then be simplified to 15 vectors with strong voltage balancing capability, reducing the number of vectors by 44.4%, as shown in Fig. 6.

Fig. 6

Simplified vectorial A-phase seven-level space voltage vector diagrams. a u_a ≥ 0, b u_a ≤ 0

From Fig. 6(a), it can be seen that when L_a changes from 0 to 1 and 2 to 3, both are only one of the three modules level changes, and the change is 1, and there is no leapfrog hopping. Similarly, when L_a changes from − 1 to 0 and -3 to − 2, no leapfrog hopping occurs. And when L_a changes from 1 to 2 and − 2 to − 1, as shown in Table 2, there are 2/3 occurrences of only one module level change out of three modules, and the change is 1 and there is no leapfrog hopping, as shown in the second and third columns of Table 2; and there are 1/3 occurrences of three-module level changes, but with smaller chances of occurring and the change is 1 and there is no leapfrog hopping, as shown in the fourth column of Table 2.

Table 2 Voltage vector variation in the region of R₂ and R₅

The optimization principle of the simplified vector algorithm by analysis is:

• 1) It is necessary to keep the internal or boundary voltage vectors of the cut-outs for the system to function properly and to output the full level;

• 2) Screen the vectors with strong voltage balancing ability by substituting the boundary vectors in the remaining cuts into Eq. (9);

• 3) Prevent the module level leapfrog hopping, and when the level changes, one of the three modules should be made to change level and the other two should remain unchanged to reduce switching losses.

4 Inner-phase and mutual-phase DC-side voltage balancing control

4.1 Inner-phase DC-side voltage balancing control

According to Sect. 3.3, a total of 27 voltage vectors in phase A are simplified into 15 vectors with strong voltage balancing capability, and the DC-side voltage U_dcai of the balancing module is carried out by changing the AC-side voltage U_aibi. However, there are three voltage vectors at the output AC-side voltage of ± U_dc level and ± 2U_dc level, and the redundant voltage vectors at the same level can be considered to have different effects on the DC-side voltage. Then, the vector with stronger voltage balancing ability is selected to be different according to the DC-side voltage magnitude and input current direction. The voltage vectors at different output levels affect the DC-side voltage as shown in Table 3, where “↓” indicates a voltage decrease, “↑” indicates a voltage increase, and “ + ” indicates that the A-phase input current i_a is positive, and “−” indicates that the phase A input current i_a is negative.

Table 3 Effect of different voltage vectors in phase A on DC-side voltage

From Table 3, it can be obtained that there is only one vector at L_a = 0 and L_a =  ± 3 after simplifying the vectors, and there is no need to make a selection, which reduces the burden on the system. At L_a =  ± 1 and L_a =  ± 2, the selection of the optimal vector is made according to the voltage magnitude and current direction. Take the R₅ region as an example, the flowchart is shown in Fig. 7, when the A-phase output level L_a is located in the R₅ region.

Fig. 7

A-phase three-module inner-phase DC-side voltage balancing control flowchart. (R₅ area)

Firstly, the output U_dc level and 2U_dc level are determined by determining that it is located in the R₅ region based on the reference vector; then, T_a1 and T_a2 are calculated and time allocation is performed, and the operating level is determined to be either the U_dc level or the 2U_dc level based on the T_PWM generated by the time allocation, which can be assumed to be the following moments:

• 1) The voltage vector is (1, 0, 0) when L_a = 1 i.e., output U_dc level at moment t;

• 2) If i_a < 0 and U_dca2 is minimal at moment t + 1, the output (1, 0, 1) at L_a = 2 will decrease U_dca1 and U_dca3 according to Table 3;

• 3) If i_a < 0 and U_dca1 is maximal at moment t + 2, the output (1, 0, 0) at L_a = 1 will decrease U_dca1 according to Table 3;

• 4) If i_a > 0 and U_dca3 is maximum at moment t + 3, the output (1, 1, 0) at L_a = 2 will increase U_dca1 and U_dca2 according to Table 3.

It can be seen that the above moments are all three modules in which only one module level changes, and the change is 1, there is no leapfrog hopping, reducing the switching losses. And through the relationship between the current direction and the DC-side voltage magnitude, and then, select the voltage vector with strong voltage balancing ability, it can achieve fast voltage balancing. Secondly, the SVPWM algorithm with voltage balancing based on simplified vector reduces numerous redundant vectors and can be implemented with only a simple ordering and a few logic judgements. Hence, the burden on the system is small, the operation speed is fast, and it can be extended to H-bridge converters with much number of modules.

4.2 Mutual-phase DC-side voltage balancing control

The three-phase input voltage and current can be decomposed into positive-sequence, negative-sequence, and zero-sequence components according to the method of symmetrical components. The additional zero-sequence voltage does not affect the total output power of the system due to the star-arrangement of the system, and the zero sequence current is zero. Then, the additional power generated by injecting zero-sequence voltage can be used to change the power distribution between the three mutual phases, thus achieving mutual-phase voltage balancing.

In Fig. 1, the three-phase current of the energy storage converters can be made to be expressed as:

$$ \left\{ \begin{gathered} i_{a} = \sqrt 2 I\cos (\omega t + \delta_{i} ) \hfill \\ i_{b} = \sqrt 2 I\cos (\omega t - \frac{2\pi }{3} + \delta_{i} ) \hfill \\ i_{c} = \sqrt 2 I\cos (\omega t + \frac{2\pi }{3} + \delta_{i} ) \hfill \\ \end{gathered} \right. $$

(10)

where I is the three-phase current RMS value, δ_i is the initial phase of the current.

Then, the additional fluctuating power in the three phases generated by the zero-sequence voltage is:

$$ \left\{ \begin{gathered} P_{a0} = U_{0} I{\text{cos}}(\theta_{0} - \delta_{i} ) \hfill \\ P_{b0} = U_{0} I{\text{cos}}(\theta_{0} - \delta_{i} - \frac{2\pi }{3}) \hfill \\ P_{c0} = U_{0} I{\text{cos}}(\theta_{0} - \delta_{i} + \frac{2\pi }{3}) \hfill \\ \end{gathered} \right. $$

(11)

where P_a0, P_b0, and P_c0 are the three-phase additional fluctuation power generated by the zero-sequence voltage, U₀ is the rms value of the zero-sequence voltage, and θ₀ is the phase angle of the zero-sequence voltage.

Making the sum of the DC-side voltages of each module of the three-phase cascade of a, b, and c of the CHB energy storage converters as shown in Fig. 1 to be U_dca, U_dcb, and U_dcc, respectively, the average values of the DC-side voltages of each module of each phase, U_ava, U_avb, and U_avc, are:

$$ \left\{ \begin{gathered} U_{ava} = U_{{{\text{dca}}}} /n \hfill \\ U_{avb} = U_{{{\text{dcb}}}} /n \hfill \\ U_{avc} = U_{{{\text{dcc}}}} /n \hfill \\ \end{gathered} \right. $$

(12)

The average value of the DC-side voltage U_dcav of each module of the three phases is:

$$ U_{{{\text{dcav}}}} = \frac{1}{3}(U_{ava} + U_{avb} + U_{avc} ) $$

(13)

The deviation values of U_ava, U_avb, U_avc, and U_dcav are defined as ∆U_dca, ∆U_dcb, and ∆U_dcc:

$$ \left\{ \begin{gathered} \Delta U_{{{\text{dc}}a}} = U_{ava} - U_{{{\text{dcav}}}} \hfill \\ \Delta U_{{{\text{dc}}b}} = U_{avb} - U_{{{\text{dcav}}}} \hfill \\ \Delta U_{{{\text{dc}}c}} = U_{avc} - U_{{{\text{dcav}}}} \hfill \\ \end{gathered} \right. $$

(14)

Equation (14) reflects the mutual-phase DC-side voltage of the CHB energy storage converters degree of imbalance.

As the DC-side voltage unbalance between the three phases ∆U_dca, ∆U_dcb, and ∆U_dcc determines the size of the additional fluctuation power P_a0, P_b0, and P_c0 injected into each phase during mutual-phase voltage balancing. So, the degree of voltage unbalance is proportional to the additional fluctuation power injected into each phase, as in Eq. (15), with the proportionality coefficient k.

$$ \left\{ \begin{gathered} P_{a0} = k \cdot \Delta U_{{{\text{dca}}}} \hfill \\ P_{b0} = k \cdot \Delta U_{{{\text{dcb}}}} \hfill \\ P_{c0} = k \cdot \Delta U_{{{\text{dcc}}}} \hfill \\ \end{gathered} \right. $$

(15)

By associating Eqs. (11), (14), and (15), the RMS value of the injected zero-sequence voltage U₀ and the phase angle θ₀ required for mutual-phase balance can be found:

$$ \left\{ \begin{gathered} U_{0} = \frac{{k\sqrt {\frac{2}{3}(\Delta U_{{{\text{dca}}}}^{2} + \Delta U_{{{\text{dcb}}}}^{2} + \Delta U_{{{\text{dcc}}}}^{2} )} }}{I} \hfill \\ \theta_{0} = \delta_{i} - \lambda \hfill \\ \end{gathered} \right. $$

(16)

where λ is:

$$ \lambda = \left\{ {\begin{array}{*{20}l} {\tan^{ - 1} \frac{{\Delta U_{{{\text{dc}}\beta }} }}{{\Delta U_{{{\text{dc}}\alpha }} }}} \hfill & {\Delta U_{{{\text{dc}}\alpha }} \ne 0} \hfill \\ {\frac{\pi }{2}} \hfill & {\Delta U_{{{\text{dc}}\alpha }} = 0\& \Delta U_{{{\text{dc}}\beta }} > 0} \hfill \\ { - \frac{\pi }{2}} \hfill & {\Delta U_{{{\text{dc}}\alpha }} = 0\& \Delta U_{{{\text{dc}}\beta }} < 0} \hfill \\ \end{array} } \right. $$

(17)

The ∆U_dcα and ∆U_dcβ in Eq. (17) indicate that Eq. (14) is converted from the abc three-phase stationary coordinate system to the αβ two-phase stationary coordinate system for the convenience of computation, as shown below:

$$ \begin{gathered} \left[ \begin{gathered} \Delta U_{{{\text{dc}}\alpha }} \hfill \\ \Delta U_{{{\text{dc}}\beta }} \hfill \\ \end{gathered} \right] = \sqrt{\frac{2}{3}} \left[ \begin{gathered} \begin{array}{*{20}c} 1 & { - \frac{1}{2}} & { - \frac{1}{2}} \\ \end{array} \hfill \\ \begin{array}{*{20}c} 0 & {\frac{\sqrt 3 }{2}} & { - \frac{\sqrt 3 }{2}} \\ \end{array} \hfill \\ \end{gathered} \right]\left[ \begin{gathered} \Delta U_{{{\text{dca}}}} \hfill \\ \Delta U_{{{\text{dcb}}}} \hfill \\ \Delta U_{{{\text{dcc}}}} \hfill \\ \end{gathered} \right] \\ = \left[ \begin{gathered} \sqrt{\frac{3}{2}} \Delta U_{{{\text{dca}}}} \hfill \\ \sqrt{\frac{1}{2}} (\Delta U_{{{\text{dcb}}}} - \Delta U_{{{\text{dcc}}}} ) \hfill \\ \end{gathered} \right] \\ \end{gathered} $$

(18)

Note that the larger the proportionality coefficient k, the larger the rms value of the zero-sequence voltage, and the larger its additional power, the more efficient the mutual-phase power balance of the energy storage converters will be. But, k must not be too large, it will affect the safe operation of the system due to too large will cause the system output voltage and current to produce large distortion.

The block diagram of mutual-phase DC-side voltage balancing control based on zero-sequence voltage injection method can be obtained from the above analysis, as shown in Fig. 8. It consists of two parts: system power control and zero-sequence voltage injection. The system power control has been introduced in Sect. 2.2, and its main function is to control the power of the storage converter to produce three-phase voltage modulated waves v_a^*, v_b^*, and v_c^*. The zero-sequence voltage injection module obtains the required zero-sequence voltage RMS value U₀ and the phase angle θ₀ by calculating, and the injection of the zero-sequence voltage component U₀ can change the power distribution among the three phases, making the mutual-phase DC-side voltage balancing. The three-phase modulating voltages v_a^*, v_b^*, and v_c^* are superimposed with the zero-sequence voltage component U₀ to obtain the final modulating wave voltages v_a^*ʹ, v_b^*ʹ, and v_c^*ʹ.

Fig. 8

Block diagram of mutual-phase DC-side voltage balancing control by zero-sequence voltage injection method

5 Simulation and experimentation

5.1 Simulation analysis

The three-module CHB energy storage converter simulation model is built based on Matlab/Simulink for analysis, in order to verify the inner-phase voltage balancing of the SVPWM algorithm with voltage balancing based on simplified vectors, as well as the mutual-phase voltage balancing effect of the zero-sequence voltage injection method. Setting the initial supercapacitor voltage of each module in each phase during charging and discharging is not equal to verify the inner-phase balance, and setting the initial supercapacitor voltage between the three phases is not equal to verify the mutual-phase balance, the main simulation parameters are shown in Table 4.

Table 4 Main simulation parameters for charging and discharging of energy storage converters

5.1.1 Inner-phase voltage balancing

The waveforms of the A-phase grid-side voltage, current, and three-phase grid-side current for verifying the DC-side voltage balancing in inner-phase are shown in Fig. 9. It can be seen that in Fig. 9a, the voltage is in the same phase as the current when charging at a given power, which enables the storage of power, and in Fig. 9b, the voltage is 180º out of phase with the current when discharging, which enables the release of power. And the three-phase AC currents of charging and discharging are still symmetrical when the initial voltages of supercapacitors of each module are unequal, and the voltage balancing algorithm of the simplified vector will not affect the three-phase AC current output.

Fig. 9

A-phase grid-side voltage-current and three-phase current waveforms: a charging and b discharging

The DC-side voltage waveform of each module in abc three-phase using the SVPWM algorithm with voltage balancing based on simplified vector is shown in Fig. 10. It can be seen, taking phase A as an example, that the energy storage unit with a large initial value voltage during charging charges at the slowest rate, and the energy storage unit with a small initial value voltage charges at the fastest rate. At last, it charges at the same rate at 0.72 s with decreasing degree of imbalance. Then, the rate of discharge is reversed to that of charging, and the eventual balance is reached at 0.48 s. Although the initial values of the voltages of each energy storage unit in each phase are set to be different, the voltages can still be balanced in a short time, and the charging and discharging can be carried out at the same charging rate. This proves that the proposed inner-phase voltage balancing algorithm has a strong voltage balancing capability.

Fig. 10

Voltage on the DC-side of each three-phase module under in-phase balance: a charging and b discharging

Figure 11 shows the comparative analysis of the DC-side voltage of each module in three phases during charging under inner-phase balance. From the figure, it can be seen that the three-phase DC-side voltage of the traditional method takes about 0.65 s, 0.64 s, and 0.585 s to reach balance from unbalance, respectively; and the three-phase DC-side voltage of the proposed method takes about 0.7 s, 0.685 s, and 0.635 s to reach balance from unbalance, respectively. Both the proposed method and the traditional method can reach balance in short time, and the voltage balance of the proposed method is a little slower than that of the traditional method (< 0.05 s).

Fig. 11

Voltage on the DC-side of each module in three-phase during charging in inner-phase balance: a traditional 3D-SVPWM method and b proposed method

Figure 12 shows the voltage waveforms of each module port in phase A during charging under converter voltage unbalance. It can be seen that there is leapfrog hopping in the levels of modules 1, 2, and 3 under the traditional 3D-SVPWM method in Fig. 12a, and there is also a simultaneous change in the levels of the three modules when the level of the A-phase output voltage u_a changes. Since the vectors are not simplified, the module moves more frequently and the switching losses are higher. And because the initial supercapacitor voltages of modules 1, 2, and 3 are 60 V, 80 V, and 100 V, respectively, when setting up A-phase charging, module 1 needs to charge faster to get more power to maintain balance, followed by module 2 and finally module 3. Therefore, module 1 needs to have a high level to get more power and maintains the + 1 level when i_a > 0 in Fig. 12a. However, there still exists a situation that all three module levels change at the same time when the level changes under the non-simplified vectors, such as at voltage amplifica-tion (1) and (2) in Fig. 12a.

Fig. 12

Voltage waveforms of each module port in phase A during charging under voltage unbalance: a traditional 3D-SVPWM method and b proposed method

The port voltage of each module in phase A under the proposed method is shown in Fig. 12b. It can be seen that there is no leapfrog hopping in each module when the u_a level changes, presenting a step wave, and only one of the three modules has a change in level. It is indicated that the switching devices of each module of the converter under the SVPWM algorithm with voltage balancing based on simplified vector have fewer actions, low voltage stress, and small switching losses.

In addition, in order to further verify the advantages of the proposed method over the traditional method in terms of system switching loss, the average value of the number of switching actions for 3 cycles after 0.3 s is counted by simulation in Fig. 13, taking the converter A-phase as an example. It can be seen from the figure that although the number of switching actions in the first module A1 in phase A using the proposed method is slightly more than the traditional 3D-SVPWM with voltage balancing method. But, the number of switching actions in the other modules and the total number of switching actions in phase A is reduced by about 50% compared to the traditional method, which significantly reduces the switching losses.

Fig. 13

Number of A-phase switching actions

According to the comparison between the traditional 3D-SVPWM algorithm with voltage balancing and the proposed algorithm in Table 5, it can be seen that the proposed algorithm has the following advantages over the traditional algorithm. First, the proposed algorithm reduces the number of voltage vectors used in a single phase by 44.4%, which makes the system less burdensome and easy to expand to more modules in cascade. Second, compared with the traditional algorithm, the proposed algorithm greatly reduces the switching losses; and the network side current THD is also smaller.

Table 5 Comparison of traditional 3D-SVPWM algorithm with voltage balancing and the proposed algorithm

5.1.2 Mutual-phase voltage balancing

Figure 14 shows the analysis of three-phase DC-side voltage, injected zero-sequence voltage, three-phase grid-side current, and grid-side current THD under mutual-phase balance after adding inner-phase balance. It can be seen that the mutual-phase voltage balancing in Fig. 14a cannot be achieved when charging without injecting zero-sequence voltage and there is a deviation value. The mutual-phase balancing starts after the injection of the zero-sequence voltage at 1 s. As the zero-sequence voltage decreases, the degree of unbalance between the three mutual-phases decreases, and eventually charges at the same rate at 1.8 s. Figure 14b shows the mutual-phase balancing by injecting the zero-sequence voltage at 0.6 s during discharge, and the balancing is achieved at 1.4 s as the zero-sequence voltage decreases. Also, the mutual-phase cannot be balanced automatically when it is not injected. Moreover, the three-phase grid-side current does not change when the zero-sequence voltage is injected at 1 s and 0.6 s. It means that zero-sequence voltage injection does not affect the output of three-phase grid-side current, which verifies the feasibility and correctness of the zero-sequence voltage injection method. The grid-side currents are analyzed for THD after both inner-phase and mutual-phase are balanced. From the THD analysis of the grid-side currents in Fig. 14a and b, it can be seen that the grid-side current during charging: THD = 1.06%, and the grid-side current during discharging: THD = 0.91%, both of which are less than 2% and satisfy the national requirement of less than 5% of the grid entry.

Fig. 14

Simulation results under mutual-phase balance: a charging and b discharging

5.2 HIL experimental verification

A hardware-in-the-loop (HIL) experimental platform as shown in Fig. 15 is built to further verify the feasibility of the simulation results. It mainly provides HIL experimental verification of the proposed SVPWM algorithm with voltage balancing based on simplified vector for inner-phase voltage balancing as well as the zero-sequence voltage injection method for mutual-phase voltage balancing. Among them, the main circuit is built in the Typhoon HIL402 platform, the HDSP-DF28335P controller is used to output pulses, and the harmonic distortion rate of the grid-side currents is analyzed by using the HIOKI power quality analyzer PQ3198. The main parameters of the HIL experiment are consistent with the simulation parameters in Table 4.

Fig. 15

HIL experimental platform

Figure 16 shows the HIL experimental waveforms of phase A under inner-phase balance, which shows that the voltage and current are in the same phase in Fig. 16a for charging, and the voltage and current are 180º out of phase in Fig. 16b for discharging. The experimental waveforms are consistent with the simulation results, and the storage and release of power are achieved. When charging, with the addition of SVPWM algorithm with voltage balancing based on simplified vector, it finally reaches balance at 0.8 s. When discharging, with the decrease of the degree of imbalance, it reaches balance at 0.5 s, and finally charging and discharging at the same rate, which verifies that the inner-phase voltage balancing algorithm proposed in this paper has a strong voltage balancing capability.

Fig. 16

HIL experimental waveforms of phase A under inner-phase balance: a charging and b discharging

The HIL experimental waveforms of the port voltage and phase voltage of each module in phase A during charging under converter voltage unbalance are shown in Fig. 17. It can be seen that Fig. 17a under the traditional 3D-SVPWM method exists a situation in which the levels of the three modules change at the same time when the phase voltage u_a level changes, and level leapfrog hopping occurs in all three modules. And under the simplified vector in Fig. 17b, each module did not show the level leapfrog hopping when the phase voltage u_a level changes. In addition, the output voltage of only one module unit among three module units has one level change, which is the same as the simulation results, verifying that the proposed algorithm has small switching losses.

Fig. 17

Waveforms of each module port voltage and phase voltage in phase A during charging under voltage unbalance: a traditional 3D-SVPWM method and b proposed method

The average value of computing time for the proposed method and the traditional method calculated in the HIL platform is shown in Fig. 18. It can be seen from Fig. 18 that the algorithm computation time of the traditional method is 19.18 μs, which accounts for 27.4% of the control cycle, and the algorithm computation time of the proposed method is 13.51 μs, which accounts for 19.3% of the control cycle. The proposed method reduces 5.67 μs and enhances the operation speed by about 30% compared to the traditional method. This shows that the proposed simplified vectors algorithm can effectively reduce the computing burden of the controller and improve the response speed of the system.

Fig. 18

Algorithmic computation time

Figure 19 shows the HIL experimental waveforms of mutual-phase voltage balancing without adding zero-sequence voltage injection and mutual-phase voltage balancing with adding zero-sequence voltage injection, as well as the THD analysis of the grid-side currents. The supercapacitor voltages of the first module in the three phases of A, B, and C are selected for the analysis because only four waveforms can be observed at one time by the TBS 2000X SERIES oscilloscope. It can be seen that in Fig. 19a charging without adding the mutual-phase balance of zero-sequence voltage injection, it does not reach the balance automatically, while with the addition of the mutual-phase balance, it reaches the balance at 1.3 s. In Fig. 19b, the discharging is consistent with the charging, and finally balance at 0.8 s. Then, the THD of the grid-side current is 1.69% and 1.87%, respectively, after charging and discharging balance, both are less than 2% and meet the national requirement of less than 5% for grid entry.

Fig. 19

Mutual-phase balance HIL experimental waveforms and grid-side current THD analysis diagrams: a charging and b discharging

6 Conclusion

A SVPWM algorithm with voltage balancing based on simplified vector is proposed in this paper for the converter inner-phase voltage balancing with CHB energy storage converters as the research background, which overcomes the problems of larger number of voltage vectors and higher switching losses. Firstly, the algorithm carries out simplification of voltage vectors by targeting strong voltage balancing capability and low switching losses and simplifies a total of 27 voltage vectors to 15 vectors in a single phase of a conventional SVPWM with voltage balancing, which is a reduction of 44.4% of the vectors. It makes the algorithm simpler, the system burden smaller, and it is easier to extend to cascaded H-bridge converters with more modules. Besides, the algorithm prevents the occurrence of leapfrog hopping in the level of each module and makes only one level change in one module when the phase voltage level changes, which greatly reduces switching losses. Finally, the additional power generated by zero-sequence voltage injection is used to change the distribution of power among the three phases, thus changing the charging and discharging speeds of the three-phase energy storage units, so that the mutual-phase voltage is balanced. The THD of the charging and discharging grid-side currents meets the requirements for grid-connection after both inner-phase and mutual-phase voltages are balanced. It is verified by the simulation and experimental results that the proposed control algorithm is correct.