1 Introduction

Advanced packaging is becoming a more viable option for high-performance devices. For example, fan-out wafer-level packaging (FOWLP) can fulfill the demand for multifunctionality, increased input/output count, smaller form factors, and cost reduction. However, compared with conventional packaging technologies, FOWLP requires greater coplanarity of the die and wafer [1,2,3], introducing new obstacles to achieving sufficient coplanarity in the original wafer processing, such as requiring control of the Cu pillar height and the thickness of the Si.

Cu pillar technology is used to connect a device to the redistribution layer or to other devices in advanced packaging and 3D/2.5D integration [3,4,5,6]. A Cu pillar is usually formed by electrodeposition during the semi-additive process. The height of a plated Cu pillar is typically a few tens of microns, which means it cannot be planarized by polishing afterward. Therefore, the height uniformity and the surface flatness of the Cu pillar are determined by the Cu electrodeposition process. The height uniformity directly affects the yield of electrical connections of pillars. Nevertheless, the height uniformity can vary if the electrodeposition step is not fully optimized for the pillar structure, which cannot subsequently be adjusted using conventional processes.

The Si bulk removal process plays an equally important role in maintaining the coplanarity of advanced packaging. The Si bulk removal process is usually carried out via a diamond-abrasive grinding process [7]. Si grinding, especially analyses of the removal mechanism, has been investigated for decades [8, 9]. Numerous novel approaches to achieving a high removal rate have recently been reported [10,11,12,13,14]. Nevertheless, further improvements in the thickness variation remain a common challenge in the device manufacturing process. For the Si removal process, minimizing the total thickness variation (TTV) of Si on the die and that of the wafer is also critical for high-accuracy thermal compression bonding, along with die placement on a carrier wafer with temporary glue for epoxy molding [3, 15, 16]. A surface protection system is required during backside thinning of the wafer [17,18,19,20]. Otherwise, the wafer surface will directly contact the chuck of the grinder. Contact between the chuck and the top surface of the wafer can introduce contaminants and mechanical stress onto the front side of the wafer. In addition, the thinned wafer becomes flexible and fragile. Furthermore, the surface topographic features of the wafer surface, such as pillars and microbumps, prevent the wafer from being held by vacuum on the chuck table of the grinding tool. Lamination of the from side using ultraviolet (UV)-releasable backgrind (BG) tape is comprehensively used to provide wafer support during the wafer thinning process. However, the tape tends to follow the surface topography, eventually leading to a large TTV of the wafer and tape. Because coplanarity between the chuck, wafer (workpiece), and wheel is key to maintaining a good TTV of the Si after grinding, the incoming thickness variation of the wafer must be minimized.

In the present study, we introduce a method to minimize the variation of the Cu pillar height and Si thickness using a surface planer process. The creep-feed fly-cut process (i.e., the so-called “surface planer” process) can create submicron-level coplanarity on the cutting surface and wafer bottom via the copying principle of the mechanical machine [21,22,23,24,25,26,27,28,29]. The manufacturing process with a surface planer was investigated to mitigate both the nonuniformity of the Cu pillar and the TTV of the Si after thinning. For Cu pillar planarization, the plated Cu pillar and the plating photoresist (PR) were planarized simultaneously (Fig. 1a). To control the Si thickness during thinning, the UV-releasable BG tape deformed by the surface Cu pillar was planarized before grinding to mitigate the original topography (Fig. 1b).

Fig. 1
figure 1

Schematics of (a) Cu pillar planarization and (b) backgrind tape planarization

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2 Experimental details

All wafer-scale processes were carried out using 300-mm Si wafers as the substrate. The original thickness of the Si wafers was 775 µm. The die size in the pillar mask pattern was 5.2 mm × 5.2 mm (2332 active dies in a 300-mm wafer). A passivation layer (50 nm SiN) was deposited onto the Si substrate. A 30 nm TiW barrier layer and a 150 nm Cu conductive seed layer were deposited by physical vapor deposition (PVD). Then, a 60 µm photoresist was coated and patterned onto the PVD Cu seed layer. The critical dimension of the pillars on the photoresist was 50 µm. The open area of the pillar mask in design was 11.69%. The total number of pillars in one die was 1610. After the photoresist was descummed and the Cu seed layer was exposed, Cu was electrochemically deposited onto the exposed area of the photoresist. The plating tool used in the experiment was a vertical wafer holder with an agitation system (Nexx Stratus P300). The Cu chemistry consisted of an acid–base virgin makeup solution containing the Copper Gleam PC additive from DuPont. The current density used for pillar plating was − 20 mA/cm2. The target height of the Cu was 50 µm.

Planarization was carried out using a creep-feed surface planer machine (DAS8930 from Disco). Details of the process conditions and a schematic of the surface planer process are available elsewhere [21]. A diamond single crystal was used for the cutting process. The diamond was fixed onto a shank, and the shank was placed on a spindle. To maintain good balance on the spindle, a dummy shank was placed on the opposite side (180°) of the spindle. The diameter of the spindle was 320 mm. The processed wafer was held face-up on the vacuum chuck table. The cutting sequence consisted of a rough cut (high feed rate) and a final fine cut (low feed rate). The target height of the photoresist and Cu pillar after the planarization was 42 µm. The pillar height was measured using a CAMTEK Falcon 630 Plus optical system. The width of the edge exclusion was 5 mm from the bevel. Surfaces were inspected using a scanning electron microscope and an optical profiler. The photoresist, Cu seed, and TiW on the field were then removed by wet chemical etching. HT-260PG-UR10-PH2 was laminated onto the wafer’s front side (pillar side) as the BG tape. The total thickness of the tape was 260 µm, where the base film was 50 µm. The grinding step was carried out using an in-feed abrasive grinder equipped with rough and fine wheels [30,31,32,33]. During the grinding process, the BG tape was made to contact the chuck table by a vacuum. The thickness of the Si wafer after grinding was measured by laser interferometry.

3 Results and discussion

3.1 Pillar planarization

In the wafer plating tool, the current is applied and distributed from the wafer edge via the metal contact of the wafer holder. Therefore, the pillar tends to be higher at the wafer edge than at the center. Figure 2a shows the pillar height distribution allocated in the whole wafer map. Immediately after the Cu plating, the mean value of the pillar height was 48.0 µm. The tallest pillar was 57.3 µm high, and the shortest was ~ 42.1 µm. The within-wafer (WiW) uniformity was calculated as follows:

Fig. 2
figure 2

The Cu pillar height distribution in a 300-mm wafer. The Cu pillar height was extracted as the mean height of a die. (a) Wafer map after the plating process. (b) Wafer map after the surface planer process. (c) Radius distribution after the plating and surface planer processes

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$$WiW \left[\%\right]=\frac{H{\text{h}}-H{\text{l}}}{H{\text{m}}}\times 100$$
(1)

where Hh is the 95% highest pillar height, Hl is the 5% lowest pillar height, and Hm is the mean height of all pillars. From this calculation, the WiW uniformity after the plating was 24.6%. Because the plating chamber was not optimized for the pillar plating, the uniformity exceeded the best performance of the plating tool. After the plating, the hardware, chemistry, anode shield, and agitation were optimized, and the uniformity was < 7%.

The pillar height before and after the surface planer process cannot be measured for the same wafer because the pillar height can only be measured by the optical method after the resist has been stripped. However, if the resist is stripped, the surface planer process will differ from the actual situation. Therefore, the surface planer process was applied to a different wafer obtained from the same lot as the wafer whose height was measured in Fig. 2a. All wafers in a lot were subjected to exactly the same plating process, and the wafers used in the present work were from the same lot. Thus, the pillar height after plating should be equivalent for the wafers in Fig. 2a, b. Figure 2b shows the pillar height distribution allocated in the whole wafer map after the surface planer process. The tallest pillar after the surface planer process was 44.0 µm, and the shortest was 41.0 µm. The WiW uniformity after the surface planer process was 3.5%. The surface planer process was carried out immediately after the plating process, without stripping of the photoresist. That is, the removal process was simultaneously carried out on the photoresist and Cu pillars. Approximately 18 µm of the photoresist was removed by the surface planer process. The amount removed by the fine cut was 1 µm. In a previous study, we found that the photoresist was not a good support material for the planarization of fine-pitch microbumps [21]. However, the dimensions of the pillars in the present study are much larger than those of the microbumps we reported previously [21]. Peeling stress and plastic deformation should occur only at the top of the pillars. Figure 2c shows the pillar height distribution plotted with respect to the radius position of the wafer both after plating and after the surface planer process. The WiW nonuniformity of the pillar height after plating was reduced by the surface planer process; that is, the pillar height was made uniform.

The WiW uniformity strongly influences the subsequent process. In addition, the within-die (WiD) uniformity is an equally important parameter for the packaging process (e.g., for die thermal compression bonding and die placement on the carrier wafer). Therefore, we also calculated the WiD uniformity by measuring all of the pillars in a die before and after the surface planer process. Figure 3 shows a box plot of pillar height coplanarity in a die in a wafer. The coplanarity was obtained by subtracting the highest pillar height from the lowest pillar height in a die. All of the measured dies in a wafer are plotted in the box chart. The mean value of the coplanarity in a die is 1.77 µm, and the standard deviation is 0.75 µm after the plating. The mean value is 1.53 µm, and the standard deviation is 0.64 µm after the surface planer process. In terms of WiD coplanarity, similar results are obtained both after the plating and after the surface planer process. The WiD coplanarity after the plating is acceptable for the packaging process. In addition, the surface planer process does not adversely affect the WiD uniformity.

Fig. 3
figure 3

Box plot of the within-die coplanarity after the plating process and after the surface planer process

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The shape of the pillar might have a negative impact when the dies are stacked. The top surface should be as flat as possible to avoid slippage of the top bump unless the top surface is domed. However, voids may form if the top surface is dish-shaped. Figure 4 shows scanning electron microscopy (SEM) images of the Cu pillars after the photoresist and Cu seed/TiW barrier were removed. No defects or missing bumps are observed on the pillar after the plating (Fig. 4a, b) or after the surface planer process (Fig. 4d, e, respectively). In addition, no deformation of the Cu pillar is observed after the surface planer process. To quantify the shape of the pillar, we observed their top shapes by interferometric microscopy. Figure 4c, f show interferometric images after the plating and after the surface planer process, respectively. The height at the center of the pillar was extracted to calculate the total indicated runout (TIR) (see Fig. 4g, h). The TIR was calculated as:

Fig. 4
figure 4

Inspection results of the Cu pillar before and after the surface planer. (a) Tilt-view SEM image at low magnification of the Cu pillars after the plating. (b) Tilt-view SEM image at high magnification of a Cu pillar after the plating. (c) Interferometric image after the plating. (d) Tilt-view SEM image at low magnification of Cu pillars after the surface planer process. (e) Tilt-view SEM image at high magnification of a Cu pillar after the surface planer process. (f) Interferometric image after the surface planer process. (g) and (h) The extracted line profiles for a Cu pillar

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$$TIR\;\left[\%\right]=\frac{H\text{c}-H\text{e}}{H\text{max}}\times100$$
(2)

where Hc is the pillar height at the center, He is the average height 5 µm from the pillar edge, and Hmax is the highest point on the pillar. The Hmax after the plating was 0.93 µm. The TIR after plating was − 1.72%, where the negative value indicates that the top of the pillar after plating was dished at the center. The Hmax was 0.21 µm. The TIR was − 0.169% after the surface planer process. This result indicates that the surface planer creates a nanometer-scale flat pillar surface, which reduces the risk of yield loss at the stacking.

3.2 Backgrind tape planarization

The wafer surface topography becomes high because of the presence of microbumps and/or Cu pillars, which poses a challenge for the current wafer support system, e.g., UV-releasable BG tape, which cannot maintain a good TTV because of its followability on the surface. To mitigate the variation caused by the followability of the tape on the pillar wafer, the tape side was subjected to the surface planer process. Figure 5a shows a wafer map of the total thickness after tape lamination of the Cu pillar wafer. Surface-planarized Cu pillars 43 µm in height are observed on the wafer. The sum of the Si wafer and the tape thickness was 1035 µm. However, the measured mean thickness after lamination was 1057 µm because of the pillars on the wafer. The greatest pillar height was 1074 µm at the die center, and the lowest pillar height was 1039 µm at the dicing street. To reduce the TTV, the surface planer process was applied to the tape. The removal amount of the tape was approximately 17 µm. Figure 5b shows a wafer map of the total thickness after the tape was subjected to the surface planer process. The TTV was substantially reduced compared with the post-lamination TTV. Figure 5c shows the total thickness with respect to the radius position before and after the surface planer process. The 90% TTV (5% top and bottom excluded) was 31.77 µm after lamination and was reduced to 14.55 µm after the surface planer process.

Fig. 5
figure 5

Total wafer thickness in a 300-mm wafer with a Cu pillar after lamination of BG tape and application of the surface planer process to the BG tape. (a) Wafer map after lamination. (b) Wafer map after the surface planer process. (c) Radius distribution with and without the surface planer process

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A huge peak and valley were formed between the die center and the dicing street after lamination of the tape (Fig. 5). The cross-point of the dicing street in both cases was observed by optical interferometry. Figure 6 shows a tilt view of interferometry at the cross-point of the dicing street at the center. The cross-point of the dicing street exhibits the lowest height because there is no pillar and this point is farthest from the edge of the pillar pattern. After lamination, the Rz was 34.4 µm, which is similar to that observed in the wafer-level measurement. After the surface planer process, the surface planer cut lines are clearly observed. The roughness of the surface planer cuts was very small and was negligible compared with the peak and valley of the tape itself. The Rz after the surface planer process was 10.1 µm, which is also consistent with the result of the wafer-level TTV.

Fig. 6
figure 6

Interferometric image of the BG tape surface laminated on the Cu pillar wafer. These images were taken at the cross-point of the dicing street (a) after lamination and (b) after the surface planer process

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The backside Si thinning process was applied to the Cu pillar Si wafer with the BG tape. The target thickness of the Si after grinding was 100 µm. These wafers were processed using the same grinding condition, and the same chuck was used for the comparison. Before tape lamination, a 200-µm-deep and 500-µm-wide edge trimming process was applied [34, 35]. Figure 7 shows the Si thickness after grinding. The Si thickness was measured using an infrared laser tool. For the case without a surface planer, the mean thickness of the Si was 100.1 µm after grinding. However, the TTV within 90% of the surface was 8.2 µm. For the case where the surface planer process was applied to the tape, the mean thickness of the Si after grinding was 100.4 µm, and the TTV was 1.52 µm. These results indicate that the surface planer process mitigates the noncoplanarity of the tape after lamination. For the case without the surface planer process, a scattering of approximately 5 µm in the same radius position in the wafer was observed. By contrast, the wafer-level variation was ~ 1 µm for the case with the surface planer process.

Fig. 7
figure 7

Si thickness of the Cu pillar wafer after grinding toward 100 µm with and without the surface planer process

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Figure 8 shows the die-level Si thickness at the middle of the wafer. In the case with (Fig. 8a) or without the surface planer process (Fig. 8b), the Si thickness at the die center is slightly greater than that at the dicing street because of the presence of the pillar. This greater Si thickness at the die center is attributed to the pillar preventing deformation of Si by vertical pressure during grinding. Figure 8c shows the cumulative frequency graph of the Si thickness in Fig. 8a, b. In the case without the surface planer process applied to the tape, the distribution of the Si thickness was wider than 4 µm. However, the distribution of the Si thickness was only 1 µm in the case where the surface planer process was applied to the tape. In either case, the Si TTV after grinding was much smaller than the TTV of incoming total thickness (tape + wafer). This smaller TTV is attributed to the vacuum chuck table of the tool compensating for some of the topography of the tape. However, if the topography is too high, as in the case where the surface planer process was not applied (> 30 µm TTV), compensation is not possible, as evident in the TTV of the Si after the grinding process. For the advanced packaging, the Si thickness variation in a die becomes critical for stacking and molding. The surface planer process applied to the tape can mitigate the TTV of the Si after grinding.

Fig. 8
figure 8

Local Si thickness of a Cu pillar wafer after grinding toward 100 µm (measurement location X: 70 to 80 mm, Y: − 5 to 5 mm): (a) without the surface planer process and (b) with the surface planer process applied to BG tape. (c) Cumulative frequency extracted from (a) and (b)

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4 Conclusions

We demonstrated planarization of Cu pillars and UV-curable BG tape to control the Cu pillar height and Si thickness of wafers. The planarized Cu pillars exhibited a WiW uniformity of 3.5% on a 300-mm wafer, which requires substantial effort for optimization when only electrodeposition is used. In addition, the planarized Cu pillars exhibited a substantially flatter shape than that after plating. Furthermore, the surface planer process compensated for the topography caused by flowability of the BG tape on the Cu pillar wafer. The TTV after Si thinning toward 100 µm was 1.52 µm. Because high coplanarity of the Cu pillars and Si thickness is required for advanced packaging, achieving wafer-level coplanarity via the surface planer process is advantageous. Thus, the surface planer process can be viewed as a potential alternative planarization process for advanced packaging.

However, the removal mechanism of the surface planer is “cutting”, which has certain limitations to obtain atomic-scale flatness or nano-topography with a high throughput process. With further scaling of advanced packaging processes, planarization and its uniformity will continue to remain important. Future improvements in planarization of polymers/metals with high coplanarity will be achieved through a combination of surface planer processes (for bulk removal) and polishing (for surface finish).