1 Introduction

The Internet-of-Things (IOT) or even the Internet-of-Everything (IOE) has greatly promoted the development of low-power integrated circuits in the past decade [4, 8, 11]. As a bridge between analog and digital circuits, the ADC is an indispensable module in the IOE systems. The performance of the ADC will directly determine the performance of the entire IOE. Therefore, designing an ADC with low power becomes especially important.

Compared with several ADCs, SAR ADC has been paid more and more attention to by scholars because of its high efficiency [15]. For capacitive SAR ADC, the capacitor arrays of the digital-to-analog converter (DAC) may result in significant switching energy drawn from the reference voltages during conversion. To avoid the limitation, various approaches have been proposed. Recently, several schemes have been presented to reduce the switching energy and also the chip area, such as the capacitor-splitting scheme [9, 12], VCM-based scheme [10], tri-level scheme [13], and VCM-based monotonic scheme [14]. In this paper, a new switching method based on the asymmetric binary algorithm is presented, which splits the LSB capacitor into two one-half unit capacitors. Compared with the switching schemes proposed above, the proposed switching method achieves the most energy efficient by using three reference voltages: VREF, VCM, and GND.

The following sections are organized as follows. Section 2 introduces the comparison between the conventional binary search algorithm and the asymmetric binary search algorithm. Section 3 presents the proposed switching scheme. Section 4 gives the simulation results of the switching energy. Section 5 shows the simulation results of linearity and mismatch. Section 6 is a brief conclusion about this paper.

2 Comparison of Binary Search Algorithms

Figure 1a shows a 4-bit switching example of the conventional binary search algorithm. In the conventional binary switching method, the MSB capacitor is connected to VREF, and the positive input signal is compared with 1/2 VREF. If the input signal is less than 1/2 VREF, the most significant bit (MSB) capacitor is connected to GND, and the MSB-1 capacitor is connected to VREF [3]. The subsequent operations are similar. However, charging all capacitors by order is the main reason for binary search inefficiency.

Fig. 1
figure 1

Searching process of binary and asymmetric binary search algorithms. a Binary search (4-bit), b Asymmetric binary search (4-bit)

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Compared with the conventional binary search, the positive input signal is firstly compared with 1/4 VREF in the asymmetric binary search method. If the input signal is more than 1/4 VREF, the MSB capacitor is switched to achieve the comparison between the input signal and 3/4 VREF. Otherwise, the MSB-2 capacitor is switched to achieve the comparison between the input signal and 1/8 VREF [1]. A 4-bit switching example is shown in Fig. 1b. Although the comparison cycles for digitizing the input signal between ± 1/4 and ± 3/4 VREF are slightly increased, the total comparison cycles will not change. Quantizing the input signal that is less than 1/4 VREF requires only three comparison cycles. Besides, the discharging operation that switching from ± 3/4 to ± 1/2 VREF consumes less energy compared with traditional charging operation. Thus, the switching power that quantizing the input signal between 0 and ± 3/4 VREF is greatly reduced, and digitizing the remaining range of the input signal consumes as much energy as the conventional binary switching.

3 The Proposed Switching Scheme

The proposed switching scheme for a 5-bit SAR ADC is shown in Fig. 2. The switching energy of each step is indicated in the figure, and the switching processes A′, B′, C′, and D′ are opposite to A, B, C, and D. It is stipulated that “yes” means to switch up, and “no” means to switch down. In this design, the LSB capacitor is split into two one-half unit capacitors to avoid the process mismatch problem of small capacitors. And the one-half unit capacitor is achieved by connecting two unit capacitors in series.

Fig. 2
figure 2figure 2

Proposed switching scheme for a 5-bit SAR ADC

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In the sampling phase, the MSB capacitor is connected to GND, and the remaining capacitors are connected to VREF. The input signal is sampled to the top plates of the differential capacitor arrays DACP and DACN through the sampling switches. To avoid the intermediate node floating all the time and the continuous accumulation of static electricity at the intermediate node, the intermediate node’s voltage is preset to GND through a switch in each sampling phase. In the quantification phase, the switch will be turned off and the comparator performs the first comparison. When the digital code is determined, the MSB capacitor on the higher-voltage side remains unchanged, and the remaining capacitors are connected to VCM, where VCM = 1/2 VREF. And the input signal will be compared with ± 1/4 VREF. Subsequently, the MSB capacitor is charged or the MSB − 1 capacitor is discharged to achieve the comparison between the input signal and ± 3/4 VREF or ± 1/8 VREF. The later comparison process is like A or D. If compared with ± 3/4 VREF, the input signal also needs to be compared with ± 1/2 VREF or ± 7/8 VREF. If the input signal is compared with ± 1/2 VREF, it is necessary to spend an extra comparison period compared with ± 5/8 VREF or ± 3/8 VREF to determine the LSB + 1 like B or C. The subsequent switching processes in A, B, C, and D follow the monotonic switching. The LSB capacitor is divided into two groups, and one of them on the higher-voltage side is switched from VCM to GND or from VREF to VCM according to the comparison results.

In the proposed switching method, the sampling phase, the first two switching operations and the downward switching operation in D don’t consume energy. Besides, the energy consumed by the remaining switching steps is not significantly increased compared with other switching methods [1, 9, 10, 12,13,14]. So, the proposed switching method achieves energy efficiency greatly.

Figure 3 shows the successive approximation waveform of the present scheme for a 5-bit SAR ADC and VREF is equal to 1 V. Figure 3a–d, respectively, shows the successive approximation waveforms of the input signal in the range from 0 to 1/4 VREF, 1/4 to 1/2 VREF, 1/2 to 3/4 VREF, and 3/4 to VREF. As shown in Fig. 3a, it takes only four comparison cycles to get the 5-bit digital output, when the input signal is between 0 and 1/4 VREF. And the digital codes are 1, 0, 1 and 1. Since the input signal is less than 1/4 VREF, it is also less than 1/2 VREF. Therefore, there is no need to switch the MSB capacitor to get the higher bit digital code “0.” The input signal is compared with 1/8 VREF and 3/16 VREF in the following comparison cycles. Finally, the binary digital output is 10011. When the input signal is between 1/4 and ¾ VREF, it is necessary to spend an additional comparison period getting the 5-bit digital output.

Fig. 3
figure 3

Successive approximation waveform in four cases of 5-bit output. a 0 < VDACP − VDACN < 1/4 VREF, b 1/4 VREF < VDACP − VDACN < 1/2 VREF, c 1/2 VREF < VDACP − VDACN < 3/4 VREF, d 3/4 VREF < VDACP − VDACN < VREF

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4 Switching Energy Analysis

Figure 4a shows the behavior level simulations of the proposed switching method and the existing switching methods presented in references [1, 10, 13, 14] in MATLAB. Compared with the existing switching methods, the proposed switching method consumes the lowest energy. Figure 4b shows the enlarged average switching energy of the proposed switching scheme. It can be seen that there is a jump at 1/8, 3/8, 5/8, and 7/8 of the digital output code. These points divide the waveform into six segments that are 0–128, 129–384, 385–512, 513–640, 641–896, and 897–1024. And the six segments correspond to the six ranges of input signals that are − VREF to − 3/4 VREF, − 3/4 VREF to − 1/4 VREF, − 1/4 VREF to 0, 0 to 1/4 VREF, 1/4 VREF to ¾ VREF, and 3/4VREF to VREF. The average switching energy of the proposed switching method is only 7.8 \( {\text{CV}}_{\text{REF}}^{ 2} \). Compared with the conventional switching method [3], the proposed switching method achieves 99.43% energy reduction and 87.2% area optimization.

Fig. 4
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Switching energy against output code. a Comparison between several switching methods, b proposed switching method

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In Table 1, the average switching energy and the total DAC capacitor for different switching schemes are compared. The proposed switching method consumes only 7.8 \( {\text{CV}}_{\text{REF}}^{ 2} \) average switching energy which results in a reduction of 99.43% over the conventional scheme. Moreover, the proposed scheme employs 262 unit capacitors and thus achieves 87.2% reduction in the total DAC capacitor compared with the conventional one. The asymmetric binary search algorithm is firstly used in [1], but its capacitors switching procedure is the VCM-based switching method, which consumes a lot of switching energy. Besides, the number of unit capacitors in [1] is not further reduced compared to other switching methods. Compared with the methods in [2, 5], the proposed scheme is able to achieve similar energy saving while taking less area, which will improve the switching timing requirements. In this work, the use of asymmetric binary search algorithms and the splitting LSB capacitor will increase the complexity of SAR logic. However, the measured power of the proposed scheme is extremely low when it is manufactured with the leading edge process technology.

Table 1 Comparison of different switching schemes for 10-bit DAC
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5 Linearity and Mismatch

The linearity of the switching scheme is directly related to the overall linearity of the SAR ADC. And the nonlinear distortion of the switching scheme is mainly caused by the mismatch of capacitors. A 10-bit SAR ADC using the proposed switching method is modeled in MATLAB. Figure 5 shows the 500 runs behavioral simulation results of INL and DNL with a mismatch of 1%. It indicates that the σINL_MAX and σDNL,MAX of the proposed switching scheme are only 0.43 LSB and 0.37 LSB. The INL and DNL of [5], whose average switching energy is close to this work, are up to 0.451 LSB and 0.559 LSB. Thus, the proposed switching scheme has a good performance in linearity.

Fig. 5
figure 5

Simulation results of INL and DNL. a INL, b DNL

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The accuracy of the reference voltage is critical for a multi-reference SAR ADC. And the intermediate reference voltage is usually obtained by dividing VREF. However, in the actual process, due to the mismatch of the devices, the value of the reference voltage is not ideal. In order to evaluate how the accuracy of VCM impacts the performance of the proposed switching scheme, the fast Fourier transform (FFT) simulation for a differential 10-bit SAR ADC is performed in MATLAB. In the scenario where the mismatch between VCM and VREF ranges from 0.1 to 0.5%, 500 runs are monitored and the simulation results are shown in Fig. 6. Effective number of bits (ENOB), signal-to-noise ratio (SNR), and signal-to-noise-and-distortion ratio (SNDR) are reduced by 0.26 bit, 1.61 dB, and 1.57 dB, respectively, when the mismatch between VCM and VREF is 0.3%. When the mismatch is 0.5%, the ENOB, SNR, and SNDR are reduced by 0.48 bit, 2.89 dB, and 2.71 dB, respectively.

Fig. 6
figure 6

Effect of mismatch on ENOB, SNR, and SNDR. a ENOB, b SNR and SNDR

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Figure 7 shows the histogram of ENOB and SNDR when the mismatch is 0.3%. It shows that the simulation results of 500 runs that the average of ENOB is 9.74 bit and the average of SNDR is 60.39 dB. Generally, the actual mismatch is less than 0.3%, so the effect of mismatch between VCM and VREF is acceptable for the design of 10-bit SAR ADCs.

Fig. 7
figure 7

Histogram of ENOB and SNDR with a mismatch of 0.3%. a ENOB, b SNDR

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6 Conclusion

A low-energy switching scheme based on the asymmetric binary search algorithm is proposed. The one-half unit capacitor is used in the structure to achieve a further reduction in power consumption. Considering the mismatch problem of small capacitors, the proposed switching structure uses two unit capacitors in series to achieve a one-half unit capacitor. Compared with the conventional switching scheme, the proposed switching scheme achieves 99.43% energy reduction and 87.2% area optimization. Using three reference voltages, VREF, VCM, and GND, the proposed scheme has significant advantages in considering power and area and has application prospect in the design of low-power SAR ADCs.