1 Introduction

The widespread of industrialisation and population increases caused to increase the energy consumption. The use of conventional energy sources increased carbon dioxide emission by simulating global warming and caused to creates unfavorable issues. Researchers are continuously struggling to develop alternate energy sources to replace conventional energy sources. Nonconventional energy sources are a good substitute for conventional energy sources. Unlikely, Nonconventional energy sources lead to high initial cost and low efficiency. Solar photovoltaic (PV) modules, small wind turbines (WT), fuel cells, etc., are widely used to harvest electrical power from non-conventional sources. However, most of the nonconventional energy systems produced unregulated low DC Voltages (12 V–48 V) and it is supposed to step up to regulated higher DC voltage levels to feed cascaded connected voltage source inverter (VSI). The converters used in the systems need some unique characteristics, such as low cost, small size, wide conversion voltage range, and Great efficiency. The DC–DC power converter can be categorised into non-isolated, partially isolated, and isolated [1].

If a wide conversion range and galvanic isolation are necessary, isolated converters (IC)is the obvious choice. A wide conversion range is achieved not only in the duty cycle, but it can also achieve between the high-frequency transformer (HFT) winding ratio. Isolated converters are faced with massive leakage inductance problems. High switching frequency has reduced the size of the HFT. However, it creates high voltage stress across switches. Isolated converters with HFT are perceived as high volume and weight, high cost, and low efficiency [2, 3].VariousPartially isolated converters (PIC) structure has been proposed [4, 5]. Partially isolated converters are preferred substantial of isolated bidirectional half and full-bridge PWM Converters. PIC is consequential of isolated bidirectional half and full-bridge PWM Converters and its area viable choice for extent input, and output ports, The prominent feature of partially isolated converters are low components count leads to avoid complex circuit. Conversely, partially isolated converters had constricted voltage regulation, making high voltage stress consequences restricted to low power application. Moreover, the failure of a single element creates enormous issues.

Non-isolated converters (NIC) are used in a wide conversion range and where galvanic isolation is not necessary. The reactive components and semiconductors have dispersed the load. A wide conversion range is attained with a high duty cycle that produces high current and voltage stress, consequently reducing dynamic response. Non isolated converters are produced high current ripples in the series inductor. Undesirably its create reverse recovery issues that lead to conduction loss and poor efficiency [4, 5]. The converters are referred to in [6] is proposed a converter with a coupled inductor for high voltage conversion. Coupled inductors are made with a ferrite core with a 1:1 transformation radio. Coupled inductor-based converters are produced high EMI issues and it’s are not suitable for high-frequency operation. Voltage doubler circuits [7] are used for a high conversion ratio, Two are more reactive components are used. Voltage doubler circuits are suitable for high-frequency operation. Interleaved converters [8, 9] are preferred for high power applications, more number of inductors, switches, coupled inductors, and Transformers are involved. Switches are operated in a different period leads to difficult control and reduced static gain. Cascaded boost converters are referred to in [10,11,12], two simple boost converters are connected in cascade for a wide conversion range. Superior voltage gain achieved. Conversely, more components and more stages influenced noises to create poor efficiency. Snubbed circuits and complex control schemes are indispensable to remove noises and increase the efficiency of the cascaded converter. The single-ended primary-inductor converter (SEPIC) [13,14,15], Cuk converter [16, 17], and interleaved flyback converter [18, 19] are choices for a wide conversion range. Aforesaid topologies, necessary to operate low or high-duty radio, lead to high cost and complex driver circuits. Wide range conversion influenced high voltage stress and filter inductor parasitic resistances create significant losses instigated to performance degrade and poor efficiency.

Commercial PV systems need DC–AC conversion to operate AC Loads. Multilevel inverters are an obvious choice for smooth operation [20,21,22,23]. MLI is considered to meet fixed AC output voltage and frequency, Low THD, Restricted voltage fluctuation. Conventionally, many topologies are emerged to achieve multilevel outputs. It prerequisites multiple sources to generate multilevel outputs. The maximum output voltage of a conventional multilevel inverter is a sum of input DC source voltages. Split capacitors and T-type multilevel inverter [24,25,26] are used laterally to increase the level of output from a single DC source. However, the maximum output voltage of the T-type multilevel inverter is equal to the input DC source voltage. Switched capacitors multilevel inverters [27,28,29,30] are better for a renewable energy system due to their robustness. Switched capacitors MLI multilevel output is generated from a single DC source and creditable voltage gain.

In view of the extensive analysis, indispensable to develop a converter with a good voltage conversion, less voltage stress across switches. Incorporation of voltage multiplier circuit with existing boost converter circuit is superior choice to achieve high voltage conversion ratio and less switching voltage stress. In general DC–DC converters are used to improve the input voltage and subsequently DC–AC converters are used to convert high voltage DC to AC. Boost operation is performed in DC–DC conversion. Among these power electronic devices DC–DC converters are highly effective for DC voltage regulation and to improve the efficiency of renewable energy systems. Appropriate selection of the DC–DC converter is an important factor that has a significant contribution to the overall performance of the power systems. Besides, the selection of an efficient DC–DC converter topology, for its optimum operation integration of a suitable control technique is equally important. The proposed SSHGC is incorporated with Luo super lift voltage multiplier circuit for wide voltage conversion and MLI is developed with switched-capacitor technique. Two capacitors are used to generate seven-levels output with a triple boost. The structure of the proposed DC–DC–AC converter is shown in Fig. 1. Voltage gain is achieved in both SSHGC and MLI.

Fig. 1
figure 1

Proposed DC–DC–AC converter

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The paper describes the structure and operating modes of the SSHGC in Sect. 2. Proposed multilevel DC–AC circuit configuration and operating modes are described in Sect. 3. Analysis of the DC–DC–AC converter with parameter design is discussed in Sect. 4. The simulation and experimental results of the cascaded SSHGC and MLI are presented in Sect. 5. Conclusion with features of the cascadedSSHGC and MLI is described in Sect. 6.

2 Analysis of Single Switch High Gain Converter

The structure of the SSHGC is shown in Fig. 2. PV module is connected to low voltage DC input port and MLI is connected in high voltage output port. The output power of the PV module depends on the intensity of the light fall on the PV module and the output voltage of the PV module is varying manner. The Inductor L1 and capacitor C1 act as an LUO super lift circuit. To achieve a wide conversion range, Inductor L2 is integrated with LUO super lift circuit. The Diode D1, D2, and D3 are connected with an Inductor L1, L2, and C1. The filter capacitor (CF) is connected across the output DC port, which helps to operate the MLI with a constant voltage. The operating modes of SSHRC are shown in Fig. 3a and b. D4 is connected between the high gain circuit and output port in order to reduce reverse current flow.

Fig. 2
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Structure of SSHGC

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Fig. 3
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Mode of operation of SSHGC converter a Mode-I (S is ON) and b Mode-II (S is OFF)

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The equivalent circuit of Mode-I operation of SSHGC is shown in Fig. 3a. The Switch ‘S’ starts conduction at the time of \(t_{1}\), The PV voltage makes the Diodes D1, D2, and D3 as forward biased. PV current starts to flow through the L1, L2, C1. L1, L2, C1 are connected in parallel with PV Module through Diodes D1, D2, and D3. L1, L2, and C1 are being charged by harvested solar power. The current flowing through the PV (IPV) is equal to the sum of the current in inductors L1, L2, and capacitors C1. Diode D4 is reverse bias, consequently, the load is disconnected from the high gain circuit. During the Mode-I capacitor, CF is responsible for providing load power. Switch S is turned on up to Inductors L1, L2, and Capacitor C1 are sufficiently charged. Mode-I ends at the time of \(t_{2}\) and Mode-II begins. Mode-II operation of the proposed converter is shown in Fig. 3a, During the mode Switch ‘S’ is turned off, the polarity of L1 and L2 reversed due to their degradation current, subsequently, D1, D2, and D3 are reverse biased. Diode D4 is forward biased and C1, L1, and L2 are connected in series with PV and output port.TheL1, L2, and C1 are being discharged. The voltage across the output port(V0(DC)) is equal to the sum of VPV, VL1, VL2, and VC1. Capacitor CF is being charged. The Mode-II ends at the time of t3. The SSHGC voltage gain and design considerations are analysed in chapter-4.

3 Boost Seven-Level Inverter with Triple Voltage Gain

The proposed MLI circuit is shown in Fig. 4. The MLI is designed with a voltage booster and an inverting circuit. The MLI is connected in series with SSHGC. The capacitors CI1 and CI2 are employed to perform boost operations. The capacitors CI1 and CI2 are frequently charged from SSHGC output power and discharged through the load to achieve triple voltage gain. The SSHGC output voltage (VDC(BUS))is raised to 2VO(DC) and 3VO (DC)with the help of Capacitors CI1 and CI2. Five IGBT switches (S1 to S5) are used to construct the MLI and the switches are connect the capacitors CI1 and CI2 with SSHGC output and load. Voltage booster circuits operate in 4 modes, and each mode boosts an SSHGC output voltage with a different voltage level. The circuit model of each mode is shown in Fig. 5a to d. The output of Voltage booster circuits is connected with inverting circuit. Diode DI1 and DI2 protect the capacitors from self-discharging, and it is forward bias during Mode-I and reverse bias in the rest of the mode. The inverting circuit is connected between the DC bus and AC load. The inverting circuit is made with four IGBT switches (S6 to S9). Four anti-parallel diodes connected with IGBT are to allow freewheeling current during operates in inductive loads. The switch S6, S7 are positive groups S8, S9, are a negative group, and it is operated by load frequency.

Fig. 4
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Circuit configuration of DC–AC multilevel inverter

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Fig. 5
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Equivalent circuit of multilevel inverter a Mode-I b Mode-II c Mode-III and d Mode-IV

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Mode-I The equivalent circuit model of Mode-I is shown in Fig. 5a. Switches S2, S4, and S5 are getting pulses and the rest of the switches are in voltage boosting and the inverting circuit is turned off. DI1 and DI2 are forward biased and allow the current to flow from SSHGC to Capacitors CI1 and CI2. The capacitors CI1 and CI2 are connected across the SSHGC output and are charged independently. The capacitor CI1current is flowing through S2, DI1, S5, and capacitor CI2 current are flowing through S4, DI2, and S5. Capacitor charge current is desired by the State of Charge (SOC) of the capacitors, and it is controlled by Pulse Width Modulation (PWM) technique. Switch S2, S4 are subjected to PWM pulses. The maximum charging voltage of the capacitor is SSHGC output voltage (VDC(BUS)). During Mode-I, SSHGC output power is only used to charge the capacitors. The voltage across the DC bus is VDC, and the load voltage (VOAC) is zero. Figure 6 shows the switching pulses of each switch in one complete cycle and Fig. 7 shows the charging and discharging profile of each capacitor in one complete cycle.

Fig. 6
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Switching sequence of the proposed MLI

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Fig. 7
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Charging and discharging waveform of capacitors

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Mode-II During this mode, the voltage across the DC bus is maintained as MLI input voltage (VO (DC)). The equivalent circuit model of Mode-I is shown in Fig. 5b. During the mode, Switch S4 and inverting circuit, positive or negative group switches are operate based on the output voltage. Inverters are subjected to SPWM control to enhance the performance of the inverter. Generally, single-phase two-level inverters are having two legs and switching pulses apply to positive or negative groups, each leg built with two serially connected switches. DC Bus voltage is applied across each leg and load is connected in between the legs. DC bus voltage of the conventional inverters are constant and switches are directly controlled by SPWM. The proposed MLI DC Bus voltage is varying from 0 to 3VO(DC), in consequence, SPWM control is limited to apply in inverting circuits. Upon that SPWM is applied to the voltage booster circuit in the proposed MLI. Switch S4 is subjected to SPWM.

Mode-III During this mode, the voltage across the DC bus is maintained as 2VO(DC). The Sum of Input DC voltage and capacitor CI2 (VCI2) has appeared across the DC bus. The equivalent circuit of Mode-III is shown in Fig. 5c, Switches S2, S3 and corresponding inverting circuit switches (either positive or negative group) are operating. Capacitor CI2 is connected between the input of the inverter and DC Bus. VCI2 is being discharged and the voltage across the capacitor CI2 is equal to VO(DC)). During the period, the voltage across the DC bus seemed as 2VO (DC), SSHGC, and CapacitorCI2 are responsible to provide the load power. SPWM pulses were applied to switch S2 and S4 to withstand the voltage across the DC bus in the range between VO(DC) and 2VO(DC).

Mode-IV During this mode, the voltage across the DC bus is maintained as 3VO(DC). Sum of Input DC voltage, capacitor CI1 (VCI1), and capacitor CI2 (VCI2) appear across the DC bus. The equivalent circuit of Mode-IV is shown in Fig. 5d, Switches S1, S4, and corresponding Inverting circuit switches are operated.CI1 and CI2 are connected in series between the input of the inverter and DC bus. Capacitors CI1, CI2, and SSHGC are responsible to provide load power. The sum of VCI1, VCI2, and VO(DC)) is appeared across DC bus voltage and it is maintained as 3VO(DC). The capacitors CI1 and CI2 and are being discharged. SPWM pulses are applied to switches S1and S2 in order to control AC load voltage. DC bus voltage is maintained in between 2VO(DC) and 3VO(DC).

The capacitors are charged during Mode-I and both the capacitors are independently charged from SSHGC output power. The charging and discharging waveform of the Capacitors in MLI is depicted in Fig. 7.The charged capacitors are discharged in Mode-III and Mode-IV. The charging current of the capacitors C11 and C12 are caused to produce current ripples. The filter capacitor connected in SSHGC is supported to reduce the MLI input voltage and current ripple, The capacitors CI1 and CI2 are allowed to get a charge from the source during output voltage (VO(AC)) is equal to zero.

The capacitors CI1 and CI2 are provide the load power with SSHGC at one complete cycle is T/7 and 2T/7respectively. SSHGC alone operate the load during the output AC voltage VO(AC) is equal to VO(DC) and − VO(DC), Along with the SSHGC output, the capacitor C12 operates the load at the time of VO(AC)is equal to 2VO(DC), and − 2VO(DC). Along with the SSHGC output, the capacitors CI1 and C12operates the load at the time of VO(AC) are equal to 3VO(DC)and − 3VO(DC). The stored energy required to operate the AC load in capacitor CI1 is less than CI2. Two different capacitor values are selected for CI1 and CI2. The design consideration of capacitors CI1 and CI2 is discussed in Sect. 4. The value of CI2 is higher than CI1. Voltage sag across the capacitor CI1 and CI2 during the discharge period has degraded the performance of the AC output, a well-designed control algorithm is used to overcome the issues.

4 Analysis of Proposed SSHGC and MLI Systems

The proposed system consists of SSHGC and MLI stages. The voltage gain of the SSHGC is obtained based on the assuming average inductor voltage at steady state is zero and the SSHGC is operated in continuous conduction mode (CCM). During the Mode-I operations, change in the current of inductor L1 is formulated as

$$\frac{di}{{dt}} = \frac{{V_{PV} }}{{L_{1} }}.kT$$
(1)

where the SSHGC converter input voltage is VPV, k is the duty cycle of the Switch S, and T is the time period. During Mode-II operation, change in inductor current is formulated as

$$\frac{di}{{dt}} = \frac{{(V_{0(DC)} - V_{PV} )}}{{L_{1} }}(1 - k)T$$
(2)

where V0 is the output voltage of SSHGC.

Equating Eqs. (1) and (2)

$$V_{PV} .k = (V_{0(DC)} - V_{PV} )(1 - k)$$
(3)

Rearranging the Eq. (3) to find steady mode voltage gain \((V_{0} /V_{in} )\)

$$\frac{{V_{0(DC)} }}{{V_{PV} }} = \frac{3 - 2k}{{1 - k}}$$
(4)

The Voltage gain of SSHGC is compared with other converters to evaluate the performance of the proposed converter. The voltage gain comparison of various duty ratios is made with classical boost, SEPIC, and Super lift Luo converter. The results are depicted in Fig. 8. The results show the voltage gain of SSHGC is higher than other converters at any duty cycle.

Fig. 8
figure 8

Voltage gain comparison of proposed SSHGC with Boost, SEPIC, and Luo Converters

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The boost inductor L1 and L2 are

$$L_{1} = L_{2} = \frac{{(V_{PV} \times D_{S} )}}{{f_{S} \times \Delta I_{L} }}$$
(5)

where VPV is input PV voltage, DS is duty ratio, fs is switching frequency, and \(\Delta I_{L}\) is a change in inductor current. While calculating L1 and L2 minimum values of DS is selected to confirm the CCM operations.

The capacitor C1 stores the energy from the PV module during S is ON stare and connected series with the load during S is OFF to release stored energy. During Mode-II, the output current is flowing through capacitor C1.

The value of the capacitor

$$C_{1} = \frac{{I_{O(DC)} \times (1 - D_{S} )}}{{f_{S} \Delta V_{C1} }}$$
(6)

where IO(DC) is the output current, \(\Delta V_{C1}\) is a change in capacitor voltage. A high Ds value is selected for calculating C1 to reduce voltage ripples.

The voltages variation during operation across MLI capacitors are degrade the performance of the inverter. The capacitor CI1 is discharged during t1 to t5 and t9 to t12. The capacitor CI2 is discharged during t3 to t4 and t9 to t10. During this period, changes in electric charges in capacitors depend on the load current and power factor.

Load active power

$$P_{L} = V_{0(AC)} .I_{O(AC)} \cos \theta \,{\text{Watts}}$$
(7)

where \(\theta\) is the phase angle between load voltage and current. Cos \(\theta\) is the power factor of the load.

Active power required for one time period to operate AC load is \(P_{L(T)} = P_{L} \times T\) Watts and one cycle (Capacitor charge and discharge) is

$$P_{L(C)} = \frac{{P_{L} \times T}}{2}\,{\text{Watts}}$$
(8)

where T is a time period of load fundamental frequency f.

Maximum energy stored in a capacitor is

$$W_{C} = \frac{{C \times (V^{2}_{C} )}}{2}\,{\text{Joules}}$$
(9)

where Vc is Voltage across the capacitor, the amount of Energy transfer is estimated as

$$W_{C} = \frac{{C \times (V^{2}_{C(S)} - V^{2}_{C(f)} )}}{2}\,{\text{Joules}}$$
(10)

where \(V^{2}_{C(S)}\) is an initial voltage across the capacitor and \(V^{2}_{C(f)}\) is a final voltage across the capacitor.

The relationship between power and energy is

$$P_{C} = \frac{Wc}{{dt}}\,{\text{Watts}}{.}$$
(11)

\(dt\) is discharging time.

At constant load, the power delivered by the capacitor is

$$P_{C} = \frac{{C \times (V^{2}_{C(S)} - V^{2}_{C(f)} )}}{2.dt}\;{\text{Watts}}{.}$$
(12)

Change in voltage across capacitors

$$\Delta Vc^{2} = (V^{2}_{C(S)} - V^{2}_{C(f)} )\,{\text{Volts}}{.}$$
(13)

From Eq. (12) The value of capacitor

$$C = \frac{{2.P_{C} .dt}}{{(V^{2}_{C(S)} - V^{2}_{C(f)} )}}\,{\text{Farad}}{.}$$
(14)

The load power requirement is fulfilled by input DC supply, Capacitor IC1, and Capacitor IC2. One cycle is split into eight sectors, out of eight sectors, two sectors are used to charge the capacitors CI1 and CI2, and six sectors are delivering power to load. The remaining two sectors DC supply alone provides load power. DCsupply and Capacitor IC2 are shared load power during two sectors. DC supply, Capacitor CI1, and Capacitor CI2 are shared load power during two sectors. DC supply, CI1, and CI2 are fulfilled the total load power requirement in the ratio of 6:4:2 respectively.

Power delivered to load by one complete cycle by

$${\text{DC}}\,{\text{source}}\,{\text{is}}\,P_{L(DC(C))} = \frac{{P_{L} \times T}}{12}\,{\text{Watts}}$$
(15)
$${\text{Capacitor}}\,{\text{CI}}_{{1}} \,{\text{is}}\quad P_{L{(CI1 (C))}} = \frac{{P_{L} \times T}}{8}\,{\text{Watts}}$$
(16)

and

$${\text{Capacitor}}\,{\text{CI}}_{{2}} \,{\text{is}}\quad P_{L(CI2(C))} = \frac{{P_{L} \times T}}{4}\,{\text{Watts}}$$
(17)

The value of

$$C_{I1} = \frac{{2 \times P_{L} \times T}}{{8(V^{2}_{CI1(S)} - V^{2}_{CI1(f)} )}} = \frac{{P_{L} \times T}}{{4(\Delta V_{CI1}^{2} )}}\,{\text{Farad}}$$
(18)

and

$$C_{I2} = \frac{{2 \times P_{L} \times T}}{{4(V^{2}_{CI2(S)} - V^{2}_{CI2(f)} )}} = \frac{{P_{L} \times T}}{{2(\Delta V_{CI2}^{2} )}}\,{\text{Farad}}$$
(19)

where \(\Delta V_{CI1}\) and \(\Delta V_{CI2}\) are changes in capacitors voltage during discharge. Low \(\Delta Vc\), reduced voltage sag in output AC voltage.

The performance analysis of the proposed MLI is tabulated in Table 1 to highlight their relative distinctions. Essential parameters like voltage gain, number of input DC sources, number of semiconductor switches, and Output AC voltage level is compared and tabulated. The major shortcoming of the latest MLI topologies presented in [28,29,30] is the requirement of more than one DC source. Minimum three DC sources are required to produce seven-level output. Higher voltage levels of MLI AC voltages to reduce THD and ensure smooth operations. The topologies presented in [27] are used three H-bridge circuits and more quantity of semiconductor switches. The proposed MLI is developed with only 9 semiconductor switches to achieve seven levels of voltage output with triple voltage gain by using a single source.

Table 1 Comparison of proposed MLI with other latest MLI
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5 Simulation and Experimental Result

Matlab simulation and hardware are realised to analyse the superiority of the proposed SSHGC and MLI system. Experimental analysis is carried out with a 200 W load. 24 V, 200 Watts module is used to feed DC power to the SSHGC converter. Modified P&O MPPT technique is applied to ensure maximum power utilisation of PV module. The SSHGC is developed with a High-speed IGW60N60H3 IGBT with a switching frequency of 25 kHz. The Photo image of the Hardware Prototype of the Proposed System is shown in Fig. 18. The SSHGC input PV voltage (VPV) and current (IPV). The simulation and experimental results are shown in Figs. 9, 10, 11, 12 and 13. The input DC voltage of SSHGCis maintained as 24 V and the current is 8.2 A. Isolation level of the PV module is set to 1000 W/M2, the temperature is 250 C and 200 Watts power is fed to SSHGCconverter.Small variation has arisen in input voltage and current Due to MPPT.

Fig. 9
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Simulation of SSHGC input voltage and current

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Fig. 10
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Voltage across L1, L2, and C1

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Fig. 11
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Simulation result of SSHGC output voltage (VO(DC)) and current (IO(DC))

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Fig. 12
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SSHGC converter power, efficiency, and duty ratio

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Fig. 13
figure 13

Hardware result of SSHGC converter a input voltage (VPV) and current b output voltage (VO(DC)) and current (IO(DC))

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The L1 and L2 values are selected as100 mH and the C1 is 200 μF, 63 V are used. The voltages waveform across the L1, L2, and C1, are shown in Fig. 10. The voltage across the L1and L2 are positive at Mode-I. During the period PV energy is stored in inductors L1, L2, and C1. The voltage across the L1 and L2 are negative at Mode-II. During the period stored energy in inductors L1, L2 and C1 are transferred to load. The voltage across the capacitor and inductors currents is always positive. Charging and discharging voltages are equal in both the inductors. Change in capacitor voltage \(\left( {\Delta V_{C1} } \right)\) during operation is degrade the voltage gain performance of the SSHGC.

The waveform of SSHGC output voltage (VO(DC)) and Current (IO(DC)) simulation waveforms are shown in Fig. 11 and experimental waveforms are shown in Fig. 13b. MPPT algorithms are operated in SSHGC with a duty ratio of 0.6. The gain of the SSHGC is.

$$\frac{{V_{0} }}{{V_{in} }} = \frac{3 - 2k}{{1 - k}} = \frac{3 - 2 \times (0.6)}{{1 - 0.6}} = 4.5$$

The input voltage VPV is 24 V and the voltage gain of the SSHGC is 4.5. The output voltage and current reach to 109 V and 1.7 A respectively.1000 μF, 200 V filter capacitor is used.

Proposed SSHGC power and efficiency curves in the maximum power point condition are shown in Fig. 12. 200 W solar power is fed to SSHGC, and the output port power is measured as 185 Watts. The efficiency of the SSHGC converter is achieved as 92.5%.

The output power of the SSHGC converter is fed to the proposed MLI. The capacitors CI1 and CI2 are used to increase the gain and level of MLI. Capacitors CI1 and CI2values are obtained by using Eqs. (18) and (19). Active load power and time period are deliberated to calculate CI1 and CI2. The value of CI1 and CI2 are 500 μF, 200 V and 1000 μF, 200 V for 200 W, 50 Hz load. The voltage rating of the capacitors are selected based on the SSHGC output voltage, electrolyte capacitors are selected for a CI1 and CI2. The voltage and current in capacitor CI1 and CI2 are shown in Fig. 14. During charging, the voltages and currents of the capacitors are positive and negative for discharging. Ten percentage of change in the capacitor voltage (\(\Delta Vc\)) is allowed during discharging.

Fig. 14
figure 14

Voltage and current a capacitor CI1 b capacitor CI2

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The Voltage across DC Bus is shown in Fig. 15. During the period t0–t1, t7–t9, and t15–t16 are capacitors CI1 and CI2 are getting a charge from the SSHGC. The voltage across the DC bus is equal to VO(DC). The voltage across CI2 is appeared across DC Bus and during the charging mode load is disconnected through switches S1, S2, S3, and S4. The switches S1, S2, S3, and S4 are operated to connect the capacitors with the DC bus to produce DC bus voltage is equal to V0(DC), 2V0(DC), and 3V0(DC). DC bus voltage when the constant switching pulses are applied to switch S1 to S4 is shown in Fig. 15a. When the switches are enabled with constant pulses, the voltage across the DC bus is seemed as V0(DC), 2V0(DC), and 3V0(DC).SPWM is used to improve the efficiency of the system and the THD of the AC output is also reduced. Switches S6, S7, S8, and S9 are used to convert the DC bus voltage into AC voltage. SPWM pulses are applied to switches S1, S2, S3, and S4.

Fig. 15
figure 15

DC bus voltage and current a constant switching pulse b SPWM

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Figure 15b shows the DC bus voltage when the SPWM pulses are applied to switch S1 to S4. During the period (t1–t2) the SPWM pulse applied to switch S4 and the DC bus voltage exist between V0(DC) and Zero, (t2–t3) SPWM pulses are applied to S2 and S4. The switch S4 gets the complementary pulse of S2, (t3–t4) SPWM pulses are applied to S1 and S2. The switch S2 gets the complementary pulse of S1. During the period t2–t3, the voltage across the DC bus exists between V0(DC) and 2V0(DC), the period between t3–t4 the Voltage across DC bus exists between 2V0(DC) and 3V0(DC).

The output load voltage and load current across the resistive load are shown in Fig. 16a and b. Load is connected across the output of the seven-level inverter. Figure 16a shows the load voltage and current when constant pulses to switches S1–S4. Figure 16b shows the load voltage and current when the SPWM pulses to switches S1–S4. In both cases, the load voltage and current are in phase. Small voltage variation in the output voltage is existed due to the voltage variation of capacitors during discharge.

Fig. 16
figure 16

AC output voltage and current a constant switching pulse b SPWM

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The DC–AC inverting system, output AC power should meet the IEEE Std 519. The percentage of THD value is essential in DC–AC inverter design. The AC voltage and current should be less than 3% of THD value in order to drive all kinds of AC load. More THD value creates undesirable factors like harmonics and power quality issues. THD Analysis is performed in the proposed inverter and results are shown in Fig. 17. The results show the THD value is 0.18% when it feeds the AC power to a resistive load (Fig. 18).

Fig. 17
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THD analysis of load voltage

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Fig. 18
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Hardware prototype of the proposed system

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6 Conclusion

A high gain DC–DC–AC converter is proposed. Gain is achieved in both DC–DC and DC–AC Conversion. The comparative gain analysis shows the significance of the proposed SSHGC. P&O algorithm is used to extract maximum Power from PVM. The output of the DC–DC converter is fed to MLI. The proposed inverter has the unique future of triple voltage gain and generates seven-level AC output. The switching capacitor technique is used in the inverter circuit in order to achieve more voltage gain. The hardware prototype is designed to validate the proposed system. The Experimental results are verified with theoretical analysis and simulation results. SPWM technique is used to control the inverter to improve the quality of output AC voltage. The maximum voltage gain of the DC–DC converter is 12, and DC–AC Inverter is 3. The overall voltage gain of the proposed system is 36. The efficiency of the DC–DC converter is 92.5%, and the DC–AC inverter is 93%. The overall efficiency of the system is 86%. THD of the AC output is 0.18%. The significant advantage of the proposed DC–DC–AC converter is its simple topology, the excellent tackling capability of MPPT control, Voltage gain is achieved in DC–DC and DC–AC stages. The proposed DC–DC–AC system is suitable for PV-based standalone and grid-connected systems.