Keywords

1 Introduction

Recently, several minute devices have been developed to satisfy the demand for low power, low cost, reduced area, and high performance. The fabrication and performance analysis of Double-gate (DG) Fin shaped field-effect transistor (FinFET) has been demonstrated for the smaller gate length [12]. The obtained results proved that a FinFET device has been considered as a strong competitor as compared to classical CMOS [3, 7]. The adoption of semiconductor on insulator (SOI) technology for fabricating of microprocessors has become adorable research. Therefore, it is a convenient device for the mobile industry with features of better switching performance to satisfy the need for efficient battery life. Moreover, low power circuit design is a basic requirement in portable devices [8]. A nanoscale FinFET based SRAM cells with appropriate read and write stability are required for satisfying the increasing demand for large data storage, low power dissipation, and high performance [5, 13, 14]. The SRAM cells stability has been greatly affected by process variations, voltage, and temperature fluctuations. The degradation of stabilities has been examined for scaled dimensions and low power behavior of circuits[10, 11].

The endeavor of designing an improved n-FinFET and p-FINFET devices have been taken. The proposed devices demonstrate great improvements for SCEs and transconductance. NanoscaleFinFET based SRAM cell devised with six transistors has been simulated using 3D cogenda Technology Computer-Aided Design (TCAD) simulator for low power applications. The stability parameters read static noise margin (RSNM) and write static noise margin (WSNM) have been evaluated using the butterfly method. The dependence of static noise margin (SNM) metrics on voltage and temperature has also been realized for SRAM circuit. This work is organized as follows: Sect. 2 explains the simulation methodology used for designing the device and its circuit; Sect. 3 illustrates the device and circuit performance; Sect. 4 concludes the work done.

2 Design Description and Simulation Methodology of Finfet and Sram Cell

The specifications of nanoscale FinFET device and the SRAM cell have been delineated in Tables 1 and 2, respectively. The three-dimensional simulator cogenda TCAD has been used for devising the device and its circuit. Figure 1 shows the 3D structure of designed n-FinFET and p-FinFETdevices. The gate electrodes, n-polysilicon (4.5 eV), and p-ploysilicon (4.85 eV)have been used for n-FinFET and p-FinFET respectively at 300 K. The SiO2 is considered as interfacial oxide; aluminium& tungsten is used as metal contacts. Figure 2 outlines the schematic and layout structure of nanoscaleFinFET based SRAM cell. The flow chart of simulation procedure done in visual TCAD has been shown in Fig. 3 [2].

Table 1 Device parameters used in TCAD
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Table 2 Parameters for an SRAM design
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Fig. 1
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Bird eye view of 3D SOI FinFET structure: a n-FinFET. b Top view of n-FinFET& p-FinFET

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Fig. 2
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Nanoscale FinFET based SRAM cell implemented in TCAD environment. a Schematic. b Layout

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Fig. 3
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Flow chart of simulation procedure of visual TCAD

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The set of performance metrics have been calculated for the designed FinFET device namely, drain current at maximal value of gate voltage (on-current, ION), drain current at minimum gate voltage (off-current, IOFF), ION/IOFF current ratio, drain induced barrier lowering (DIBL) and subthreshold swing (SS). These parameters have been computed with gate voltage (Vg)variation of 0 to 1.0 V and drain voltage (Vd) of 50 mV and 1.0 V as boundary conditions. SS indicates the gate potential requisite for altering the drain current by one decade. Equation (1) states the formula for the evaluation of the SS.

$${\text{SS}} = \frac{{\partial V_{g}^{{}} }}{{\partial \log_{10} I_{d} }}$$
(1)

where Id indicates drain current in amperes. Subthreshold swing manifests the capability of the transistor to overcome the subthreshold regime. DIBL is calculated as the difference of gate voltage corresponding to both 50 Mv and 1 V drain voltage (Vd) at drain current (IDIBL) of 2.83 × 10−7 A which is determined with the formulae stated in Eq. (2).

$$I_{\text{DIBL}} = \frac{\text{Weff}}{Lg} \times 10^{ - 7} {\text{ A}}$$
(2)
$${\text{Weff}} = 2H_{\text{Fin}} + W_{\text{Fin}}$$
(3)

where Lg is length of gate and Weff is the channel effective width which employs the fin height and fin width as in Eq. (3). Transconductance is evaluated by dividing the changing drain current and the changing gate voltage keeping drain voltage constant. It is expressed as gm = (∂Id/∂Vg) Siemen [1, 6].

The memory circuit performance metrics based on voltage transfer curve include RSNM and WSNM. The ability to read data from SRAM circuit without flipping is characterized by RSNM. It also describes the robustness of SRAM. WSNM is another stability parameter that measures the writing ability of SRAM cells [5, 13, 14].

3 Results and Discussions

  1. (A)

    Device Performance:

The input and output characteristic curves of SOI nanoscale n-FinFET and p-FINFET for different drain voltages are shown in Fig. 4a, b. The VI characteristic of n-FINFET is plotted on the right side of the figure where the similar VI curve for p-FINFET is shown on left side of the figure. It is observed from Fig. 4a that almost the same ION and IOFF currents are obtained for two devices for similar dimensions in two operating regions i.e. saturation region at Vd = 0.75 and linear region at Vd = 50 mV. The extracted SCE metrics and transconductance values are mentioned in Table 3[1, 6].

Fig. 4
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VI characteristics of n-FINFET and p-FinFET. a Input. b Output

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Table 3 Extracted electrical characteristics of FinFETs
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  1. (B)

    Circuit Performance:

  1. (i)

    The schematic of SRAM cell for read operation is outlined in Fig. 5a. In read operation, the bit-lines (BL and BLB) are biased to supply voltage (Vd) and wordline (WL) is connected to Vd. In this situation, access transistors M5 and M6 are switched on. Let us assume, “1” data is saved at Q, and “0” is saved at Qbar, M1 and M4 devices are switched off and M3 and M2 are switched on. Therefore, current will flow through BLB-M6-M2 as shown in Fig. 5a. Hence, voltage level of bit-line BLB discharges and voltage level of BL maintains at Vd. Figure 6 demonstrates the waveforms for read operation implemented in TCAD environment. Figure 6a displays the potential at different nodes of SRAM cell during read operation where Fig. 6b delineates the current, potential, and power at wordline (WL). Therefore, a successful read operation has been realized for simulated circuits. Figure 5b shows the schematic of designed cell for write operation. In write operation, the voltages of bit-lines (BL and BLB) are opposite to each other, and wordline (WL) is connected to Vd. In this situation, access devices M5 and M6 are switched on. This will drop the voltage level of Qnode and raises the voltage level of Qbar node until the voltage level of Q node is enough to switch on M4 and switch off M2or the voltage level at node Qbar is good enough to switch on M3 and switch off M1. Finally, the voltage level of nodes Qbar and Q will be turned over to ‘1’ and ‘0’, respectively. Figure 7 delineates the waveforms obtained after a successful write operation performed in TCAD for nanoscale FinFET based 6T SRAM cell [9].

    Fig. 5
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    Operations of 6T SRAM cell using nanoscale FinFET. a Schematic diagram for Read operation. b Schematic diagram for Write operation

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    Fig. 6
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    Waveforms for read operation performed in TCAD for FinFET based 6T SRAM cell

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    Fig. 7
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    Waveforms for write operation performed in TCAD for FinFET based 6T SRAM cell

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  2. (ii)

    The SRAM circuit stability has been measured by SNM. It is stated as the largest DC margin for which the cell condition does not flip during its access. The butterfly curve method is used for estimating SNM of a bit cell as shown in Fig. 8b corresponding to setup outlined in Fig. 8a. The square fitting method is utilized for determining RSNM. It is the largest square to be fitted in between overlapped plot of inverter transfer characteristics and its inverse characteristics. Similarly, WSNM is extracted as displayed in Fig. 8 [5, 13, 14].

    Fig. 8
    figure 8

    Butterfly curve method of FinFET based 6T SRAM cell for measuring RSNM and WSNM

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  3. (iii)

    The dependence of stability on temperature is shown in Fig. 9a. It is noticed that with the increase in temperature, RSNM and WSNM decreases due to increment of the random variation effects because of exponential dependence of current on sub-threshold operation. It is observed that RSNM and WSNM are reduced by 56% and as 16% as temperature varies from 253 to 450 K. The dependence of stability on voltage is illustrated in Fig. 9b. It can be clearly seen that both RSNM and WSNM are degrading for reduced supply voltage which explains the effects of voltage scaling [10, 11].

    Fig. 9
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    Dependence of SRAM cell stabilities on temperature and supply voltage. a Impact of temperature on stability. b Impact of supply voltage on stability

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4 Conclusion

  • In this work, the electrical characteristics of nanoscale FinFET devices have been discussed for low supply voltage. It has been noted that simulated devices show 47.4% improvement for DIBL and 7.32% enhancement for SS as compared to results extracted by authors [4].

  • Further, low power and miniaturized FinFET based 6T SRAM cell have been demonstrated along with the calculation of SNM values using the butterfly curve method. The progress of WSNM for designed SRAM cell is 8.6% as compared to results demonstrated by researchers [4].

  • The impact of voltage and temperature variations on the stability of SRAM cell has also been discussed. The obtained values show improvement as compared to previous work.

  • The miniaturized FinFET devices have lower leakage current and reduced power consumption as compared to the planar transistors. Therefore, nanoscaled FinFET technology has been considered as economical, reliable, sustainable, and energy-efficient for future generations. These devices could become an essential part of microprocessors in the future.