Abstract
Junctionless transistor (JLT) which does not have a PN junction in the source-channel-drain path, is reported to have a lower OFF-state current and therefore is more scalable to lower channel lengths compared to a conventional MOSFET, moreover a JLT also offers easy fabrication steps. Tunnel FET (TFET) provides a theoretically possible limit of subthreshold swing (SS) and has applicability for low-power electronics. Combining junctionless technology in a TFET (JL-TFET), the possible application of the device is looked into, for further low-power and high-temperature applications. This work analyses the performances of a JL-TFET for high-temperature applications and the same is compared with a conventional p-i-n silicon-on-insulator tunnel field effect transistor (p-i-n SOI-TFET). Using calibrated technology computer-aided design (TCAD) simulations, analog circuit performance parameters like ON-state to OFF-state current ratio (\({{\varvec{I}}}_{{\varvec{O}}{\varvec{N}}}/{{\varvec{I}}}_{{\varvec{O}}{\varvec{F}}{\varvec{F}}}\)), subthreshold slope (SS), transconductance (\({{\varvec{G}}}_{{\varvec{m}}}\)), gate-to-source capacitance (\({{\varvec{C}}}_{{\varvec{G}}{\varvec{S}}}\)), gate-to-drain capacitance (\({{\varvec{C}}}_{{\varvec{G}}{\varvec{D}}}\)), and cut-off frequency (\({{\varvec{f}}}_{{\varvec{T}}}\)) etc. are analyzed for temperatures till 500 K. ON-state current of JL-TFET increases in the order of hundreds of \({\varvec{\mu}}{\varvec{A}}/{\varvec{\mu}}{\varvec{m}}\) at high temperatures, whereas p-i-n SOI-TFET shows lesser temperature sensitivity. JL-FET is more applicable to low-power applications, whereas a p-i-n SOI-TFET has more suitability for high-speed applications. Dual material technology adoption helps in improving the ambipolar behavior of the device. Analysis of interface traps is carried out in this architecture where the concentration, energy positions, and energy width of the distribution of acceptor-like and donor-like traps at the interface of semiconductor and oxide are also evaluated.
Article PDF
Similar content being viewed by others
Explore related subjects
Discover the latest articles, news and stories from top researchers in related subjects.Avoid common mistakes on your manuscript.
Data Availability
All the material/Simulator license is owned by the authors and/or no permissions are required. The data(s) are available to the journal if required.
References
Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225–322
Colinge JP, Kranti A, Yan R, Lee CW, Ferain I, Yu R, Dehdashti AN, Razavi P (2011) Junctionless nanowire transistor (JNT): Properties and design guidelines. Solid State Electron 65:33–37
Strangio S, Palestri P, Esseni D, Selmi L, Crupi F, Richter S, Zhao QT, Mantl S (2015) Impact of TFET unidirectionality and ambipolarity on the performance of 6T SRAM cells. IEEE J Electron Devices Soc 3:223–232
Gedam A, Acharya B, Mishra GP (2021) Junctionless silicon nanotube TFET for improved DC and radio frequency performance. Silicon 13:167–178
Nigam K, Gupta S, Pandey S, Kondekar PN, Sharma D (2018) Controlling the ambipolarity and improvement of RF performance using Gaussian Drain Doped TFET. Int J Electron 105:806–816
Nagavarapu V, Jhaveri R, Woo JCS (2008) The tunnel source (PNPN) n-MOSFET: a novel high-performance transistor. IEEE Trans Electrons Devices 55:1013–1019
Saurabh S, Kumar MJ (2011) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electrons Devices 58:404–410
Strangio S, Palestri P, Lanuzza M, Crupi F, Esseni D, Selmi L (2016) Assessment of InAs/AlGaSb tunnel-FET virtual technology platform for low-power digital circuits. IEEE Trans Electron Devices 63:2749–2756
Chattopadhyay A, Mallik A (2011) Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel fieldeffect transistor. IEEE Trans Electron Devices 58:677–683
Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling fieldeffect transistors. IEEE Trans Electron Devices 57:2317–2319
Agarwal S, Yablonovitch E, Liu TJK, Kuhn K (2015) Designing a low voltage, high current tunneling transistor. Cambridge University Press, Cambridge, pp 79–116
Xiao TP, Zhao X, Agarwal S, Yablonovitch E (2015) Impact of interface defects on tunneling FET turn-on steepness. In 2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S) IEEE, pp 1–2
Nigam K, Kondekar PN, Chandan BV, Kumar S, Tikkiwal VA, Singh K, Bhardwaj E, Choubey S, Chaturvedi S (2022) Performance and analysis of stack junctionless tunnel field effect transistor. Silicon 14:1549–1558
Tirkey S, Sharma D, Yadav DS, Yadav S (2017) Analysis of a novel metal implant junctionless tunnel FET for better DC and analog/RF electrostatic parameters. IEEE Trans Electron Devices 64:3943–3950
Routh S, Deb D, Baruah RK, Goswami R (2022) Junctionless tunnel FET for high-temperature applications from an analog design perspective. In 2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO) IEEE, pp 1–4
Fleetwood DM, Winokur PS, Reber RA Jr, Meisenheimer TL, Schwank JR, Shaneyfelt MR, Riewe LC (1993) Effects of oxide traps, interface traps and border traps on metal-oxide-semiconductor devices. J Appl Phys 73:5058–5074
Lyu JS, Lee KSN (1993) Determination of the interface trap density in metal oxide semiconductor field-effect transistor through subthreshold slope measurement. Jpn J Appl Phys 32:4393
Deb D, Goswami R, Baruah RK, Kandpal K, Saha R (2021) An SOI npn double gate TFET for low power applications. In 2021 Devices for Integrated Circuit (DevIC) IEEE, pp 621–623
Singh KS, Kumar S, Nigam K (2020) Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET. IEEE Trans Device Mater Reliab 20:404–412
Singh AK, Tripathy MR, Baral K, Singh PK, Jit S (2020) Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate. Appl Phys A 126:1–11
Qiu Y, Wang R, Huang Q, Huang R (2014) A comparative study on the impacts of interface traps on tunneling FET and MOSFET. IEEE Trans Electron Devices 61:1284–1291
Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices 54:1725–1733
Ehteshamuddin M, Alharbi AG, Loan SA (2018) Impact of interface traps on the BTBT-current in tunnel field effect transistors. In 2018 5th International Conference on Electrical and Electronic Engineering (ICEEE) IEEE, pp 224–227
Tripathy MR, Samad A, Singh AK, Singh PK, Baral K, Mishra AK, Jit S (2021) Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide. Microelectron Reliab 119:114073
Pezzimenti F, Bencherif H, De Martino G, Dehimi L, Carotenuto R, Merenda M, Della Corte FG (2021) Study and assessment of defect and trap effects on the current capabilities of a 4H-SiC-based power MOSFET. Electronics 10:735
Fan ML, Hu VPH, Chen YN, Su P, Chuang CT (2013) Analysis of single-trap-induced random telegraph noise and its interaction with work function variation for tunnel FET. IEEE Trans Electron Devices 60:2038–2044
Fan ML, Yang SY, Hu VPH, Chen YN, Su P, Chuang CT (2014) Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. Microelectron Reliab 54:698–711
Ghosh P, Bhowmick B (2020) Effect of temperature in selective buried oxide TFET in the presence of trap and its RF analysis. Int J RF Microwave Comput Aided Eng 30:22269
Ghosh P, Roy A, Bhowmick B (2020) The impact of donor/acceptor types of interface traps on selective buried oxide TFET characteristics. Appl Phys A 126:330
Gupta S, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET. IEEE Trans Electron Devices 64:4731
Huang XY, Jiao GF, Cao W, Huang D, Yu HY, Chen ZX, Singh N, Lo GQ, Kwong DL, Li MF (2010) Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors. IEEE Electron Device Lett 31:779
Beneventi GB, Gnani E, Gnudi A, Reggiani S, Baccarani G (2013) Can interface traps suppress TFET ambipolarity? IEEE Electron Device Lett 34:1557
Pandey R, Saripalli V, Kulkarni JP, Narayanan V, Datta S (2014) Impact of single trap random telegraph noise on heterojunction TFET SRAM stability. IEEE Electron Device Lett 35:393
Sant S, Schenk A, Moselund K, Riel H (2016) Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero tunnel FETs. In 2016 74th Annual Device Research Conference (DRC) IEEE, pp 1–2
Priya LG, Balamurugan NB (2019) New dual material double gate junctionless tunnel FET: subthreshold modeling and simulation. AEU-Int J Electron C 99:130–138
Basak S, Asthana PK, Goswami Y (2015) Leakage current reduction in junctionless tunnel FET using a lightly doped source. Appl Phys Letters 118:1527–1533
Ghosh B, Akram MW (2013) Junctionless tunnel field effect transistor. IEEE Electron Device Lett 34:584–586
Jain P, Prabhat V, Ghosh B (2015) Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material. Comput J Electron 14:537–542
Sentaurus Device User: Sentaurus TCAD Version R-2020.09-SP1
Schenk A (1992) model for the field and temperature dependence of SRH lifetimes in silicon”. Solid State Electron 35:1585–1596
Raushan MA, Alam N, Akram MW, Siddiqui MJ (2018) Impact of asymmetric dual-k spacers on tunnel field effect transistors. J Comput Electron 17:756–765
Narang R, Saxena M, Gupta RS, Gupta M (2013) Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans Nanotechnol 12:951–957
Baruah RK, Paily RP (2012) High-temperature effects on device performance of a junctionless transistor. International Conference on Emerging Electronics, pp 1–4
Biswas A, Dan SS, Royer CL, Grabinski W, Lonescu AM (2012) TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Microelectron Eng 98:334–337
Mishra V, Verma YK, Agarwal L, Gupta SK (2021) Temperature impact on device characteristics of charge plasma based tunnel FET with Si 0.5 Ge 0.5 source. Eng Res Express 3:045012
Shaikh MU, Loan S (2019) Drain-engineered TFET with fully suppressed ambipolarity for high-frequency application. IEEE Trans on Electron Devices 66:1628–1634
Tiwari S, Saha R (2021) Methods to reduce ambipolar current of various TFET structures. A review. Silicon 1–9
Goswami R, Bhowmick B, Baishya S (2015) Electrical noise in Circular Gate Tunnel FET in presence of interface traps. Superlattices Microstruct 86:342–354
Wang W, Hwang J, Xuan T, Ye PD (2011) Analysis of electron mobility in inversion-mode MOSFETs. IEEE Trans Electron Devices 58:1972–1978
Ehteshamuddin M, Alharbi AG, Loan SA (2018) Impact of interface traps on the BTBT-current in tunnel field effect transistors. 5th International Conference on Electrical and Electronic Engineering (ICEEE). IEEE, pp 224–27
Pezzimenti F, Bencherif H, Martino GD, Dehimi L, Carotenuto R, Merenda M, Corte FGD (2021) Study and assessment of defect and trap effects on the current capabilities of a 4H-SiC-based power MOSFET. Electronics 10:735
Deb D, Goswami R, Baruah RK, Kandpal K, Saha R (2022) Parametric investigation and trap sensitivity of N-p-N double gate Tfets. Comput Electr Eng 100:107930
Funding
This work was supported by DST FIST II (Grant number: SR/FST/ET-II/2018/241). Author A has received research support from All India Council for Technical Education (Grant number: 1–6382306131).
Author information
Authors and Affiliations
Contributions
Ratul Kumar Baruah conceptualized the work. Simulation and analysis were performed by Sujay Routh, Deepjyoti Deb supported by Ratul Kumar Baruah and Rupam Goswami. The first draft of the manuscript was written by Ratul Kumar Baruah, Sujay Routh, and Deepjyoti Deb and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript. Sujay Routh and Deepjyoti Deb contributed equally to this work.
Corresponding author
Ethics declarations
Ethics Approval
The results/data/figures in this manuscript have not been published elsewhere, nor are they under consideration from any of the Contributing Authors by another publisher.
Consent to Participate
All authors have consent to submit the work in this journal.
Consent for Publication
We have read and understood the publishing policy and submit this manuscript in accordance with this policy.
Competing Interests
We declare that the authors have no competing interests as defined by Springer, or other interests that might be perceived to influence the results and/or discussion reported in this paper.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
Routh, S., Deb, D., Baruah, R.K. et al. Impact of High-temperature and Interface Traps on Performance of a Junctionless Tunnel FET. Silicon 15, 2703–2714 (2023). https://doi.org/10.1007/s12633-022-02191-8
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s12633-022-02191-8