1 Introduction

The current-mode (CM) circuits have received significant attentions in recent years as they have advantages of high slew-rate, wide bandwidth, small nonlinear distortion, large dynamic-range and so on. The Second-Generation Current Conveyor (CCII) is introduced in 1970 [1], and it is a versatile and flexible building block in current-mode analog circuit design [2–8]. However, CCII has two main drawbacks: (1) large voltage tracking error from terminal Y to terminal X because of the parasitic resistor of terminal X, which leads to transfer function error; (2) lack of electronically tunable feature, which means the parameters can not be adjusted by additional bias current.

In 1996, A. Fabre proposed a CCCII [9]. It possesses electronically tunable function by utilizing the parasitic floating intrinsic transimpedance at port X (RX), which can be tuned electronically by adjusting the bias current.

In the past, the core of CCCII is simply constructed by the mixed translinear-loop, which is originally realized in BJT [10, 11] and later in MOSFET [12–15]. BJT has advantages of low noise and high operating frequency, but it is not compatible with CMOS VLSI technology, so it is inconvenient for VLSI integration. Minaei proposed a CMOS CCCII circuit based on MOS translinear loop in 2002 and Al-Shahrani proposed a CMOS CCCII based on source-coupled differential pair input stage in 2003 [16]. However, the CCCII based on MOS translinear-loop has unsymmetrical dynamic-range and strict restrictive condition in fabrication technology. Meanwhile, CMOS CCCII based on source-coupled differential pair has poor input voltage range and low linearity. Hence, the objective of this paper is to present a new CMOS CCCII with high linearity to overcome the problems mentioned above, then it can be better applied in more application fields [17–25], such as chaotic system, oscillators, current mode filters, radio frequency oscillators, low noise amplifiers, ASK/FSK modulators and so on [26–28].

This paper is organized as follows: the cross-coupled differential pair input stage and the proposed novel CMOS CCCII are described in Sects. 2 and 3, respectively. The PSPICE simulation results of this proposed CCCII circuit in TSMC 0.18 μm CMOS RF technology and performance comparison with other reported circuits are included in Sect. 4. To further illustrate merits of this proposed CMOS CCCII, A current-mode universal filter is simulated in Sects. 5 and 6.

2 The Cross-Coupled Differential Pair Input Stage

Assuming that all MOSFET are enhancement-mode types and biased in saturation region with substrates connected to their respective sources. Then the body effect is ignored and the transistor drain current can be approximated by the relation [29]:

$$ I_{D} = k\left( {V_{GS} - V_{TH} } \right)^{2} $$
(1)

where V GS is gate-source voltage, V TH is the threshold voltage, k = (W/L)μC ox /2 is the trans- conductance parameter, W and L are width and length of the transistor channel, μ is the effective surface carrier mobility and C ox is the gate oxide capacitance per unit area. The channel length modulation effect is not included in (1).

The CCCII circuit symbol is illustrated in Fig. 1 and its ideal defining equation can be given as [12]:

$$ \left[ {\begin{array}{*{20}l} {{\text{I}}_{\text{y}} } \hfill \\ {{\text{V}}_{\text{x}} } \hfill \\ {{\text{I}}_{\text{z}} } \hfill \\ \end{array} } \right] = \left[ {\begin{array}{*{20}l} 0 \hfill & 0 \hfill & 0 \hfill \\ 1 \hfill & {{\text{R}}_{\text{x}} } \hfill & 0 \hfill \\ 0 \hfill & { \pm 1} \hfill & 0 \hfill \\ \end{array} } \right]\left[ {\begin{array}{*{20}l} {{\text{V}}_{\text{y}} } \hfill \\ {{\text{I}}_{\text{x}} } \hfill \\ {{\text{V}}_{\text{z}} } \hfill \\ \end{array} } \right] $$
(2)
Fig. 1
figure 1

Circuit symbol of CCCII

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In Fig. 1, terminal X is a current input which possesses low input impedance; terminal Y is a voltage input which possesses high input impedance; Z+ is the non-inverting current output port, and Z− is the inverting current output port. Ib is the biasing current, by which the voltage relation between terminal X and terminal Y is adjustable.

The current output at port Z(iz), which is conveyed from the input current at port X(ix), can be expressed as [14]:

$$ i_{x} = \pm i_{z} = \pm \frac{{v_{x} - v_{y} }}{{R_{x} }} $$
(3)

As R x is the parasitic resistance, the CCCII-based application can be realized in resistor-free and tunable architectures by utilizing R x as the adjustable circuit parameter. To better understand the function of CCCII, the equivalent circuit of it is displayed in Fig. 2.

Fig. 2
figure 2

Equivalent circuit of a CCCII

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Considering a matched transistor pair (Mn1, Mn2) coupled by two voltage sources with equal value of \( ({\text{V}}_{\text{TH}} + {\text{V}}_{x} ) \), which is shown in Fig. 3. Representing \( (V_{2} - V_{1} ) \) by ν, using (1) gives:

$$ I_{1} = k\left( {V_{x} - v} \right)^{2} $$
(4a)
$$ I_{2} = k\left( {V_{x} + v} \right)^{2} $$
(4b)
Fig. 3
figure 3

Schematic diagram of cross-coupled input stage

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The output current \( i_{x} = I_{1} - I_{2} \), obtained by a simple p-channel current mirror, will be

$$ i_{x} = I_{1} - I_{2} = 4kV_{x} v $$
(5)

Thus this configuration exhibits a perfectly linear transconductance of value \( G_{m} = 4kV_{x} \).

3 The Proposed CMOS CCCII

Considering a actual implementation of the circuit described in Fig. 3, the sources \( ({\text{V}}_{\text{TH}} + {\text{V}}_{x} ) \) are substituted by two additional n-channel transistors (Mn3 and Mn4) biased by constant currents. The practical circuit configuration is displayed in Fig. 4. Mn1 and Mn4 share a same p-well connected to their common source node, whereas Mn2 and Mn3 are in a separate well to avoid back-gate bias effects. For obtaining reasonable voltage sources with low source impedance, these devices must be biased with currents which are larger than the signal currents through them.

Fig. 4
figure 4

Practical circuit configuration of cross-coupled input stage

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Mn1, Mn2, Mn3 and Mn4 have the same channel length, but the channel widths of Mn3 and Mn4 are made n times wider than Mn1 and Mn2. For maintaining the value of \( {\text{V}}_{b} = \sqrt {{{I_{0} } \mathord{\left/ {\vphantom {{I_{0} } k}} \right. \kern-0pt} k}} \), Mn3 and Mn4 are biased with nI 0 . Defining normalized variables \( {\text{X}} = {{{\text{V}}_{\text{XY}} } \mathord{\left/ {\vphantom {{{\text{V}}_{\text{XY}} } {{\text{V}}_{\text{b}} }}} \right. \kern-0pt} {{\text{V}}_{\text{b}} }} \) and \( {\text{Y}} = {{i_{x} } \mathord{\left/ {\vphantom {{i_{x} } {\text{I}}}} \right. \kern-0pt} {\text{I}}}_{ 0} \) with reference to Fig. 4, we write:

$$ Y_{1} = {{i_{1} } \mathord{\left/ {\vphantom {{i_{1} } {I_{0} }}} \right. \kern-0pt} {I_{0} }} = - \gamma X^{2} + \frac{\alpha }{2}X\sqrt {1 - \beta X^{2} } $$
(6a)
$$ Y_{ 2} = {{i_{ 2} } \mathord{\left/ {\vphantom {{i_{ 2} } {I_{0} }}} \right. \kern-0pt} {I_{0} }} = \gamma X^{2} + \frac{\alpha }{2}X\sqrt {1 - \beta X^{2} } $$
(6b)

where

$$ V_{XY} = V_{X} - V_{Y} $$

and

$$ \alpha = {{4n} \mathord{\left/ {\vphantom {{4n} {\left( {n + 1} \right)}}} \right. \kern-0pt} {\left( {n + 1} \right)}},\quad \beta = {n \mathord{\left/ {\vphantom {n {\left( {n + 1} \right)}}} \right. \kern-0pt} {\left( {n + 1} \right)}}^{2} ,\quad \gamma = {{n\left( {n - 1} \right)} \mathord{\left/ {\vphantom {{n\left( {n - 1} \right)} {\left( {n + 1} \right)^{2} }}} \right. \kern-0pt} {\left( {n + 1} \right)^{2} }} $$
(6c)

The output \( {\text{Y}} = {{i_{x} } \mathord{\left/ {\vphantom {{i_{x} } I}} \right. \kern-0pt} I}_{ 0} = {{\left( {i_{1} + i_{2} } \right)} \mathord{\left/ {\vphantom {{\left( {i_{1} + i_{2} } \right)} {I_{0} }}} \right. \kern-0pt} {I_{0} }} \) is obtained as

$$ Y = \alpha X\sqrt {1 - \beta X^{2} } \quad \left( {\left| X \right| \le \sqrt {{{\left( {n + 1} \right)} \mathord{\left/ {\vphantom {{\left( {n + 1} \right)} n}} \right. \kern-0pt} n}} } \right) $$
(7)

We can change the formula by following equation

$$ i_{x} = \alpha \sqrt {kI_{0} } V_{XY} \sqrt {1 - {{\beta kV_{XY}^{2} } \mathord{\left/ {\vphantom {{\beta kV_{XY}^{2} } {I_{0} }}} \right. \kern-0pt} {I_{0} }}} $$
(8)

From (6c) and (7), the estimation of symmetrical dynamic-range of the cross-coupled input stage is

$$ \left| {V_{XY} } \right| \le \sqrt {{{\left( {n + 1} \right)} \mathord{\left/ {\vphantom {{\left( {n + 1} \right)} n}} \right. \kern-0pt} n}} \cdot \sqrt {{{I_{0} } \mathord{\left/ {\vphantom {{I_{0} } k}} \right. \kern-0pt} k}} $$
(9)

and the roughly linear input range is

$$ \left| {V_{XY} } \right| < < \left( {{{\left( {n + 1} \right)} \mathord{\left/ {\vphantom {{\left( {n + 1} \right)} {\sqrt n }}} \right. \kern-0pt} {\sqrt n }}} \right) \cdot \sqrt {{{I_{0} } \mathord{\left/ {\vphantom {{I_{0} } k}} \right. \kern-0pt} k}} $$
(10)

For n = 10, in order to obtain better than 1 percent linearity, the actual linear input range is

$$ \left| {V_{XY} } \right| \le \sqrt {{{I_{0} } \mathord{\left/ {\vphantom {{I_{0} } k}} \right. \kern-0pt} k}} $$
(11)

During the linear input range, we know the parasitic resistor is

$$ R_{x} = \left( {\frac{40}{11} \cdot \sqrt {kI_{0} } } \right)^{ - 1} $$
(12)

For large n, we can obtain wider linear input range. For n = 1, we obtain \( \alpha = 2 \), \( \beta = 0.25 \), \( \gamma = 0 \), and the two equations become identical. With the value of n is increased, β becomes smaller, resulting in improved linearity in the transfer characteristics. For \( n > > 1 \), from (6c) we get \( \alpha \cong 4 \), \( \gamma \cong 1 \), and \( \beta \cong {1 \mathord{\left/ {\vphantom {1 n}} \right. \kern-0pt} n} \). In the limit as \( n \to \infty \), \( \beta \to 0 \) and a linear parasitic resistance \( R_{x} = {1 \mathord{\left/ {\vphantom {1 {4\sqrt {kI_{0} } }}} \right. \kern-0pt} {4\sqrt {kI_{0} } }} \) is obtained over the entire range \( \left| X \right| \le 1 \) (i.e.\( \left| {V_{XY} } \right| \le \sqrt {{{I_{0} } \mathord{\left/ {\vphantom {{I_{0} } k}} \right. \kern-0pt} k}} \)). Furthermore, the circuit is also operated for input voltages well outside this range, though in a nonlinear fashion. The maximum available input current is \( \left( {n + 1} \right)I_{0} \).

Figure 5 shows the proposed CCCII ± circuit, of which the Z ± differential pair is identical to the active loaded NMOS differential pair of the input stage. For maintaining the same value of drain current, Mn5 and Mn6, Mn7 and Mn8 have the same size of Mn1 and Mn2, while biased with I0.

Fig. 5
figure 5

The proposed CCCII ± circuit

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For the Z+ differential pair of Fig. 5, we can get:

$$ i_{n6} = i_{n2} $$
(13)
$$ i_{p4} = i_{p3} = i_{n5} = i_{n1} = i_{p1} = i_{p2} $$
(14)

Therefore, the \( i_{x} \) and \( i_{z} \) are approximated equal through the condition shown in (15):

$$ i_{z} = i_{n6} - i_{p4} = i_{n2} - i_{p2} = i_{x} $$
(15)

The Z− differential pair which horizontally flipped from the Z+ differential pair yields:

$$ i_{n5} = i_{n1} = i_{p1} = i_{p2} $$
(16)
$$ i_{p3} = i_{p4} = i_{n6} = i_{n2} $$
(17)

From (16) and (17), we can get:

$$ i_{z} = i_{n5} - i_{p3} = i_{p2} - i_{n2} = - i_{x} $$
(18)

In summary, any required output properties of the CCCII can be generated by putting the appropriate Z+ or Z− pairs in concurrent with the NMOS differential pair of the input stage. Three types of differential pairs illustrated in Fig. 6 are fundamental blocks for synthesizing a CCCII. As the input stage differential pairs must be existed, the number and type of output pairs can be selected to fulfill the requirement.

Fig. 6
figure 6

Proposed structure a input stage, b \( Z^{ + } \) pair, c \( Z^{ - } \) pair

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4 Performance Simulations

The proposed CMOS CCCII in Fig. 5 is simulated by PSPICE program. In the simulation process, the W/L ratios of each MOS transistor are shown in Table 1 and TSMC 0.18 µm CMOS RF technology parameters are used.

Table 1 W/L ratios of MOSFETS in Fig. 6
Full size table

The circuit uses 14 transistors with a ±1.5 V voltage supply and the DC biased current is 50 µA. From Table 1, we can get that Mn3 and Mn4 are made ten times wider than Mn1 and Mn2 with the same channel length of 0.18 µm.

In order to validate the correctness of (2), the static characteristic is firstly analyzed. By conducting DC scan for Y port, the voltage relationship between X and Y port is obtained and charted in Fig. 7. From the curve we can find that voltages of X and Y port meet the voltage relationship of (2) with very low offset-voltage. It exhibits a linear one-to-one voltage following characteristic over large voltage range as well as DC current transfer characteristics displayed in Fig. 8, but has little poor follower characteristic at port Z+.

Fig. 7
figure 7

DC transfer characteristic of Y and X port voltage

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Fig. 8
figure 8

DC current transfer characteristics of CCCII±

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In Fig. 9, the small signal current gain characteristics between terminals Z+ and X with grounded node Y is displayed. It is clearly that the 3 dB bandwidth of current gain approximates about 7.78 GHz. Fig 10 shows the small signal voltage gain between terminals X and Y when node Z is grounded. The 3 dB bandwidth of voltage gain is 11.61 GHz.

Fig. 9
figure 9

Current transfer gain

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Fig. 10
figure 10

Voltage transfer gain

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Table 2 compares the main performances of the proposed new CCCII described in Fig. 5 with those recently published relevant works. All these simulation results are obtained under a bias current of I0 = 50 μA. The symbols α0 and β0 represent current transfer (between X and Z) and voltage transfer (between Y and X), respectively. As exhibited in Table 2, the CCCII of Fig. 5 provides higher input impedance in Y port, wide input voltage range and higher 3 dB bandwidth for current and voltage gain.

Table 2 Simulation performances comparison of reported works and this paper
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Figure 11 shows the characteristics of R x at terminal X, and it is denoted that the simulation result of R x is nearly equal to 2.25 kΩ in the frequency range from 1 to 630 MHz at bias current I0 = 100 µA. Different R x values are also obtained at various bias current in the figure, which indicates that the transresistance of the new CCCII is electronically tunable in large bias current range.

Fig. 11
figure 11

Parasitic resistance R x when n = 10

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5 Application of the CCCII to Current-Mode Filter

The CCCII can be made electronically adjustable in different applications. In this section, a novel universal filter with single-input, triple-output employing only four elements (include two proposed CCCIIs) is presented in Fig. 12.

Fig. 12
figure 12

Current-mode universal filter uses the proposed CCCII

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This filter contains only two capacitors without requirement of any additional passive resistance and its structure can be characterized by the following expressions [26]:

$$ \frac{{I_{in} - I_{o1} - I_{o2} }}{{SC_{1} }} - I_{o1} R_{x1} = 0 $$
(19)
$$ \frac{{I_{o1} }}{{SC_{2} }} - I_{o2} R_{x2} = 0 $$
(20)

Then the transfer function of this circuit is given as follows:

$$ \frac{{I_{o1} }}{{I_{in} }} = \frac{{SR_{x2} C_{2} }}{{S^{2} R_{x1} C_{1} R_{x2} C_{2} + SR_{x2} C_{2} + 1}} $$
(21)
$$ \frac{{I_{o2} }}{{I_{in} }} = \frac{1}{{S^{2} R_{x1} C_{1} R_{x2} C_{2} + SR_{x2} C_{2} + 1}} $$
(22)
$$ \frac{{I_{o3} }}{{I_{in} }} = \frac{{S^{2} R_{x1} C_{1} R_{x2} C_{2} }}{{S^{2} R_{x1} C_{1} R_{x2} C_{2} + SR_{x2} C_{2} + 1}} $$
(23)
$$ \frac{{I_{o3} + I_{o2} }}{{I_{in} }} = \frac{{S^{2} R_{x1} C_{1} R_{x2} C_{2} + 1}}{{S^{2} R_{x1} C_{1} R_{x2} C_{2} + SR_{x2} C_{2} + 1}} $$
(24)
$$ \frac{{I_{o3} - I_{o1} + I_{o2} }}{{I_{in} }} = \frac{{S^{2} R_{x1} C_{1} R_{x2} C_{2} - SR_{x2} C_{2} + 1}}{{S^{2} R_{x1} C_{1} R_{x2} C_{2} + SR_{x2} C_{2} + 1}} $$
(25)

Equations (21)–(25) show that the proposed filter produces bandpass, lowpass, highpass, bandreject and all-pass responses simultaneously at its outputs. The natural frequency and the quality factor of the proposed circuit can be obtained as [26]:

$$ \omega_{0} = \frac{1}{{\sqrt {R_{x1} C_{1} R_{x2} C_{2} } }} $$
(26)
$$ Q = \sqrt {{{R_{x1} C_{1} } \mathord{\left/ {\vphantom {{R_{x1} C_{1} } {R_{x2} C_{2} }}} \right. \kern-0pt} {R_{x2} C_{2} }}} $$
(27)

The validity of the proposed filter is verified using PSPICE. For these simulations, the passive components are configured as C1 = C2 = 1nF and CCCIIs are implemented using the model in Fig. 5. The voltage supplies are taken as ±1.5 V and the bias current IB1 = IB2 = 100 µA. The results shown in Fig. 13 validate the feasibility of the proposed filter topology. By changing the bias current value of the two CCCIIs, the function of this filter can be adjusted.

Fig. 13
figure 13

Simulation result of the universal filter

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6 Conclusion

This paper proposes a new CMOS CCCII based on cross-coupled differential transistor pair instead of source-coupled as input stage. By using cross-coupled differential transistor pair and other improvements in circuit design, the presented topology has merits of wide input voltage range and improved maximum operational frequency with competitive linear performance under lower supply voltage. Simulation results obtained from PSPICE shows that the proposed circuit not only meets the port characteristics of standard CMOS CCCII but also conforms theoretical behavior prediction. As compared with previously reported works and analyzed a universal filter based on it, the proposed CCCII can be potentially applied in many fields for accomplishing high performance circuit systems.