1 Introduction

Metal–oxide–semiconductor (MOS) capacitors have been widely used for various applications because of their excellent optical and electrical properties [1]. The usability and suitability of a MOS capacitor in nanotechnology and semiconductor device industry depend on devices characteristic which are directly related to the gate dielectrics and their interfaces with the underlying semiconductors, especially for their electrical characteristics [2–5].

Hafnium silicates (HfSi04) may be a good alternative gate material with high dielectric constant. Hafnium silicate dielectric constant changed between 15 and 25 [6] depending on halfnium (Hf) content. It has excellent thermal stability, adequate band gaps, and compatibility for future MOS-based devices [7–10]. These characteristics of Hafnium silicate are related to the electrical stability of interface between gate oxide and underlying semiconductors [10]. In MOS capacitors, low interface quality causes some defects which can be examined under two headings. One of which is the surface state such as border traps, mobile ionic charges and oxide trapped charges. The other is series resistance. Due to the surface states and the series resistance defects, the electrical characteristics of MOS capacitor deviate from ideal behaviours [11, 12].

In this study, our aim is to investigate the frequency dependent electrical characteristics of Al/HfSiO4/p-Si (MOS) capacitors, especially focussing on oxide–semiconductor interface effect, i.e., interface states, border states and series resistance effects. In addition, the possible uses of HfSiO4 as a dielectric layer in MOS based technology were discussed from the obtained results. To do this, the electrical characterizations were investigated in the frequency range of 50 kHz to 1 MHz by the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements at room temperature. The measured capacitance and conductance were corrected in order to eliminate series resistance effects and find the real MOS capacitance. Using the corrected Gc/ω–V and Cc–V characteristics, the real interface state density (Dit) for each frequency was calculated. In addition, the capacitance hysteresis were measured and also corrected to examine borders state (Nbt) effects under applied voltage frequencies. Moreover, the doping concentration (NA), Fermi energy level (EF), diffusion potential (Vd), and barrier height (ΦB) as a function of frequency were obtained by corrected C −2c –V plots.

2 Experimental details

In order to fabricate the HfSiO4 thin film, silicon wafer which is 500 μm thick, p-type < 100 > Si substrate with a resistivity of 1–4 Ω was cleaned by the standard Radio Corporation of America (RCA) cleaning process firstly. In RCA cleanning process, silicon wafers were cleaned in 6:1:1 deionized (DI) water–H2O2–HNO3 for 5 min to get rid of organic residue and then to remove ionic residue silicon wafers were cleaned in a mix of 5:1:1 DI water–H2O2–HCL solution for 5 min. In order to eliminate naturel oxides in Si surface, the wafers were cleaned in 100:1 DI water–HF solution for 30 s and the cleaning wafers were dried by pure N2 gas lastly. Immediately after surface cleaning, a wafer was loaded in the chamber of the sputter system for HfSiO4 deposition onto Si layer. HfSiO4 target with dimensions of 4-inch and purity of 99.99 %, was used for the deposition of the oxide layers. The base pressure of the sputter chamber was adjusted below 4.0 × 10−4 Pa. Then, Ar flow rate was adjusted to be 16 sccm and sputtering pressure was adjusted to be at 1.0 Pa, then the pre-sputtering were performed for 3 h in order to get rid of any impurities on the target surface at 300 W and commercial sputtering was performed following the pre-sputtering in same parameters for 30 min. After deposition of HfSiO4, the HfSiO4/p-Si films were annealed at 750 °C for 40 min in the Nitrogen ambient and the thickness of the film was measured by spectroscopic reflectometer found as 300 nm. After annealing of the films, high-purity aluminum (Al) metal (99.999 %) was deposited by sputtering onto the whole back surface of the wafer and then Schottky contact was also formed by sputtering of Al dots with diameter of about 1.5 mm. The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements for fabricated Al/HfSiO4/p-Si (MOS) capacitor were performed at different frequencies of 50, 100, 250, 500 750 kHz and 1 MHz at room temperature using an Impedance Analyzer (MODEL HIOKI 3532-50 LCR meter) to study electrical characteristics of fabricated MOS capacitors.

3 Results and discussion

The capacitance voltage (C–V) and conductance voltage (G/ω–V) measurements were performed for each frequency between 50 kHz and 1 MHz at room temperature to study electrical instability and possible usage of HfSiO4 in MOS based technology. The measured C–V characteristics curves of Al/HfSiO4/p-Si (MOS) capacitors at different frequencies are shown in Fig. 1. Each C–V curves shows three regimes of accumulation–depletion–inversion region. It is observed that each C–V curves is a function of frequency and bias voltage. Especially, the flat band voltages (Vfb) are sensitive to the applied voltage frequency and it shifted to higher values than ideal one (−0.55 V) constantly by decreasing the frequency. This behaviour can be attributed to the frequency dependent interface states and border traps localized close to the interface between HfSiO4/Si that exchange mobile carriers with Si [13]. The contribution of these two trap state effects on flat band contribution will be discussed in details further. In addition, as seen in Fig. 1, the capacitance decreases with increasing frequency. This behaviour may be caused by time depended surface states and interface state. The variation in measured capacitance could be explained by the equivalent capacitance circuit [14, 15] observed in Fig. 2.

Fig. 1
figure 1

C–V characteristics of Al/HfSiO4/p-Si (MOS) capacitor in various frequencies range from 50 kHz to 1 MHz

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Fig. 2
figure 2

Equivalent circuit diagram under a low and b high frequency regions of MOS capacitors

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At the lower frequencies (<500 kHz) the effective capacitance CLF is expressed as

$$\frac{1}{{C_{\text{LF}} }} = \frac{1}{{C_{\text{ox}} }} + \frac{1}{{C_{\text{sc}} + (C_{\text{it}} /(1 + \omega^{2} \tau^{2} ))}}$$
(1)

where Cox, Csc, are the oxide capacitance, space charge capacitance, respectively, while Cit is capacitance associated with the interface traps, ω (ω = 2πf) is angular frequency. Interface trap lifetime (τ), which is on the order of 10−6–10−7 s in the literature, is defined as product of Cit and Rit where Rit is resistance associated with the interface traps. The ωτ is very small at lower frequency, i.e., (ωτ)2 can be ignored in the Eq. 1 [16, 17]. This means that if interface trapped charges and defects are easily follow the applied voltage, it leads to yield an excess capacitance at lower frequencies. On the other hand, interface states do not contributed to the total capacitance at the high frequencies (500 kHz>) [15, 18] since interface states are not fast enough to rearrange in response to the applied voltage excitation provided that ωτ > 1. The effective capacitance represented by CHF is expressed by the following expression.

$$\frac{1}{{C_{\text{HF}} }} = \left( {\frac{1}{{C_{\text{ox}} }} + \frac{1}{{C_{\text{sc}} }}} \right)$$
(2)

Considering the interface states contribution to the MOS capacitor characteristic, the C–V curves at all frequencies show three separated regimes, which are called inversion, depletion and accumulation as ideal MOS capacitors. In addition to these, C–V curves do not show kinks measured capacitance at all frequencies. The meaning of this is to highlight that there is a low defect and a good interface between HfSiO4 and p-Si [17, 19, 20]. Moreover, it can be seen in Fig. 1 that each C–V curves shifted to right side with increasing voltage frequency. The variation in C–V curves may be caused by the frequency dependent surface state. The interface states and series resistance are examples of the frequency dependent surface states.

The conductance is a significant parameter to investigate interface quality of the fabricated MOS capacitor [21]. When a small AC signal is applied to MOS capacitor, the conductance caused by interaction between interface states and majority carrier densities in the silicon losses [17]. Hence, it is direct measure of interface states and mobile carriers of Si. Interface traps somewhere near the band edge may be easily intercept and release carriers under different gate voltage influencing the charge and field distribution caused by different curves ideal behaviour of MOS capacitor. Frequency dependent measured conductance is shown in Fig. 3. The measured conductance curves increase with increasing applied voltage frequencies, except at 50 kHz. In addition, measured G/ω–V curves peaks move toward higher voltages with decreasing frequency. This behaviour may be related to relaxation time of trap states, series resistance and interfacial dielectric layer [21].

Fig. 3
figure 3

Conductance curves for Al/HfSiO4/p-Si (MOS) capacitors for diffrent frequencies

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The series resistance corrections were performed to MOS capacitor characteristics in order to eliminate possible noise effects on the MOS capacitor characteristics. The measured admittance Yma at strong accumulation of the MOS structure using the parallel RC circuit, is equal to the total circuit admittance [22, 23].

$$Y_{\text{ma}} = G_{\text{ma}} + j\omega C_{\text{ma}}$$
(3)

where ω is angular frequency, Cma is measured capacitance and Gma measured conductance in strong accumulation region. Comparing the real and imaginary part of the impedance, the series resistance is given by the following equation [24].

$$R_{s} = \frac{{G_{\text{ma}} }}{{(G_{\text{ma}} )^{2} + (\omega C_{\text{ma}} )^{2} }}$$
(4)

The Rs values of the Al/HfSiO4/p-Si (MOS) capacitor were calculated and are tabulated in Table 1. It is observed that the series resistance values decrease with increasing applied frequency. These behaviours may be explained by re-contraction and re-ordering of defect sites under frequency dispersion [14, 20, 25]. In order to remove series resistance effect from the G–V, G/ω–V curves, the correction of capacitance and conductance characteristic can be calculated by the following equations;

$$C_{C} = \frac{{\left[ {(G_{m} )^{2} + (\omega C_{m} )^{2} } \right]C_{m} }}{{a^{2} + (\omega C_{m} )^{2} }}$$
(5)

and

$$G_{C} = \frac{{\left[ {(G_{m} )^{2} + (\omega C_{m} )^{2} } \right]a}}{{a^{2} + (\omega C_{m} )^{2} }}$$
(6)

where ω is angular frequency, Cm is measured capacitance and Gm measured conductance measured voltage range, a = (G m ) − [(G m )2 + (ωC m )2]R s . The comparison of the measured and corrected MOS capacitor characteristics, corrected capacitance and conductance curves are shown in Fig. 4a–d. As seen in Figs. 4a, c, the series resistance deviates from the MOS capacitor characteristics, especially, for high frequency measurements. On the other hand, the corrected capacitance did significantly not deviated from the originals. The corrected conductance deviated from originals ones. The measured conductance curves almost increase with increasing frequency while they decrease constantly after correction was performed. This behaviour is expected as indicated in the literature [20, 26, 27]. The observed results indicate that series resistance is an important parameter that is the masking real MOS capacitor characteristics and elimination should be performed before detailed electrical analysis.

Table 1 Various calculated frequency-dependent electrical parameters for Al/HfSiO4/p-Si (MOS) capacitors
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Fig. 4
figure 4

Variations on the a corrected and measured capacitance for 50 kHz and 1 MHz frequencies, b corrected capacitance for various frequencies between 50 kHz and 1 MHz, c corrected and measured conductance for 50 kHz and 1 MHz, d corrected conductance for various frequencies between 50 kHz and 1 MHz

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Density state of interface state (Dit), which is the most important parameter affecting C–V characteristics, can be found using following equation [28].

$$D_{\text{it}} = \frac{2}{Aq}\frac{{{{G_{c,\hbox{max} } } \mathord{\left/ {\vphantom {{G_{c,\hbox{max} } } \omega }} \right. \kern-0pt} \omega }}}{{(G_{c,\hbox{max} } /\omega C_{\text{ox}} )^{2} + (1 - C_{c} /C_{\text{ox}} )^{2} }}$$
(7)

where q is elementary charge, A is front area of MOS capacitor, Cox (Aε0εi/d) is the oxide capacitance whose value is 1.04 × 10−9 F, ε0 (=8.85 × 10−14 F/cm) is the permittivity of free space [29], Gc,max/ω is peak value of corrected Gc,max/ω–V curve, Cc is corrected capacitance of the MOS corresponding to Gc,max/ω. Some required values and calculated density of state values are given in Table 1. Frequency dependent interface state density under frequency dispersion is also depicted in Fig. 5. The Dit values decrease with increasing applied voltage frequency as expected [30, 31] and the order of Dit approximately was calculated as 1010 eV−1 cm−2. The calculated values are in the same order as other promising dielectrics reported in [20, 32–34].

Fig. 5
figure 5

Variations of Dit as a function voltage for Al/HfSiO4/p-Si (MOS) capacitor

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Since the Dit values are in the expected order, the abnormal changes of the Vfb under frequency dispersions probably were caused by border states. In order to calculate border state density, the capacitance hysteresis were measured and then corrected. The corrected capacitance hysteresis curve is shown in Fig. 6 for 1 MHz and 50 kHz. Using the hysteresis curve obtained from flat band voltage shift (ΔVfb), the border state density (Nbt) in oxide layers were calculated by Eq. 8, assuming the total contribution interface states are almost zero for flat band shift in hysteresis [35, 36], and border state densitises Nbt, is given by

$$N_{\text{bt}} = \frac{{(C_{\text{acc}} \times \Delta V_{\text{FB}} )}}{qA}$$
(8)

where Cacc is accumulation capacitance. The calculated Nbt are given in Table 1. The usual Nbt values are in the order of 1010 eV−1 cm−2 for real MOS capacitor. However, calculated Nbt is in the order of 1011 eV−1 cm−2 for fabricated Al/HfSiO4/p-Si (MOS) capacitor. Hence, the abnormal frequency variations on the flat band voltages of the MOS capacitors can be attributed to the frequency dependent border states. In addition, the observed hysteresis is in the counter clockwise direction which clearly reveals a larger reduction of the acceptor-like border traps. Thus, the donor-like border traps play the dominant role [37, 38].

Fig. 6
figure 6

Hysteresis C–V characteristics for 1 MHz and 50 kHz

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The intercept of \({\text{C}}_{\text{c}}^{ - 2 }\) versus \({\text{V}}\) is plotted in Fig. 7. It has been observed that linearity of the obtained \({\text{C}}_{\text{c}}^{ - 2 } - {\text{V}}\) curves indicates the uniform distribution of interface states in the MOS capacitor structure. The relation between \({\text{C}}_{\text{c}}^{ - 2 }\) and \({\text{V}}\) can be expressed as in the following equation [39, 40].

$$C_{c}^{ - 2} = \frac{{2(V_{0} + V)}}{{\varepsilon_{s} \varepsilon_{0} qA^{2} N_{d} }}$$
(9)

where \({\text{V}}_{0}^{ }\) is the applied voltage and \({\text{V}}_{0}^{ }\) (=VD − kT/q) is the intercept of the \({\text{C}}_{\text{c}}^{ - 2 }\) versus \({\text{V}}\) plot with the voltage axis at various frequencies from 50 kHz to 1 MHz, ɛ s is relative permittivity of Si, ɛ 0 is the permittivity of free space and \({\text{N}}_{a}^{ }\) is the doping concentration obtained from the slope of \({\text{C}}_{\text{c}}^{ - 2 }\) versus \({\text{V}}\) characteristics. The values of barrier potentials (ΦB) can be obtained by means of the following equation [41].

$$\varphi_{B} = C_{2} V_{0} + \frac{kT}{q} + E_{F} - \Delta \varphi_{B}$$
(10)

where Ef (kT/q) ln(Nv/Na) is the energy difference between the bulk Fermi level and valance band edge, Nv is the effective density of state in valance band, C2 is the rate of Na (experimental)/Na (Theoretical) [42]. Theoretical value of Na is 1.67 × 1016 cm−3. Barrier potential, Δϕ B , can be calculated from the following equation.

$$\Delta \varphi_{B} = \sqrt {\frac{{qE_{m} }}{{4\pi \varepsilon_{s} \varepsilon_{0} }}}$$
(11)

where \({\text{E}}_{\text{m}}^{ }\) is the maximum electric field. These calculated electrical characteristic are tabulated in Table 2. Diffusion potentials are located at the positive voltage since the negative charges are trapped in the MOS capacitor by virtue of the fabrication process. Moreover, doping concentration increase with the increasing applied voltage frequency because of decline in the slope of \({\text{C}}_{\text{c}}^{ - 2 }\) versus \({\text{V}}\) plot. As data in Table 2 show, the Ef is almost constant as excepted under frequency dispersion. Moreover, variations on \({\text{V}}_{\text{D}}^{ }\) and Δϕ B were also observed under applied voltage frequency dispersion. This may be related to existence of the interfacial layer HfSiO4, especially, time dependent interface state at the HfSiO4/Si interface. On the other hand, the ΦB values varied from 0.615 to 0.559 eV depending on the charge accumulations due to time dependent trap sites.

Fig. 7
figure 7

C −2c –V characteristics and corresponding linear fit function of Al/HfSiO4/p-Si (MOS) capacitor at various frequencies from 50 kHz to 1 MHz

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Table 2 Barrier potentials and related electrical parameters under frequency dispersion of Al/HfSiO4/p-Si (MOS) capacitors
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4 Conclusion

In summary, the detailed electrical characteristics of Al/HfSiO4/p-Si MOS capacitor have been investigated for different voltage frequency at the room temperature. According to the results of the study, the capacitance and conductance are sensitive to applied voltage frequency due to frequency dependent charges, e.g., interface states, border traps, and series resistance. Seri resistance decreases with increasing applied voltage frequency and the seri resistance corrections must have been performed before detailed electrical analysis to obtain accurate results. The calculated Dit values were found to be in the order of 1010 eV−1 cm−2, which is in good agreement with other reported dielectric layer for MOS based technology. In addition, high sensitivity of the Vfb voltage variations was attributed to the interface states, especially, time dependent border states. On the other hand, it is observed that barrier potential values are also sensitive to the applied voltage frequencies. However, its values are expectable for elimination of leak charge injection from the substrate into the dielectric and thus the tunnelling effect does not significantly occur. In conclusion, fabricated HfSiO4 dielectric layer exhibits demanding electrical characteristics to be used in MOS-based technologies.