A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

Abstract

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.

1 Introduction

The process variations have always been one of the key issues in the robustness of CMOS integrated circuits especially in the mixed signal and RF circuits. For example, the variations of CMOS capacitances can be as large as 20 %. In the applications which heavily depend on capacitances accuracy, such as LC tank based voltage-controlled oscillator, the errors may introduce variations of operating frequency larger than 10 %, which is almost the tuning range of the oscillator in practice. Similar scenarios exist in the analogue-to-digital converters with high resolution, where well-matched capacitances are highly desired. Processing monitoring and calibration is hence of great interest to both microelectronics manufacturing and circuit designing [1–4]. The ring oscillator is a popular solution to track process variations, e.g., capacitance, in terms of frequency changes [4]. However, itself is very sensitive to many other variations, such as device sizes, supply voltage and temperature, etc.

It is not easy to extract the exact capacitance variations using a single kind of topology. To solve this issue, a new simple capacitance-to-frequency converter is proposed in this letter. It is able to transform the variations of capacitances in term of frequency changes with a considerably high accuracy, while maintaining a small silicon area and high flexibility in CMOS technology.

2 Design Considerations

The measurement of capacitance is an essential task in process characterisation. The CBCM technique has been a promising solution to measure on-chip capacitance for its high accuracy up to fF level. Figure 1 shows the topology of CBCM technique. Two non-overlap signals, V_p and V_n are applied to two inverters with and without load capacitors.

Fig. 1

The topology of CBCM

By comparing the current difference between the two inverters (with or without capacitor under measure), the load capacitance can be determined as:

$$ {\mathrm{C}}_{DUT}=\frac{{\mathrm{I}}_2-{\mathrm{I}}_1}{{\mathrm{V}}_{dd}{f}_{clk}} $$

(1)

where f _clk is the frequency of the square wave V_p and V_n.

However, this technique requires current meter in the measurement. Hence it is not suitable for on-chip calibration. Actually, the requirement for the on-chip capacitance variations measurement is quite different from conventional capacitance measurement. In such applications, no external current meter is available. However, only the variation of capacitance is required. For example, the percentage of variations over a reference capacitor is enough for the calibration of circuit performance. The simplest way to achieve this functionality is to use a ring oscillator to track the process variations. However, the oscillating frequency is highly dependent on other parameters, such as supply voltage, process corners of the transistors. Also, the operating frequency of the oscillator is never linear to the load capacitances due to non-linear effects of the circuits. These make the solution less attractive in the application of on-chip capacitance calibration.

It is observed that if the current difference in Eq. (1) can be replaced with some parameter that is easier to handle on-chip, such as frequency or period, the calibration of variations is possible. By combining the two above-mentioned solutions, a simple way for the capacitance variation monitoring can be performed in the following steps. By using the CBCM technique, the capacitance is calculated from the difference between the current of the two inverters. Then the current difference can be transformed into charge difference in reference capacitances, which subsequently results in the periodic difference in charging and discharging. Eventually, the capacitance is represented by differences in frequencies.

3 Proposed Design

A circuit can then be designed based on this idea. Figure 2 shows the topology of the proposed capacitor-to-frequency converter. In the capacitance measurement or calibration, each converter is loaded with different capacitances, and the differences in capacitance can be represented with different output period at V_out.

Fig. 2

The topology of the proposed capacitor-to-frequency converter

Compared with CBCM circuit in Fig. 1, by adding a tail MOS transistor MN₃, the current of the inverter is transformed into voltage. Then switches MP₃ and MN₄ are added to control the charge over capacitor C_charge. A comparator is used to compare the voltage at this capacitor with a threshold voltage V_ref. The operation of the circuit is described as follows. Initially, V_ctrl is low, the capacitor is being charged until the voltage of the capacitor, V_c increase to V_ref. The output of the comparator, V_out will consequently be logical high when V_c reaches V_ref. V_out is delayed as V_ctrl to control the switches which constitutes a feedback loop. In the delay time, V_ctrl keeps low and the capacitor keeps charging. When V_ctrl becomes high, the capacitor will be discharged immediately. Then the output of the comparator V_out and the output of the delay circuit V_ctrl will be low again, the circuit will come to the next period. Finally, the capacitor C_charge is charged and discharged to perform a periodical operation. Hence, the charging time, T is transformed to frequency, f _out. The current of the charging branch can be determined as:

$$ {\mathrm{I}}_{\mathrm{c}}=\frac{{\mathrm{V}}_{ref}}{\mathrm{T}}{\mathrm{C}}_{\mathrm{c}\mathrm{harge}} $$

(2)

This relationship can be used to calculate or calibrate the capacitances. For example, two capacitors C₁ and C₂ are measured using two capacitance-to-frequency converters in Fig. 2. According to Eq. (2), we can get:

$$ \varDelta {\mathrm{I}}_{\mathrm{c}}=\frac{{\mathrm{V}}_{ref}}{{\mathrm{T}}_1}{\mathrm{C}}_{\mathrm{c}\mathrm{harge}}-\frac{{\mathrm{V}}_{ref}}{{\mathrm{T}}_2}{\mathrm{C}}_{\mathrm{c}\mathrm{harge}} $$

(3)

And the current difference ΔI is linear to ΔI_c:

$$ \varDelta \mathrm{I}=\upalpha \varDelta {\mathrm{I}}_{\mathrm{c}} $$

(4)

Here, the coefficient α represents a linear relationship between ΔI and ΔI_c. It is a constant when the circuit parameters are all determined. Therefore

$$ {\mathrm{C}}_2-{\mathrm{C}}_1=\frac{\varDelta \mathrm{I}}{{\mathrm{V}}_{dd}{f}_{clk}}=\frac{\upalpha \varDelta {\mathrm{I}}_{\mathrm{c}}}{{\mathrm{V}}_{dd}{f}_{clk}} $$

(5)

So by comparing the difference in period for the charging and discharging time among C₁ and C₂, the capacitance difference is now the time (or frequency) difference. The coefficient α in Eq. (4) varies with f _clk, C_charge, V_ref and device sizes of MP₂, MN₂, MN₃. It can be optimized to achieve high accuracy at desired range of measurement. Firstly, f _clk and component MP₂, MN₂, MN₃ determine the current consumption of the inverter. If the current consumption is too small, the V_c could not reach V_ref, leading to the failure of the circuit. However, large current consumption leads to poor linearity. Secondly, V_ref and C_charge should be properly sized according to the range of capacitance under measure. Finally, the delay time is determined based on the discharged time of C_charge. It is important to make sure C_charge can be discharged to zero within the delay time.

4 Simulation Results

In the applications of mixed-signal and RF CMOS IC design, the typical capacitance is fF to pF. Hence the circuit in this work is optimized at such ranges. The circuit is implemented using a standard CMOS process. Only standard CMOS devices such as MOS transistors and capacitance are used in the circuit. It is optimized to measure fF to pF capacitance. For example, when V_dd = 1.8 V, f _clk = 10 MHz, C₁ = 302.5fF, C₂ = 1058.5fF, V_ref = 0.7 V, the delay time is 2us, the simulated V_out of the circuits with the two load capacitors are shown in Fig. 3. In this scenario, the circuit except the capacitance is less than 50 μm × 50 μm and consumes less than 60 μW.

Fig. 3

The simulated V_out of the circuit

In Fig. 3, V_out1 and V_out2 exhibit obvious differences in phase and frequency. Based on this difference, the calibration can be performed on-chip using digital technique. Also, if the capacitance is measured, the proposed circuit can be used to calculate the capacitance like a conventional CBCM technique. In CBCM technique, the capacitance is calculated using current difference, while the frequency difference is used in the proposed circuit. According to the frequency of V_out1 and V_out2, f _out1 and f _out2, we can get different charging time T₁ and T₂. Using Eq. (3), the current difference ΔI_c can be calculated. Here we can get the linear relationship of ΔI_c and ΔI:

$$ \upalpha \approx 3.31 $$

(6)

We can compare with the conventional CBCM technique, here the measurement error of this circuit is 0.53 %. According to the range of capacitance under measure, we can modify f _clk, C_charge, V_ref and device sizes of MP₂, MN₂, MN₃ to obtain good linearity.

Several design considerations can be concluded as follows. The frequency of the clock signal and C_charge should be determined based on the considerations of operating speed and linearity of measurement results and the suitable range of the capacitance of C_DUT. As mentioned above, the increase of f _clk results in the increase of charging current I and consequently the decrease of the charging period of C_charge, which is preferred to the circuit speed. However, with high input frequency, f _clk and large capacitance, the measurement results of C_DUT exhibits a poor linearity. Therefore, f _clk and C_charge should be determined according to the range of capacitance under measure. For example, when the capacitance is around 10fF, we can increase f _clk to 100 MHz, which can be decreased to 5 MHz if the capacitance under measure is around 1 pF. The minimum reference frequency can be as low as 1 MHz if a lower speed operation is acceptable. Besides, the capacitance of C_charge can be set to 20 pF to keep a proper charging time difference. As for the design of comparator, the voltage reference and voltage offset should be considered based on the requirement of accuracy. In this design, V_ref is set to be 0.7 V considering the charging time of C_charge as well as the topology of the comparator. Since the accuracy of C_DUT is directly limited by the offsets of the comparator. In this work, simulations are carried out to ensure the robustness of this design. For example, we can manually add 5 mV offset voltage in the comparator, which is a typical value of offset in this kind of topology. The accuracy degrades by 0.7 %, which is quite acceptable in the proposed system. However, if the offset is increased to 15 mV, the accuracy can be degraded by more than 3 %, which is not acceptable. This ensures the proper operation of proposed system. As long as desired measurement range is determined, the circuit can be further optimized for smaller silicon area and higher accuracy. Post-layout simulations with process corners are performed to verify the functionality of the proposed circuit at a wide working range. The percentage of error in the circuits is summarized in Fig. 4. It is observed that the proposed circuit is able to provide a high accuracy (less than 2 % error) from fF to pF ranges.

Fig. 4

Delayed frequency difference (unified) and percentage error

Besides, according Eqs. (1)(3)(4), we can get:

$$ \frac{1}{{\mathrm{T}}_1}-\frac{1}{{\mathrm{T}}_2}\propto {\mathrm{C}}_{DUT} $$

(7)

where T₁ and T₂ can be directly calculated from f _out1 and f _out2. Define the time reciprocal difference as delayed frequency difference (DFD). The linear relationship between this delayed frequency difference and capacitance under measure is also shown in Fig. 4. It is observed that the unified DFD exhibit a linear relationship with the capacitance under measure from fF to pF ranges. It suggests that the measurement or calibration can be performed on-chip precisely.

5 Conclusion

A capacitance-to-frequency converter is proposed. It can be used to measure the on-chip capacitance up to 1fF accuracy in term of output frequency measurement. More importantly, it is able to perform on-chip digital calibration regarding capacitance variations. The circuit is designed and simulated using a standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm and the building blocks of the circuits are standard CMOS circuits which can be easily configured for use at different operating frequencies, capacitance under measurement, and accuracy as well as for different CMOS technology nodes.