Study of the electrical parameters of a dual-material double-gate TFET using a strained type II staggered Ge_1−x−ySi_xSn_y/Ge_1−a−bSi_aSn_b heterojunction

Abstract

A strained Ge_1−x−ySi_xSn_y/Ge_1−a−bSi_aSn_b direct type II staggered heterojunction n-channel tunneling field-effect transistor (FET) with a dual-material double gate is proposed herein. A high-K gate dielectric is used to improve the overall device performance. The energy bandgap for strained Ge_1−x−ySi_xSn_y grown on a relaxed Ge_1−a−bSi_aSn_b layer is determined using the generalized approach of Menendez and Kouvetakis (MK). Poisson’s equation is solved by using a parabolic approximation to determine the surface potential and electric field. The drain current is calculated using the tunneling generation rate obtained from Kane’s model. A significant improvement of the drain current is observed as compared with that of previously reported Si-based TFETs.

1 Introduction

Aggressive downscaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) to achieve higher packing densities and increased values of the ON-current I_ON leads to severe degradation of the device performance due to short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL), leakage current, etc. [1]. The subthreshold swing of such devices is also restricted to 60 mV/decade at room temperature [2], which results in power dissipation problems when used in nanoscale circuits. To overcome such limitations, alternative devices with a reduced subthreshold swing must be explored to achieve higher ON-currents and reduced leakage currents for use in low-power applications [3,4,5].

The TFET uses band-to-band tunneling for carrier transport across the junctions instead of the conventional drift–diffusion current mechanism in MOSFETs. This makes it suitable for use in low-power applications. The TFET device has a built-in tunnel barrier that prevents SCEs and helps to achieve subthreshold swing values below the 60 mv/decade threshold [5,6,7]. Also, there is scope to improve the overall device characteristics of TFETs by simultaneously optimizing the I_ON, I_OFF, V_T, subthreshold slope, nature of the output characteristic, and immunity against SCEs, especially DIBL effects [8].

However, TFETs also suffer from certain drawbacks such as low I_ON as compared with conventional MOSFETs and ambipolar issues when used in switching applications. Also, device reliability can be a major concern, as TFET devices suffer from degradation of the device performance in terms of the drain current and threshold voltage due to the presence of interface traps and oxide charges at the gate dielectric–channel interface near the source–channel region [9]. The performance of TFETs can be improved by improving their I_ON and overcoming the ambipolar issues, which can be achieved by structural or material engineering of the device architecture. Recently, several structural modifications have been observed to address the shortcomings of the conventional TFET. A gate–source overlap with the addition of an Esaki tunneling diode in the source region of a TFET device is seen to improve the I_ON/I_OFF ratio and reduce the ambipolarity and leakage current [10]. The performance of conventional TFETs is seen to be greatly improved by modifying the channel shape (e.g., by using a T-shaped channel) and the positioning of the drain [11]. The scaling limitations of TFET devices (due to the emergence of SCEs) can be overcome by introducing a ground plane into the buried oxide of silicon-on-insulator (SOI) TFETs [12]. The addition of a source pocket at the source–channel interface greatly improves the ON current [13]. The use of heterojunctions in junctionless TFETs can improve the overall device performance and allow their use in digital applications [14]. The strained double-gate TFET (DGTFET) using dual-material and high-K dielectric has also shown encouraging results [15,16,17]. The use of a narrower-bandgap material also greatly improves the I_ON [19].

Dramatic improvements have been achieved in this field over the last 10–15 years, including the successful growth of GeSn [20] and the discovery of practical chemical vapor deposition (CVD) routes to high-quality Ge_1−xSn_x films and alloys of GeSiSn directly on Si substrates [21,22,23,24,25].

An interesting feature of this alloy is the crossover observed from an indirect to direct bandgap when the Sn concentration in the alloy exceeds 8% [26,27,28]. A material with a direct nature can also be obtained by applying strain. All the layers and virtual substrates (VS) can be grown on a Si substrate, highlighting the possibility of integrating the electronics and photonics onto a Si platform. It has also been proved that a type II direct bandgap configuration can be realized by using a strained GeSiSn layer with Sn content below 25% [29]. This type II direct bandgap can lead to significant band-to-band tunneling (BTBT) even at low voltages. Also, heterojunctions with such type II staggered band alignment have been shown to boost the performance [30, 31] of TFETs based on GeSiSn alloy.

Material engineering using new and novel materials must be combined with structural engineering to obtain devices with optimum performance. A heterojunction n-channel TFET built with a direct bandgap type II staggered strained Ge_1−x−ySi_xSn_y/Ge_1−abSi_aSn_b junction is proposed herein. The Ge_1−x−ySi_xSn_y layer is strained, whereas the Ge_1−a−bSi_aSn_b layer is relaxed. The method used to calculate the energy bands is a generalization of Van de Walle’s approach along with the inclusion of the strain-dependent spin–orbit Hamiltonian [25]. An analytical model for the above-mentioned device is derived by solving the two-dimensional (2-D) Poisson equation using the parabolic approximation technique. The surface potential and electric field are thus obtained using appropriate boundary conditions. The drain current is also obtained using the generation rate derived from Kane’s band-to-band tunneling generation rate model [32,33,34].

2 Theory

2.1 Device structure

A schematic of the structure of the proposed device is shown in Fig. 1. The p-type source and n-type drain are considered to have doping concentrations of 10²⁰/cm³ and 5 × 10¹⁸/cm³, respectively. The use of a lower doping concentration on the drain side ensures a lower OFF-current, while the higher source doping provides a higher ON-current due to the increased bandgap narrowing at the tunneling junction [18]. On the other hand, the channel doping concentration is chosen as 10¹⁷/cm³ to enhance the carrier mobility. Being an n-channel device, tunneling occurs at the source side of the source–channel interface. A high-K gate dielectric HfO₂ (K = 25) is used to reduce the gate leakage. Two gate metals M1 and M2 have different work functions of 4 eV and 4.4 eV, respectively. Initially there is no band overlap on the source side, but with an increase of the gate voltage, carriers tunnel from the valence band of the heavily doped p-type source to the conduction band of the nearly intrinsic channel and then move towards the n-doped drain by the drift–diffusion mechanism.

Fig. 1

A schematic diagram of the n-channel strained Ge_1−x−ySi_xSn_y/Ge_1−a−bSi_aSn_b DG-TFET

2.2 Bandgap calculation

The energy band structure at the Γ and L points of the conduction band in the Ge_1−x−ySi_xSn_y layer grown on Ge_1−a−bSi_aSn_b is calculated using a generalization of the Menendez and Kouvetakis (MK) [25] approach. It is assumed that there is a reference level within each semiconductor and that this level lines up when a heterostructure is formed. This alignment process of the reference levels gives the offset ΔE_V,av for the average of the three top valence bands in the actual materials. In the strain-dependent spin–orbit Hamiltonian introduced by Chandrasekhar and Pollak [37], the Menendez and Kouvetakis (MK) [25] and Van de Walle [38] approaches are also included. The expressions for the band edges of a (001)-oriented Ge_1−x−ySi_xSn_y layer lattice-matched to a relaxed Ge_1−a−bSi_aSn_b layer are given by

$$E_{{\mathrm{V}\Gamma }} \left( {x,y} \right) \, = - \frac{{\Delta_{0} \left( {a,b} \right)}}{3} - E_{{{\text{V,av}}}} \left( {a,b} \right) - \frac{{\Delta_{0} \left( {x,y} \right)}}{6} + \partial E_{h}^{o} + \frac{1}{4}\partial E_{001} + \frac{1}{2}\sqrt {(\Delta_{0} \left( {x,y} \right) + \frac{1}{2}\partial E_{001} )^{2} - 2\left( {\partial E_{001}^{\prime } } \right)^{2} },$$

(1a)

$$E_{\mathrm{C}}\Gamma \left( {x,y} \right) \, = E_{\mathrm{V}}\Gamma \left( {x,y} \right) + E_{0} \left( {x,y} \right) + \partial E_{\rm h}^{\mathrm{C}}\Gamma,$$

(1b)

$$E_{\mathrm{CL}} \left( {x,y} \right) = E_{{\mathrm{V}\Gamma }} \left( {x,y} \right) + E_{\text{ind}} \left( {x,y} \right) + \partial E_{\rm h}^{\rm CL}$$

(1c)

where Δ₀ is the spin–orbit splitting. Here, E_VΓ(x,y) is the highest valence band in the strained Ge_1−x−ySi_xSn_y layer, and E_CΓ(x,y) and E_CL(x,y) are the conduction-band edge at the Γ and L point, respectively.

The shear components of the strain have a significant effect on the degenerate bands; they lead to splitting of the valence bands. The splitting of the energy subbands averages out to obtain E_V,av. Even when no shear strain is present, valence-band splitting occurs due to the spin–orbit effect and the topmost valence band is given by $E_{V} = E_{{{\text{V,av}}}} + \frac{{\Delta_{0} }}{3}.$.

When strained layers are grown on a substrate, the shear components of the strain lead to additional splitting of the bands, which interacts further with the spin–orbit splitting to produce the final valence-band position. This effect is reflected in the difference of the spin–orbit splitting of the layer $\frac{{\Delta_{0} \left( {x,y} \right)}}{3}$ and the substrate $\frac{{\Delta_{0} \left( {a,b} \right)}}{3}$ [29].

E₀(x,y) is the direct bandgap of Ge_1−x−ySi_xSn_yat the Γ point and E_ind(x,y) is the indirect Γ–L bandgap, given as

$$E^{n} \left( {x,y} \right) = E_{\text{Ge}}^{n} \left( {1 - x - y} \right) + xE_{\text{Si}}^{n} + yE_{\text{Sn}}^{n} - b_{\text{GeSi}} x\left( {1 - x - y} \right) - b_{\text{GeSn}} y\left( {1 - x - y} \right) - b_{\text{SiSn}} xy.$$

(2)

The indirect bandgap energy is calculated according to Vegard’s law by using the values of the bowing parameters presented in Table 1. The strain shifts $\partial E_{001} ,\partial E_{001}^{\prime } ,\partial E_{\rm h}^{\rm V} ,\partial E_{\rm c}^{C\varGamma } \;{\text{and}}\;\partial E_{\rm C}^{\rm CL}$ are calculated from Menendez and Kouvetakis (MK) [25] and Chuang et al. [35]. The lattice constants of the ternary alloys are calculated using the following equation:

Table 1 The parameter values for Si, Ge, and Sn

$$a\left( {x,y} \right) = a_{\text{Ge}} \left( {1 - x - y} \right) + \left( x \right)a_{\text{Si}} + \left( y \right)a_{\text{Sn}} + b_{\text{GeSn}}^{\prime } \left( y \right)\left( {1 - x - y} \right) + b_{\text{SiGe}}^{\prime } \left( x \right)\left( {1 - x - y} \right) - b_{\text{SiSn}}^{\prime } \left( y \right)\left( x \right)$$

(3)

The lattice constant is used to calculate the strain as $e_{\parallel } = \frac{{\left[ {a\left( {a,b} \right) - a\left( {x,y} \right)} \right]}}{{a\left( {x,y} \right)}}$ [25].

The lattice constants of Ge, Si, and Sn, the lattice bowing parameters, and the deformation potentials used to calculate the strain and strain shifts are presented in Table 1.

Using Eqs. (1)–(3), the various concentrations of Ge, Si, and Sn in the ternary alloy giving type II, direct, and staggered band alignment are obtained and presented in Table 2. We choose the composition which gives rise to type II band alignment [29]. This improves the band-to-band tunneling rate in the proposed device, as the tunneling barrier width is reduced, thereby improving the ON current as seen below. The mole fractions providing the optimum device performance are selected to obtain the desired results.

Table 2 The values of x, y, a, and b to achieve a direct bandgap type II Ge_1−x−ySi_xSn_y/Ge_1−a−bSi_aSn_b heterojunction

2.3 Calculation of the drain current

For the calculation of the drain current, the following assumptions are made:

• The surface potential at the source end is equal to the difference between the Fermi level of the p-type source and the intrinsic Fermi level.

• The potential drop in the depletion region of the source is negligible, and the potential in the source region is uniform.

• The source–channel and drain–channel depletion regions are free from mobile charge.

• Trap charges are taken as zero.

The analytical model for the proposed device structure is derived by solving the 2-D Poisson’s equation

$$\frac{{\delta^{2}\Psi \left( {x,y} \right)}}{{\partial x^{2} }} + \frac{{\delta^{2}\Psi \left( {x,y} \right)}}{{\partial y^{2} }} = 0.$$

(4)

The potential profile in the vertical direction is assumed to be a second-order polynomial [36]

$$\Psi \left( {x,y} \right) = a_{O} \left( x \right) + ya_{1} \left( x \right) + y^{2} a_{2} \left( x \right).$$

(5)

The boundary conditions in the channel region are:

• (a) The electric flux at the front-oxide gate interface is continuous for the dual-material gate TFET, so

$$\frac{{{\text{d}}\Psi _{1} \left( {x,y} \right)}}{{{\text{d}}y}} = \varepsilon_{\text{ox}} \frac{{\Psi _{S1} \left( x \right) - \varphi_{g 1} }}{{\varepsilon_{\text{Si}} t_{\text{ox}} }}\;{\text{under}}\;{\text{M1}}\;{\text{at}}\,y = 0,$$

$$\frac{{{\text{d}}\Psi _{2} \left( {x,y} \right)}}{{{\text{d}}y}} = \varepsilon_{\text{ox}} \frac{{\Psi _{S2} \left( x \right) - \varphi_{g2} }}{{\varepsilon_{\text{Si}} t_{\text{ox}} }} \;{\text{under}}\;{\text{M2}}\;{\text{at}}\,y = 0,$$

where $\varphi_{\rm g1} = V_{\rm gs} - \phi_{\rm M1} + \chi + {\raise0.7ex\hbox{${E_{\rm g} }$} \!\mathord{\left/ {\vphantom {{E_{\rm g} } 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}},$

$$\varphi_{\rm g2} = V_{\rm gs} - \phi_{\rm M2} + \chi + {\raise0.7ex\hbox{${E_{\rm g} }$} \!\mathord{\left/ {\vphantom {{E_{\rm g} } 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}}.$$

• (b) The electric flux at the back gate oxide and the back channel interface is continuous for both materials:

$$\frac{{{\text{d}}\Psi _{1} \left( {x,y} \right)}}{{{\text{d}}y}} = \varepsilon_{\text{ox}} \frac{{\varphi_{g1} -\Psi _{S1} \left( x \right)}}{{\varepsilon_{\text{Si}} t_{\text{ox}} }}{\text{under}}\;{\text{M1}}\;{\text{at}}\,y = t_{\text{Si}},$$

$$\frac{{{\text{d}}\Psi _{2} \left( {x,y} \right)}}{{{\text{d}}y}} = \varepsilon_{\text{ox}} \frac{{\varphi_{g2} -\Psi _{S2} \left( x \right)}}{{\varepsilon_{\text{Si}} t_{\text{ox}} }}\;{\text{under}}\;{\text{M2}}\;{\text{at}}\,y = t_{\text{Si}}.$$

• (c) The potential at the source and drain end is given as

$$\Psi _{1} \left( {x,y} \right) =\Psi _{\rm S1} \left( 0 \right) = V_{{{\text{bi}} }} = \frac{ - KT}{q}\ln \frac{{N_{\text{Source}} }}{{N_{\rm i} }},$$

$$\Psi _{2} \left( {l_{1} + l_{2} ,0} \right) =\Psi _{\rm S2} \left( {l_{1} + l_{2} } \right) = V_{{{\text{bi}}1}} + V_{\text{DS}},$$

$$V_{{{\text{bi}}1}} = \frac{ - KT}{q}\ln \frac{{N_{\text{Drain}} }}{{N_{\rm i} }},$$

where V_bi is the built-in potential, ϕ_M1 and ϕ_M2 are the work functions of the gate metals, E_g is the bandgap energy, q is the elementary charge, V_GS is the gate–source voltage, V_DS is the drain–source voltage, ε_Si is the relative permittivity of GeSiSn, and ε_ox is the relative permittivity of HfO₂.

The 2-D potential under M1 and M2 can be obtained as

$$\Psi _{1} \left( {x,y} \right) =\Psi _{\rm S1} \left( x \right) + a_{11} \left( x \right)y + a_{12} \left( x \right)y^{2} \;0 \le x \le l_{1},$$

(6a)

$$\Psi _{2} \left( {x,y} \right) =\Psi _{\rm S2} \left( x \right) + a_{21} \left( x \right)y + a_{22} \left( x \right)y^{2} \;l_{1} \le x \le l_{1} + l_{2}.$$

(6b)

The values of the above constants are given as follows:

$$a_{11} \left( x \right) = \varepsilon_{\text{ox}} \frac{{\Psi _{\rm S1} \left( x \right) - \varphi_{\rm g1} }}{{\varepsilon_{\text{Si}} t_{\text{ox}} }},$$

(7a)

$$a_{12} \left( x \right) = \varepsilon_{\text{ox}} \frac{{\varphi_{\rm g1} -\Psi _{\rm S1} \left( x \right)}}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }},$$

(7b)

$$a_{21} \left( x \right) = \varepsilon_{\text{ox}} \frac{{\Psi _{\rm S2} \left( x \right) - \varphi_{\rm g2} }}{{\varepsilon_{\text{Si}} t_{\text{ox}} }},$$

(7c)

$$a_{22} \left( x \right) = \varepsilon_{\text{ox}} \frac{{\varphi_{\rm g2} -\Psi _{\rm S2} \left( x \right)}}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }}.$$

(7d)

Thus, we get

$$\Psi _{1} \left( {x,y} \right) =\Psi _{\rm S1} \left( x \right) + \varepsilon_{\text{ox}} \frac{{\Psi _{\rm S1} \left( x \right) - \varphi_{\rm g1} }}{{\varepsilon_{\text{Si}} t_{\text{ox}} }}y + \varepsilon_{\text{ox}} \frac{{\varphi_{\rm g1} -\Psi _{\rm S1} \left( x \right)}}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }}y^{2},$$

(8a)

$$\Psi _{2} \left( {x,y} \right) =\Psi _{\rm S2} \left( x \right) + \varepsilon_{\text{ox}} \frac{{\Psi _{\rm S2} \left( x \right) - \varphi_{\rm g2} }}{{\varepsilon_{\text{Si}} t_{\text{ox}} }}y + \varepsilon_{\text{ox}} \frac{{\varphi_{\rm g2} -\Psi _{\rm S2} \left( x \right)}}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }}y^{2}.$$

(8b)

Solving the Poisson’s equation, we obtain the surface potential under M1 and M2 as

$$\frac{{{\text{d}}^{2}\Psi _{\rm S1} \left( x \right)}}{{{\text{d}}x^{2} }} - \frac{{2\varepsilon_{\text{ox}} }}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }}\Psi _{\rm S1} \left( x \right) = \frac{{2\varepsilon_{\text{ox}} }}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }}\varphi_{\rm g1},$$

(9a)

$$\frac{{{\text{d}}^{2}\Psi _{\rm S2} \left( x \right)}}{{{\text{d}}x^{2} }} - \frac{{2\varepsilon_{\text{ox}} }}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }}\Psi _{\rm S2} \left( x \right) = \frac{{2\varepsilon_{\text{ox}} }}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }}\varphi_{\rm g2}.$$

(9b)

Solving the above second-order differential equation yields

$$\Psi _{\rm S1} \left( x \right) = B_{1} \mathrm{e}^{px} + C_{1} \mathrm{e}^{ - px} \varphi_{\rm g1 },$$

(10a)

$$\Psi _{\rm S2} \left( x \right) = B_{2} \mathrm{e}^{px} + C_{2} \mathrm{e}^{ - px} \varphi_{\rm g2},$$

(10b)

where $p^{2} = \frac{{2\varepsilon_{\text{ox}} }}{{t_{\text{Si}} \varepsilon_{\text{Si}} t_{\text{ox}} }},$

where χ is the electron affinity and p is the characteristic length.

The coefficients B₁, C₁, B₂, and C₂ are

$$B_{1} = \frac{{V_{\rm bi1} + V_{\rm DS} + \varphi_{\rm g2} - \left( {\varphi_{\rm g2} - \varphi_{\rm g1} } \right)\cos \left( {pl_{2} } \right) - \mathrm{e}^{{ - p\left( {l_{1} + l_{2} } \right)}} + (\varphi_{\rm g1} + V_{\rm bi} )}}{{\left( {2\sinh \left( {p\left( {l_{1} + l_{2} } \right)} \right)} \right)}},$$

(11a)

$${{C}}_{ 1} = V_{\text{bi}} + \varphi_{\rm g1} - B_{1},$$

(11b)

$${{B}}_{ 2} = B_{1} - \left( {\frac{{\varphi_{\rm g1} - \varphi_{\rm g2} }}{{2\mathrm{e}^{{pl_{1} }} }}} \right) ),$$

(11c)

$$C_{ 2} = C_{ 1} + \left( {\frac{{\varphi_{\rm g2} - \varphi_{\rm g1} }}{{2\mathrm{e}^{{ - pl_{1} }} }}} \right) ).$$

(11d)

Differentiating the surface potential along the channel length gives the electric field distribution.

The lateral electric field is

$$\Xi _{x1} \left( x \right) = - \frac{d}{{{\text{d}}x}}(\Psi _{\rm S1} \left( x \right)) = B_{1} p\mathrm{e}^{px} + C_{1} p\mathrm{e}^{ - px} \;{\text{where}}\; 0 \le x \le l_{1},$$

(12a)

$$\Xi _{x2} \left( x \right) = - \frac{d}{{{\text{d}}x}}\left( {\Psi _{\rm S2} \left( x \right)} \right) = B_{2} p\mathrm{e}^{px} + C_{2} p\mathrm{e}^{ - px} \;{\text{where}}\; l_{1} \le x \le l_{1} + l_{2}.$$

(12b)

The vertical electric field is

$$\Xi _{y1} \left( x \right) = \frac{d}{{{\text{d}}y}}\left( {\Psi _{1} \left( {x,y} \right)} \right) = - (a_{11} \left( x \right) + 2a_{12} \left( x \right)y)\;{\text{where}}\; 0 \le x \le l_{1},$$

(13a)

$$\Xi _{y2} \left( x \right) = \frac{d}{{{\text{d}}y}}\left( {\Psi _{2} \left( {x,y} \right)} \right) = - (a_{21} \left( x \right) + 2a_{22} \left( x \right)y)\;{\text{where}}\;l_{1} \le x \le l_{1} + l_{2}.$$

(13b)

The tunneling generation rate G($\Xi$) is calculated from Kane’s model [32, 33] as

$$G (\varXi )= A_{\text{Kane}} \left| \varXi \right|^{2} \mathrm{e}^{{\frac{{ - B_{\text{Kane}} }}{\left| \varXi \right|}}},$$

where $\left|\Xi \right| = \sqrt {\Xi _{x}^{2} + \varXi_{y}^{2} }$ is the magnitude of the electric field and A_Kane and B_Kane are Kane’s parameters.

The value of Kane’s parameters, which are dependent on the reduced tunneling mass and bandgap, are taken as

$$A_{\text{Kane}} = 2.3334 \times 10^{22} \;{\text{m}}^{ - 1} \;{\text{V}}^{ - 2} \;{\text{s}}^{ - 1},$$

$$B_{\text{Kane}} = \, 2.9541 \times 10^{2} \;{\text{MV/m}}.$$

In a DG-TFET, electrons undergo BTBT from the valence band of the source to the conduction band of the channel region. The total drain current I_D per unit length can be obtained by integrating the band-to-band generation rate over the volume of the device [34]:

$$I_{\rm D} = q{\iint }G\left(\Xi \right){\text{d}}x{\text{d}}y,$$

(14)

where q is the electronic charge.

3 Results and discussion

The proposed analytical model is implemented for a device with a channel length of 20 nm. The device has a body thickness of 10 nm and an equivalent oxide thickness (EOT) of ~ 1 nm.

Figure 2 shows the band alignment at the strained Ge_1−x−ySi_xSn_y/Ge_1−a−bSi_aSn_b interface.

Fig. 2

Band alignments at the strained Ge_(1−x−y)Si_xSn_y/Ge_(1−a−b)Si_aSn_b Interface

The analytical model derived herein is first applied to an Si-based DG-TFET, and the results are compared with data previously reported by Garg et al. [39] by using the same parameter values as those of the Si-based DG-TFET studied by Garg et al. [39]. Figure 3 illustrates the transfer characteristic of the Si-based TFET. Good agreement is seen between the results obtained using the theoretical model described herein and the simulation results of Garg et al. [39]. The model is thus validated and is now implemented on the proposed device structure.

Fig. 3

The transfer characteristics for the Si-based DG-TFET

Figure 4 illustrates the variation of the surface potential along the channel length at different gate voltages with a constant drain–source voltage. The surface potential varies significantly with the gate–source voltage. There is a reduction in the surface potential in the channel region with increasing gate voltage. For a higher gate–source voltage, the slope of the surface potential is sharper, indicating a greater tunneling current on the source side.

Fig. 4

The variation of the surface potential V_S for different V_GS values at V_DS = 0.1 V

Figure 5 illustrates the variation of the surface potential along the channel length for different drain voltages at a constant gate–source voltage. The surface potential at the source side remains unaffected by the drain voltage. Also, the slope of the potential profile is unaffected when increasing the drain bias. Therefore, the drain-induced barrier lowering (DIBL) effect will be significantly reduced and the tunneling current will remain shielded from the drain bias.

Fig. 5

The variation of the surface potential V_S for different V_DS values at V_GS = 0.1 V

The variation of the lateral electric field $\Xi$_x along the channel length at a constant drain voltage and constant gate voltage is shown in Fig. 6. The gradient of the field is high at the source and drain ends, but low in the middle of the channel. This gradient aids the diffusion of the carriers injected due to BTBT at the source junction to move to the drain end. The lateral electric field is crucial in calculating the tunneling generation rate.

Fig. 6

The variation of the lateral electric field Ξ_x along the channel length

Figure 7 plots the vertical electric field $\Xi$_y along the channel length at a constant drain voltage and constant gate voltage. The vertical electric field is maximum at the source end, which is the tunneling junction, but low at the drain end. Therefore, the chance of vertical tunneling from the gate is higher near the source than the drain. Therefore, bandgap or material engineering at the source side can reduce the leakage current. Also, the total electric field is maximum at the source–channel interface, i.e., the tunneling junction. This depicts the local band bending of the energy band leading to the BTBT.

Fig. 7

The variation of the vertical electric field Ξ_y along the channel length

Figure 8 illustrates the output characteristics of the device at constant gate–source voltage. The drain current I_D increases with the drain voltage, as desired.

Fig. 8

The log I_D versus V_DS characteristic curve of the proposed device

Figure 9 shows the transfer characteristics of the device at constant drain–source voltage for different bandgaps taken from Table 2. An ON-current I_ON of ~ 25 mA/µm is achieved with an OFF-current of ~ 10⁻¹⁰ A/µm for a bandgap E_g of 0.4648 eV. The EOT of the proposed device is taken as ~ 1 nm. The OFF-current of the device varies when changing the bandgap of the heterostructure, while the ON-current shows very little change. It can thus be concluded that the device performance is dependent on the mole fraction values in the alloy and the tunneling barrier width is indirectly a function of the mole fraction values of the alloy. The application of the gate voltage reduces the tunneling gap, and a very high local electric field is created, which leads to tunneling. As the gate bias is increased, the tunneling current flows from the source to drain end in the lateral direction. The sharp potential profile strongly influences the tunneling current near the source–channel interface.

Fig. 9

The I_D versus V_GS transfer characteristics of the proposed device

The variation of the transfer characteristics when changing the oxide thickness is illustrated in Fig. 10, which presents a comparative view of the I_D versus V_GS characteristics of an Si-based DG-TFET (EOT = 2 nm) and the proposed device for various values of t_ox. The ON-current increases with a decrease in the EOT. As t_ox decreases, the electric field increases, which in turn increases the tunneling probability. This increase in the band-to-band tunneling results in an increase of the ON-current of the device. It is observed that the proposed device offers a higher ON-current (~ 25 mA/µm) as compared with the Si-based DG-TFET (~ 2 µA/µm). The OFF-current of the proposed device is little affected when changing the EOT, showing a lower leakage current. A lower OFF-current is obtained for the Si-based DG-TFET. To overcome the disadvantage of the higher OFF-current, certain types of structural engineering can be incorporated, such as the addition of a drain pocket at the channel–drain interface. This not only reduces the OFF-current but also helps to eliminate the ambipolarity [39, 40]. The structure proposed herein overcomes the major disadvantage of the low ON-current of almost all types of TFET. The use of the SiGeSn heterostructure offers a great advance in this regard, and the proposed structure is clearly seen to provide a much higher ON-current than the Si-based DG-TFET when using comparable device parameters.

Fig. 10

The I_D versus V_GS characteristics for the proposed device at various t_ox values and for the Si-based DG-TFET

Figure 11 illustrates the variation of the I_ON/I_OFF ratio over a range of EOT values for the proposed device structure. A smaller EOT values gives a higher ON-current, leading to a better I_ON/I_OFF ratio and complements the device scaling. As the EOT of the device is increased, a degradation is seen in the I_ON/I_OFF ratio. The incorporation of a high-K dielectric (HfO₂) helps to obtain a lower EOT, thereby improving the overall performance of the device.

Fig. 11

The I_on to I_off ratio versus the EOT for the proposed device structure

Figure 12 shows the variation of the I_ON/I_OFF ratio when changing the channel length. At shorter channel lengths, the SCEs emerge, thereby reducing the I_ON/I_OFF ratio. Around a channel length of 20 nm, there is a large increase in the I_ON/I_OFF ratio, thus proving that this channel length can provide the optimum device characteristics while allowing device scaling. A I_ON/I_{OFF -}ratio on the order ~ 10⁷ is observed at the channel length of 20 nm.

Fig. 12

The I_ON/I_OFF ratio versus the channel length (i.e., the scaling of the device dimension) for the proposed device structure

Figure 13 depicts the SS_avg of the proposed device structure versus the channel length. As the device dimensions are increased, a lower SS_avg is obtained. For a shorter channel length, i.e., 10 nm, an SS_avg value of 90 mV/dec is obtained. Meanwhile, at a channel length of 20 nm, an SS_avg value of 36.5 mV/dec is obtained, being much lower than that obtained from conventional MOSFET and TFET devices.

Fig. 13

The variation of SS_avg versus the channel length (scaling trend)

Figure 14 illustrates the transfer characteristics of the proposed device at V_DS = 0.1 V and 1 V. The DIBL is calculated as the ratio of the difference of the gate voltages at which the drain current is equal to the DIBL current of 10⁻⁹A/μm at different V_DS values to the difference of the drain voltages [12]. The DIBL of the proposed device extracted from the graph is 44.4 mV/V, being much lower than for conventional TFETs (~ 121 mV/V) [12]. Thus, the DIBL is reduced by almost 63%.

Fig. 14

The transfer characteristics of the proposed device, indicating the DIBL effect

Figure 15 illustrates the gate-induced drain leakage (GIDL) current of the device [41,42,43] obtained for different V_GS values at fixed drain voltages. The GIDL current can be reduced by increasing the EOT and introducing structural engineering into the device, which eventually improves the overall device performance.

Fig. 15

The I_GIDL − V_GS transfer characteristics for different drain voltages

Table 3 presents a comparison of the various performance characteristics of the Si-based TFET and the proposed device structure. The advantages of the current structure are clearly observed in the context of the low I_ON/I_OFF ratio of the proposed device, and it can be concluded that the source of this problem is the higher I_OFF of the proposed device compared with the Si-based TFET. Further studies are necessary to address this problem, along with that of the ambipolarity. It can be conjectured that optimization of the device structure, and hence the nature of the strain in the material, could be employed for such work. Another important unresolved issue is related to the presence of interface trap states that may play a role, typically via the generation of hot electrons. However, at this point, there is little experimental data available on SiGeSn to reach any conclusion on this matter.

Table 3 A comparison of the proposed device structure with the Si-based TFET

4 Conclusions

A strained Ge_1−x−ySi_xSn_y/Ge_1−a−bSi_aSn_b direct type II staggered heterojunction n-channel tunneling FET with a dual-material double gate is designed and an analytical model proposed for the same. Analytical expressions for the electric field and surface potential are derived. Using the electric field components, the tunneling generation rate is calculated and thus the drain current is obtained using Kane’s model. The two major disadvantages of the TFET include a low ON-current and ambipolarity, restricting use in low-power applications. The device proposed herein improves the ON-current drastically. It is thus concluded that the proposed GeSiSn-based TFET achieves better ON-current I_D as compared with the Si-based DG-TFET.