Abstract
In this paper, a simulated Si0.6Ge0.4/Si hetero-structure double gate tunneling FET with drain dielectric pocket (DDP-SiGe-TFET) is reported for the first time. The high-k (HfO2) dielectric pocket is positioned in the vicinity of the HfO2/drain interface for improving the ambipolarity. The combination of low bandgap SiGe source and high bandgap Silicon channel improves the drain current performance without raising the OFF-state leakage current (IOFF). The different electrical characteristics such as drain current, average subthreshold swing, switching current ratio, tunneling distance, band-to-band (BTBT) rate, and electric field of the suggested device have been studied. The outcomes are further compared with the conventional Si-TFET and hetero-structure TFET to justify its supremacy. The influence of the variation in the DDP length (Lp), thickness (tp), and alloy fraction (x) of the Si1-xGex source upon device performance is examined. DDP-SiGe-TFET offers a much higher ION/IAmb ratio of 4.7 × 1010 with lower subthreshold swing (SS) of 24 mV/decade for an optimized Lp = 40 nm and tp = 8 nm. Further, the RF performance investigation of the device in terms of transconductance (gm), cut-off frequency (ft), and maximum oscillation frequency (fmax) has been carried out. The different device structures presented here have been simulated using the Silvaco TCAD simulation tool.
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Shwetapadma Panda has simulated the device and was a major contributor in writing the manuscript. Sidhartha Dash has theoretically developed the model and has contributed to the analysis of the results. Both the authors read and approved the final manuscript.
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Panda, S., Dash, S. Drain Dielectric Pocket Engineering: its Impact on the Electrical Performance of a Hetero-Structure Tunnel FET. Silicon 14, 9305–9317 (2022). https://doi.org/10.1007/s12633-022-01707-6
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DOI: https://doi.org/10.1007/s12633-022-01707-6