1 Introduction

Computation using artificial neural networks is nowadays experiencing a renaissance, as the rapid development of the Internet of Things and the availability of large computing power have made it possible to achieve great results in areas such as image, speech, and text recognition, the development of self-driving cars and drones [1,2,3,4,5], etc. However, with their increasing performance, the operation of such systems also requires growing amounts of additional power. Currently, specialized neuromorphic processors are being developed around the world to overcome this problem [6,7,8,9,10]. It is supposed that they will bring neural computation to a fundamentally new level of performance while reducing the associated energy consumption.

One of the promising hardware approaches in this field is the use of memristors. Their ability to change conductivity under certain external influences (resistive switching effect) has allowed researchers to consider memristors as a model for synapses in the brain [11,12,13]. On the basis of memristive structures, the implementation of mixed analog–digital hardware multilayer neural networks becomes possible [14,15,16].

The memristive structure with a crossbar topology is one of the most important parts of the widely investigated neurosynaptic core architecture, storing the weights of a configured neural network. However, this structure has a fundamental problem: when reading the conductivity, sneak paths arise around a target memristor, resulting in some additional current that makes the crossbar inoperable [17]. To suppress such sneak currents, a number of different solutions have been proposed based on the addition of some passive or active components to the crossbar, namely diodes set on unselected bit lines [17] or in a one-diode one-memristor (1D1M) crossbar architecture [18, 19], selectors in a one-selector one-memristor (1S1M) architecture [20, 21], or transistors in a 1T1M architecture [22,23,24,25]. Such diodes and selectors are passive elements which, due to their rectifying characteristics, limit the sneak paths. They can be formed using self-consistent technology in one process with the memristive layer. Nevertheless, they have notable drawbacks. Structures with the 1D1M architecture have problems with programming the bipolar memristors (due to the small currents in the reverse branch of the diode), while 1S1M structures show strong nonlinearity in the I–V curve at the reading voltages, which seriously complicates the operation of neuromorphic systems, where close-to-linear I–V relations are highly desirable. Also, the variation of the characteristics of even the most advanced memristive devices introduces noticeable distortion into the operation of neural network algorithms [26], which must be taken into account during their implementing [27]. The 1S1M architecture requires higher reading voltages, meaning that device variability can cause more severe disturbance of the memristance reading process [28], also leading to an increase in the power consumption.

The 1T1M crossbar architecture is based on active transistor elements and is immune to the drawbacks mentioned for the structures including diodes and selectors. However, it also suffers from some disadvantages, e.g., the necessity for additional technological operations to develop the transistor layer and combine it with the memristive devices, or potentially a lower on-chip density than in the case without transistors. However, the 1T1M topology has been thoroughly investigated, is technologically well developed based on one-transistor one-resistor (1T1R) random-access memory (RAM) technologies [29, 30], and is operationally very robust and adaptive due to the subtle control of the characteristics of the memristors.

Despite the intrinsic ability of a transistor to control the current through it, there is still a problem, as shown below, with the sneak currents in 1T1M crossbars with high dimensions. Moreover, other sources of imperfect operation are also possible. These are known as discharge and leakage currents, being due to the discharge of the gate capacitance of the field-effect transistor (FET) and the nonideal insulator properties of the gate dielectric, respectively.

This work is devoted to consideration of the contributions of these different parasitic currents to the deterioration of the performance of a 1T1M crossbar. This architecture is chosen as it is appropriate for neuromorphic computing; i.e., it sums the inputs in rows multiplied by memristive weights organized in columns for further signal transmission to neurons from I\(_{{\rm out}N}\) outputs (Fig. 1). The assessment is done both analytically and using model simulations based on two example prospective bipolar memristive structures: (i) a nanocomposite \((\mathrm{CoFeB})_x{(\mathrm{LiNbO}_3)_{100-x}}\) structure with metallic nanogranules of CoFeB in a nonstoichiometric oxide matrix, which demonstrates a highly multilevel resistive state storage ability (> 28 states), high endurance (\(>\,10^6\)), and good high-to-low resistance ratio \(R_{\mathrm{off}} / R_{\mathrm{on}}\,>\) 100 [31,32,33,34], and (ii) an yttria-stabilized zirconia-based structure, as its resistive switching process can be well controlled by adjusting the yttrium doping level and it is compatible with standard complementary metal–oxide–semiconductor (CMOS) technology [35, 36]. However, the presented approach is also applicable to other materials with appealing memristive characteristics, e.g., HfO\(_x\) [37], SiN\(_x\) [38], and others.

Fig. 1
figure 1

An \(N\times N\) crossbar, where \(V_{\mathrm{in}}\) and \(I_{\mathrm{out}}\) designate the input and output lines, and \(V_{\mathrm{c}}\) is the crossbar’s control line input

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2 Device models

(a) The memristor model To determine the applicability of resistive switching elements to neuromorphic systems on a chip, where a large-scale memristive crossbar architecture is required, various memristor models [39,40,41,42,43,44,45,46,47] with different levels of detail have been developed to date. However, as the dimensions of the simulated crossbar increase, the computing resource requirements increase dramatically. Thus, the memristor model used in this work should meet the following criteria:

  • Flexibility: the possibility of adjusting different intrinsic parameters (the threshold voltage, the resistances in the limit states, and others)

  • Computational economy: being quite easy to simulate

Based on these criteria, the VTEAM Verilog-A model [40] is chosen. Moreover, models of this kind have potential for further improvement [48].

The I–V curve of the memristor in the VTEAM model is shown in Fig. 2. Its only qualitative difference from the I–V characteristic of real memristors (Fig. 3) is that the memristor resistance of the model is constant between the values \(R_{\mathrm{off}}\) and \(R_{\mathrm{on}}\) over the entire interval from the SET to RESET voltage. However, this discrepancy only results in quantitative changes without affecting the result qualitatively.

Fig. 2
figure 2

The I–V curve of the VTEAM simulation using scaled \((\mathrm{CoFeB})_x (\mathrm{LiNbO}_3)_{100-x}\) memristor parameters

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Fig. 3
figure 3

The experimental I–V curve obtained for the \(\mathrm{(CoFeB)}_x (\mathrm{LiNbO}_3)_{100-x}\) memristor with dimensions of \(200\times 500\times 2\,\upmu \mathrm{m}^{3}\) and scaled down to \(1\times 1\times 2\,\upmu \mathrm{m}^{3}\)

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Note that the values of \(R_{\mathrm{off}}\) and \(R_{\mathrm{on}}\) are chosen in accordance with the physical area of the simulated memristor (Table 1). The dimensions selected for the yttria-stabilized zirconia-based structure correspond to the previously published results for the samples in Ref. [35]. At the same time, the size of the \(\mathrm{(CoFeB)}_x (\mathrm{LiNbO}_3)_{100-x}\) nanocomposite structure is a result of scaling the samples from Ref. [32], assuming a linear dependence of the conductivity on the size of the nanocomposite. The linearity of this dependence is an assumption, but does not affect in principle the conclusions of our study. The real effects of scaling nanocomposite memristors will be studied in future work.

Table 1 The characteristics of the considered memristor structures
Full size table

For such large resistances, the influence of the contact wires is minimal; For example, for copper with a resistivity of \(17.5\times 10^{-9}\,\Omega\)m, even a 1-cm-long wire with cross-sectional area of 1 \(\upmu \mathrm{m}^{2}\) has a resistance of 175 \(\Omega\). Meanwhile, the resistance of the transistor in its open state, \(R_{\mathrm{FET,on}}\), equals 25 k\(\Omega\), which is significantly larger and must be taken into account when designing the crossbar.

(b) The FET transistor In this work, an N-channel normally closed field-effect transistor model is used, as described in the BSIM-SOI international standard format [49], with gate dimensions of \(L = 0.35\,\upmu\)m and \(W = 1\,\upmu\)m. This FET is suitable for this study because its geometry and properties approximately correspond to those of the exploited memristors, e.g., in terms of operating currents and switching voltages. It is worth noting that, despite the large dimensions of the transistor, applicable results can be obtained for their use in neuromorphic computing [50].

The simulation process is carried out using Cadence Spectre software.

3 The acceptable value of the weight range

Updating the range of synaptic weights affects the learning ability and inference accuracy of the emulated neural network [51]. Consider a memristor-based neural network that requires no fewer than \(S = 2^{{\lambda }}\) stable levels of memristor conductivity to achieve its admissible performance. Optimally, these can be organized in a uniform distribution of S states between the minimal and maximal values of a synaptic weight range. Note that, for a feedforward neural network classifier, the admissible number \({\lambda }\) of weight precision bits is evaluated to be no fewer than 5 [51]. It can certainly be assumed that the smallest precision with which one can process memristive weights equals the minimum value of conductivity \(1/R_{\mathrm{off}}\). Indeed, at this end of the conductivity range, strong variations in the resistance values are generally observed during cyclic endurance testing [22,23,24,25, 29, 30, 34, 36], making it difficult to control the magnitude of the weights with accuracy greater than \(1/R_{\mathrm{off}}\).

This reasoning leads us to the following necessary condition for acceptable performance of a memristor-based neural network:

$$\begin{aligned} R_{\mathrm{off}}/R_{\mathrm{on}} \ge S. \end{aligned}$$
(1)

Even if one could perfectly control a single memristor state by precisely setting S levels in its conductivity range, the problems arising in a 1T1M memristive crossbar under the influence of parasitic currents will severely deteriorate the accuracy of reading the weights and, consequently, of teaching the whole neural network. Thus, careful evaluation of the influence of parasitic currents on the performance of the crossbar is required.

4 Methods

The first goal of this study is to simulate a \(256\times 256\) 1T1M crossbar and determine the dimensions of the crosspoint memristive structure for which the distortions introduced by sneak currents are minimum. Then, a \(512\times 512\) crossbar is simulated to determine the sneak currents for the memristor with the identified optimal dimensions.

The simulations are implemented in a worst-case mode, where the target memristor is located at the most distant position on the crossbar relative to its inputs and outputs (at the upper-right corner) and set in its high-resistance state, while all other resistive switching elements of the crossbar are in the low-resistance state. Under these conditions, the sneak currents influencing the target memristor will be the largest [52]. Regarding Fig. 1, the target memristor is the element located at the intersection of the lines \(V_{\mathrm{in1}}\) and \(I_{\mathrm{out}N}\) (the current is measured at the output).

According to the estimates above, the resistance of the contact wires is many times lower than that of the transistors or memristive structures, so it is ignored in this study.

The crossbar modeling consists of two consecutive steps (noting that all the unused inputs and outputs of the circuit are floated by default during the modeling):

  1. 1.

    Since all the memristors are initially in the low-resistance state, it is necessary to switch the target memristor with matrix index (1, 256) to the high-resistance state. This is achieved by applying a voltage pulse with an amplitude of −3 V to the input \(V_{\mathrm{in1}}\), while connecting the memristor’s output to ground. While changing the conductivity of the memristor, the values \(V_{{\mathrm{c}},1{-}255} = -3.3\) V and \(V_{{\mathrm{c}},256} = 3.3\) V are applied to the control lines of the transistors, to close and open the corresponding bit lines, respectively.

  2. 2.

    The conductivity of the memristor is read by the application of a reading pulse with an amplitude of 1 V to the input V\(_{\mathrm{in1}}\), while the output current I\(_{{\mathrm{out}},256}\) is analyzed. To close or open the corresponding bit lines, the transistor control voltages \(V_{{\mathrm{c}},1-255}\) = 0 V and \(V_{{\mathrm{c}},256}\) = 3.3 V are applied, as opposed to the first step. The zero voltage on the control lines for closing the transistors is caused by changing the conductivity of some of the nontarget memristors in the first row of the crossbar under the influence of a total bias of 4.3 V (the sum of the reading and control voltage amplitudes) applied to the series-connected transistor–memristor pairs.

5 The sneak current issue

The simulations of the \(256 \times 256\) 1T1M crossbar show that it is possible to create crossbars on the basis of both analyzed memristive structures with dimensions greater than \(256 \times 256\) (Tables 2, 3).

Table 2 The sneak currents for the (CoFeB)\(_x\)(LiNbO\(_3\))\(_{100-x}\)-based memristive crossbar
Full size table
Table 3 The sneak currents for the Au/Zr/ZrO\(_2\)(Y)/TiN/Ti-based memristive crossbar
Full size table

This conclusion is due to the following values of the sneak currents obtained during the study of the \(256 \times 256\) crossbar:

  • For the (CoFeB)\(_x\)(LiNbO\(_3\))\(_{100-x}\) nanocomposite, the maximum sneak current value is less than 51% of the reading current through the memristive structure;

  • For the yttria-stabilized zirconia-based structure, the sneak currents do not exceed 0.6% of the operating current in the OFF-state of the target memristor.

The sneak currents in the worst-case mode can be easily evaluated analytically by applying Kirchhoff’s laws to the circuit shown in Fig. 1, leading to the following formulae (for \(N \gg 1\)):

$$\begin{aligned} I_{\mathrm{sneak}}\approx \frac{V_{\mathrm{r}}}{R_{\mathrm{FET,off}}}N, \end{aligned}$$
(2)
$$\begin{aligned} R_{\mathrm{off}}^*\approx \frac{R_{\mathrm{off}}R_{\mathrm{FET,off}} / N}{R_{\mathrm{off}} + R_{\mathrm{FET,off}} / N}, \end{aligned}$$
(3)

where \(V_{\mathrm{r}}\) is a reading voltage, \(R_{\mathrm{off}}\) is the real resistance of a memristor in its fully nonconductive state, \(R_{\mathrm{off}}^*\) is the measured resistance of the upper corner memristor according to the reading current at its output, and \(R_{\mathrm{FET,off}}\) is the resistance of the transistor in its closed state (with 0 V applied to the gate).

The approximate Eq. (2) reveals that the sneak currents do not depend on the characteristics of the memristor at all, because the transistor resistance in the OFF state is much greater than that of the memristor in any resistive state, not to mention the series resistance related to the CMOS metal lines and electrodes, which are a thousand times smaller. Using the BSIM-SOI transistor model, \(R_{\mathrm{FET,off}}\) with 0 V at its gate is evaluated as 350 G\(\Omega\). Using this value, the magnitude of the sneak current for the \(256 \times 256 (N = 256)\) crossbar is obtained as approximately 732 pA, which is quite close to the numerical results presented in Tables 2 and 3. The difference may be related to the accuracy of the simulation and taking into account the line resistance of the CMOS metal lines and electrodes in the simulation. At the same time, increasing the line resistance to the level of 3 k\(\Omega\), as in Ref. [53], leads to a change in the final result of less than 3%.

For the example using the \((\mathrm{CoFeB})_x(\mathrm{LiNbO}_3)_{100-x}\) nanocomposite with dimensions of \(1\times 1\times 4\,\upmu \mathrm{m}^{3}\), the results of the simulation of the \(512\times 512\) crossbar are presented in Table 2. In this case, the sneak current equals 1328 pA, which is approximately twice the value for the crossbar with \(N = 256\) and corresponds to Eq. (2). Guided by Eq. (1) described in Sect. 2, this crossbar cannot be considered to be fully operational, because the sneak currents distort the \(R_{\mathrm{off}}/R_{\mathrm{on}}\) ratio, resulting in a conventional boundary value less than 32 corresponding to 5 bits of weight precision (\(R_{\mathrm{off}}^* / R_{\mathrm{on}} = 30.4\)).

It is possible to estimate the largest size of a 1T1M crossbar that will still be insignificantly influenced by the sneak currents in the operational sense of condition (11). Substituting \(R_{\mathrm{off}}\) for \(R_{\mathrm{off}}^*\) in Eq. (1) and using Eq. (3) for \(R_{\mathrm{off}}^*\), the maximum allowable size of a 1T1M crossbar can be deduced to be

$$\begin{aligned} N_{\mathrm{max}}^{({\mathrm{sneak}})} \approx \frac{R_{\mathrm{FET,off}}}{R_{\mathrm{off}}} \left( \frac{1}{S}\frac{R_{\mathrm{off}}}{R_{\mathrm{on}}} - 1\right) . \end{aligned}$$
(4)

Equation (4) determines the crossbar size when \(R_{\mathrm{off}}^* / R_{\mathrm{on}}\) becomes equal to S, representing the limit of allowable operational functionality due to the parasitic effect of sneak currents in the worst-case mode.

For example, considering the characteristics of the \((\mathrm{CoFeB})_x(\mathrm{LiNbO}_3)_{100-x}\) nanocomposite memristor with dimensions of \(1\times 1\times 2\,\upmu \mathrm{m}^{3}\), the largest crossbar achieving a satisfactory range of resistive ratio values (\(S = 32, R_{\mathrm{off}}/ R_{\mathrm{on}} = 66\)) is approximately \(465\times 465\). These results are in good agreement with the numerical estimate presented above.

6 The discharge current issue

The application of the crossbar architecture shown in Fig. 1 via the sequence of steps described in Sect. 4 imposes certain limits: during the switching of control lines, for an accurate current (or conductivity) measurement, it is necessary to discharge the transistors’ capacitances. If this is not done, the resulting discharge of the transistors’ gates during control voltage changes will result in strong distortion of the readings of the conductivity of the target memristor.

Figure 4 shows the RESET process of the upper corner memristor with subsequent reading using line \(I_{{\mathrm{out}},256}\) of the 1T1M \(256 \times 256\) (CoFeB)\(_x\)(LiNbO\(_3\))\(_{100-x}\) nanocomposite memristor crossbar. Note that the control lines of the nontarget bit lines (\(V_{{\mathrm{c}},1-255}\) in Fig. 4c) should be switched to the negative voltage to be closed during the application of the negative potential to the input word line 1 to reset the target upper-right corner memristor. In this process, relaxation current pulses with a time constant of approximately 15 \(\upmu \mathrm{s}\) are observed at the output (\(I_{{\mathrm{out}}256}\) in Fig. 4b). These are associated with the recharging of the transistor gate capacitances. If the reading process (the 1-V pulse in Fig. 4a, f) starts before the current relaxation ends, the result will be significantly different from the expected one, as shown in Fig. 4d; indeed, the output current in this case can exceed the expected one by several orders of magnitude. The general scheme of the crossbar currents (for only one row) is shown in Fig. 4g.

Thus, the influence of this transient process depends on the time that has elapsed since the end of the resistive switching of a memristor. Several solutions can be proposed to fix this problem:

  • Waiting for the end of the transition process, which could require quite a lot of time

  • Using samples with a larger area, but this approach is undesirable because of problems with both scaling and higher power consumption of the crossbar

  • Using an additional simple discharge circuit

Fig. 4
figure 4

The process for reading the conductivity of the (CoFeB)\(_x\)(LiNbO\(_3\))\(_{100-x}\,1\times 1\times 2\,\upmu \mathrm{m}^{3}\) memristor and a map of the currents in the crossbar. a The input voltage (\(V_{in1}\)) trace: the pulse switching the memristor to the OFF state, followed by the reading pulse, b the dynamics of the output current (\(I_{{\mathrm{out}},256}\)), with an active discharge circuit (grey color) and without it (brown color), c the voltage applied to the control lines (\(V_{{\mathrm{c}},1-255}\)), d the reading current pulse (\(I_{{\mathrm{out}},256}\)) in the crossbar without a discharge circuit, e the reading current pulse (\(I_{{\mathrm{out}},256}\)) in the crossbar with an active discharge circuit, f the input voltage reading pulse [enlarged from (a)], g a map of the currents in the crossbar during the reading process, where the influence of the discharge currents (\(I_{{\mathrm{dsch}}}\)) can be attenuated by using a discharge circuit

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The last approach is to use a transimpedance amplifier, whose input is connected to the corresponding output column (Fig. 4g). It connects a column to a virtual ground without significantly reducing the input impedance of the circuit, which is of great importance for large crossbars.

The gray curve in Fig. 4b shows the result for the output current when using this discharge technique. In this case, substantially less time is needed for complete relaxation of the currents in the control lines before switching or reading the target memristor state, and the read result is almost undistorted (Fig. 4e), compared with in the absence of the discharge circuit.

Note that such use of a virtual ground is a well-known technique in electronic circuits with a crossbar architecture [54, 55]; the novelty of this work is the demonstration of the relationship between the different kinds of parasitic current effects and the estimation of the maximum allowable size of the 1T1M crossbar that can be built with and without such a discharge circuit in its design.

In this regard, it can be concluded that the effect of the sneak currents on the read result is not as destructive as that of the transient relaxation processes arising in the 1T1M crossbar. Moreover, the addition of the suggested simple discharge circuit at the outputs can solve this problem.

7 The leakage current issue

Besides the sneak and discharge currents, there is one more possible source of result distortion in the 1T1M crossbar architecture, namely the leakage current through the gate dielectric of the transistors in the control lines. This occurs even in the stationary, fully relaxed mode of the crossbar system and appears due to the nonideal properties of the gate dielectric (i.e., its noninfinite resistance).

A leakage current is generated only by those control lines that have a nonzero potential difference between the voltage on the gates of their transistors and the output of the crossbar. Accounting for the fact that, generally, the output is accepted to be grounded, this condition means that nonzero values of \(V_{\mathrm{c}}\) are applied to the control lines.

In the worst-case mode, the highest total leakage current is observed in the case of reading the conductivity of the memristive in the upper corner when all the other bit lines are closed by a negative or positive (depending on the type of transistor) voltage \(V_{\mathrm{c}}\) on the control lines. Then, these currents flow (up to the flow direction) from the gate to the source of each transistor and through one of the memristors in the rightmost column, opened by the corresponding control line, to the ground at the crossbar output.

The resistance of the gate dielectric layer is generally much greater than that of any transistor channel (source–drain) or memristor resistive state, even in their OFF state. Therefore, the total leakage current at the output for a large (\(N \gg 1\)) 1T1M crossbar can be estimated as

$$\begin{aligned} I_{\mathrm{leak}} \approx \frac{V_{\mathrm{c}}}{R_{\mathrm{gd}}}N^2, \end{aligned}$$
(5)

where \(R_{\mathrm{gd}}\) is the resistance of the transistor gate dielectric. As noted above, \(R_{\mathrm{gd}} \gg R_{\mathrm{FET,off}}\), so such an influence of the leakage currents on the read result is not observed in our numerical experiments. However, Eq. (5) displays a parabolic dependence on the crossbar size N, in contrast to the linear dependence in Eq. (2) for the sneak currents. Thus, for some large dimension of the crossbar, the leakage currents will become close in magnitude to the sneak currents. This will occur for a size

$$\begin{aligned} N_{\rm ls} \approx \frac{V_{\mathrm{r}}}{|V_{\mathrm{c}}|}\frac{R_{\mathrm{gd}}}{R_{\mathrm{FET,off}}}, \end{aligned}$$
(6)

where \(N_{\rm ls}\) is on the order of 10\(^6\). This is quite a large size, but degradation of the performance may occur for crossbars with rather smaller dimensions, due to the absolute values of the leakage currents, without regard to the sneak currents. If \(V_{\mathrm{c}}\) is a positive blocking voltage (for a p-type FET), then this deterioration effect will occur, again, when \(R_{\mathrm{off}}^*/R_{\mathrm{on}} \ge S\), where \(R_{\mathrm{off}}^*\) is the measured resistance of the target upper-corner memristor in the worst-case mode, distorted due to the leakage currents:

$$\begin{aligned} \frac{V_{\mathrm{c}}}{R_{\mathrm{gd}}}N^2 + \frac{V_{\mathrm{r}}}{R_{\mathrm{off}}} = \frac{V_{\mathrm{r}}}{R_{\mathrm{off}}^*}. \end{aligned}$$
(7)

Then,

$$\begin{aligned} N_{\mathrm{max}}^{({\mathrm{leak}})} \approx \sqrt{\frac{R_{\mathrm{gd}}}{R_{\mathrm{off}}}\frac{V_{\mathrm{r}}}{|V_{\mathrm{c}}|}\left( \frac{1}{S}\frac{R_{\mathrm{off}}}{R_{\mathrm{on}}} - 1\right) }, V_{\mathrm{c}} > 0. \end{aligned}$$
(8)

When \(V_{\mathrm{c}}\) is the negative blocking voltage (for an n-type FET, as in this work), an incorrect result will be obtained when the total current becomes negative when reading the target memristor conductivity, viz.

$$\begin{aligned} -\frac{|V_{\mathrm{c}}|}{R_{\mathrm{gd}}}N^2 + \frac{V_{\mathrm{r}}}{R_{\mathrm{off}}} < 0, \end{aligned}$$
(9)

and therefore

$$\begin{aligned} N_{\mathrm{max}}^{({\mathrm{leak}})} \approx \sqrt{\frac{R_{\mathrm{gd}}}{R_{\mathrm{off}}}\frac{V_{\mathrm{r}}}{|V_{\mathrm{c}}|}}, V_{\mathrm{c}} > 0. \end{aligned}$$
(10)

Considering that the factor (\(R_{\mathrm{off}} / (SR_{\mathrm{on}}) -1\)) is on the order of magnitude of 1 (for \(R_{\mathrm{off}} / R_{\mathrm{on}} \approx 100\)), Eq. (4) can be simplified and expressions (8) and (10) combined to obtain

$$\begin{aligned} N_{\mathrm{max}}^{({\mathrm{sneak}})}\sim \frac{R_{\mathrm{FET,off}}}{R_{\mathrm{off}}}, \end{aligned}$$
(11a)
$$\begin{aligned} N_{\mathrm{max}}^{({\mathrm{leak}})}\sim \sqrt{\frac{R_{\mathrm{gd}}}{R_{\mathrm{off}}}\frac{V_{\mathrm{r}}}{|V_{\mathrm{c}}|}}. \end{aligned}$$
(11b)

According to Eq. (11b), the biggest allowable size of such a crossbar containing nanocomposite memristors could be \(\sim\) 20,000 (for \(V_{\mathrm{r}} = 1\) V and \(V_{\mathrm{c}} = -3.3\) V), which is much smaller than the size of 10\(^6\) given by Eq. (6), from the point of view of the proximity of the leakage and sneak current values. On the other hand, the use of high-k dielectric transistors could improve this situation, as this would allow a decrease of the leakage current by several orders of magnitude, thus increasing the maximum size to 200,000 or even greater.

8 Discussion

Before designing a crossbar with the 1T1M architecture, it should be checked whether the desired crossbar size is less than the least of the values given by Eq. (11) [or, more precisely, by (4), (8), and (10)], according to the characteristics of the memristive devices and transistors used. Generally, the size defined by (11a) is much less than that given by (11b), so the sneak current is still the major problem, as for crossbars without transistors or selector devices.

Partial solutions of the sneak current problem, according to formula (4), may be: (i) increasing the ratio \(R_{\mathrm{off}} /R_{\mathrm{on}}\) of the memristive devices used, or (ii) using a control FET with a high resistance \(R_{\mathrm{FET,off}}\) in its closed state.

It is important to note that the derived formulae are valid when \(R_{\mathrm{on}} \gg R_{\mathrm{FET,on}} + r\) (the latter being the series resistance related to the CMOS metal lines and electrodes). Otherwise, the physical characteristics of the crossbar line resistance will affect the ratio calculated based on the output currents. Nevertheless, formulae (4) and (8) remain valid if \(R_{\mathrm{on}}\) is replaced by the sum (\(R_{\mathrm{on}} + R_{\mathrm{FET,on}} + r\)). Also, it is necessary to apply linear corrections for the wire resistances when measuring conductivities in different columns of the crossbar.

To reduce the destructive effect of the leakage currents through the FET gates, one should use transistors whose gate dielectric exhibits good insulating properties. Also, it is possible, as in this work, to choose \(V_{\mathrm{c}}\) equal to 0 V during the reading process (only for normally closed transistors, i.e., with an induced channel), so that \(N_{\mathrm{max}}^{({\mathrm{leak}})}\) diverges to infinity, according to Eq. (11b).

The most destructive (in terms of their amplitude) are the transistor gate discharge currents in the control lines of a 1T1M crossbar. Their effect can be eliminated either by waiting until the end of the relaxation phenomena after switching the control lines, or by using a simple discharge circuit in the form of a transimpedance amplifier-based virtual ground.

Another issue that should be considered is the geometrical scaling of the crossbar. If the length and width of a transistor channel from the source to drain are designated as l and w, respectively, then

$$\begin{aligned} R_{\mathrm{FET,off}}\propto \frac{l}{w}, \end{aligned}$$
(12a)
$$\begin{aligned} R_{\mathrm{off}}\propto \frac{l}{wl}. \end{aligned}$$
(12b)

The last expression approximately applies because the memristive device is generally laid above the drain and corresponds to its size. It can be seen that \(R_{\mathrm{off}}\) depends quadratically on a linear scaling factor, whereas \(R_{\mathrm{FET,off}}\) almost does not depend on the scaling. Thus, the ratio \(R_{\mathrm{FET,off}} /R_{\mathrm{off}} \propto l^2\) decreases quadratically with downscaling of the size of the elements. This is a serious issue because of the reduction of the maximum allowable crossbar size due to the increase of the sneak currents according to Eq. (11a).

Another fundamental solution to the problem of sneak currents is to use a special scheme for reading the 1T1M crossbar, compatible with that suggested for eliminating the discharge currents. One can apply \(V_{\mathrm{r}}\) to a chosen word line and 0 V to a chosen bit line, which intersect at the target memristor, while connecting all other word and bit lines to the (virtual) ground (0 V). At the same time, only the target control line should be open, while all the others are closed (Fig. 5). This, in principle, should lead to the absence or a reduction by orders of magnitude of the sneak current values in the target bit line. A simple evaluation based on Kirchhoff’s equations shows that the sneak current in the worst case can be expressed as

$$\begin{aligned} I_{\mathrm{sneak}} \approx \frac{r^2}{R_{\mathrm{FET,off}}\left( R_{\mathrm{FET,on}} + R_{\mathrm{on}}\right) }\frac{V_{\mathrm{r}}}{R_{\mathrm{FET,off}}}N^2, \end{aligned}$$
(13)

where r is the resistance of one contact bus and the series electrodes. It is assumed that \(r<< R_{\mathrm{FET,off}} / N\). Repeating the considerations described above yields

$$\begin{aligned} N_{\mathrm{max}}^{({\mathrm{leak}})} \sim \sqrt{\frac{R_{\mathrm{FET,on}} + R_{\mathrm{on}}}{R_{\mathrm{off}}}}\frac{R_{\mathrm{FET,off}}}{r} \end{aligned}$$
(14)

[cf. formula (11a)]. Moreover, this approach simultaneously diminishes the problems with the discharge and leakage currents, as it allows them to drain into the (virtual) ground connected to the bit lines.

Fig. 5
figure 5

The proposed reading scheme where all the unselected bit and word lines are (virtually) grounded

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Note that, if such a scheme is not justified in practice due to the additional hardware cost of grounding the unused crossbar word lines, a simple scheme of virtually grounding only the nontarget columns can be chosen. In this case, the estimates for the amplitude of the sneak current and the allowable crossbar size are

$$\begin{aligned} I_{\mathrm{sneak}}\approx \frac{r}{R_{\mathrm{FET,off}}}\frac{V_{\mathrm{r}}}{R_{\mathrm{FET,off}}}N^2, \end{aligned}$$
(15)
$$\begin{aligned} N_{\mathrm{max}}^{({\mathrm{sneak}})}\sim \frac{R_{\mathrm{FET,off}}}{\sqrt{rR_{\mathrm{FET,off}}}}. \end{aligned}$$
(16)

This scheme yields a maximum 1T1M crossbar size that is \(\sqrt{(R_{\mathrm{on}} + R_{\mathrm{FET,on}}) / r}\) times smaller than that given by Eq. (14).

9 Conclusions

The results of this study reveal that, in a large memristive crossbar built with the 1T1M architecture, the sneak and discharge currents and even the leakage current through the transistor gate dielectric must be accounted for to enable correct estimation of the crosspoint memristor resistances. Simple evaluations based on Kirchhoff’s equations give the maximum size of a crossbar corresponding to the allowable quality of its operation in neuromorphic calculations. It is demonstrated that the stationary sneak and dynamical discharge currents have the most deteriorating effect on the performance of the crossbar.

Nevertheless, all these negative effects can be overcome by using a simple proposed scheme for switching and measurement, consisting of grounding all the nontarget word and bit lines. It is also worth noting that such virtual grounding should be realized by using transimpedance amplifiers, so as to not significantly reduce the input impedance of the circuit with increasing crossbar size.

This scheme of operation enables 1T1M crossbars with dimensions of up to \(N \sim \sqrt{(R_{\mathrm{on}} + R_{\mathrm{FET,on}}) / R_{\mathrm{off}}}R_{\mathrm{FET,off}}/r\), where \(R_{\mathrm{on}}\) and

\(R_{\mathrm{off}}\) are the resistances of the memristor in its low- and high-resistive states, \(R_{\mathrm{FET,off}}\) and \(R_{\mathrm{FET,on}}\) are the resistances of a control FET channel in its closed and open states, and r is the resistance of the bus electrode or some appropriate small compliance resistance connected to it in series. This upper value of N can reach as much as 10\(^8\) or even more, depending on the compliance resistance, memristors, and FETs chosen. At the same time, taking into account a plausible geometrical size of a 1T1M crossbar (up to \(\sim 10 \mathrm{cm}\)) and a scaling dependence of type (12b) for the resistances r, \(R_{\mathrm{off}}\), and \(R_{\mathrm{on}}\), the maximum allowable dimensions of a 1T1M crossbar can be estimated as \(N \sim 10^6\).

In this case, the reading or writing times and, consequently, the overall performance are limited mainly by the relaxation time constant rC, with C designating the transistor gate capacity. By choosing a sufficiently small r, it is possible to improve the crossbar performance within certain limits.

It is believed that the results of this study will support the development of high-speed and reliable analog and multistate neuromorphic systems based on large memristive crossbars for different prospective applications, from neuromorphic computation to brain–computer interfaces and neuroprostheses.