1 Introduction

Due to the nonscalability of the subthreshold swing (SS), increasing power density is a major challenge for continued MOSFET scaling. The SS of a MOSFET is limited to 60 mV/dec, resulting in increased leakage current in the subthreshold region. One of the promising device designs to replace MOSFETs is the TFET, which has shown potential to overcome the SS limit of MOSFETs [1–5]. Because of their low OFF currents (in the range of femtoamps), they are ideally suited for low-power and low-standby-power logic applications operating at moderate frequencies [6]. Other promising applications of TFETs include ultralow-power specialized analog integrated circuits with improved temperature stability [7, 8]. Although TFETs seem to be well adapted as candidates for ultimately scaled quasi-ideal switches, their unacceptably low ON current [lower than International Technology Roadmap for Semiconductors (ITRS) requirements] is the greatest challenge to their application. Besides, TFETs often exhibit delayed saturation in their output characteristic, which is detrimental for complementary metal–oxide–semiconductor (CMOS) applications. In addition, strong drain-induced barrier lowering (DIBL) effects are sometimes manifested in TFETs, which may severely limit the utility of such devices. Additive combination of many technology boosters has been proposed to increase the tunneling current and optimize device performance [9–16].

Some work has used bandgap engineering or heterostructuring of the channel (strained SiGe) [9, 10] or source material (low-bandgap Ge) [11]. Several studies have shown how gate work-function engineering [12] or use of high-k dielectric [13] can help to improve the coupling between the gate and tunnel junction to boost the ON current. In [14–16], the effect of device structure engineering on TFET performance was investigated. Multiple-gate structures have also been explored for improvement of TFET device performance. Saurabh and Kumar [17] proposed the application of a dual-material double-gate (DMDG) structure in TFET devices for optimization of ON current, threshold voltage, SS, and immunity to DIBL effects.

The most important electrical parameter for a solid-state switch is probably its threshold voltage. While a number of analytical models [18–21] have been proposed for the potential, electric field, and drain current of the DMDG structure, no threshold voltage models have been proposed to date. Since analytical models are useful to provide further insight into the working principles of a device, in this work, a threshold voltage model for a DMDG TFET is proposed. Model validation has been carried out by comparing model results with two-dimensional (2-D) device simulation results. The effects of device physical parameters such as the gate length, channel thickness, and gate dielectric, as well as the effect of the drain bias on the gate threshold voltage have been observed. The proposed model can be used as an efficient tool for design and fabrication of DMDG TFET devices.

Fig. 1
figure 1

Schematic of n-type DMDG TFET

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2 Device structure and parameters

A schematic diagram of the structure of an n-type DMDG TFET is shown in Fig. 1. A DMDG TFET is a gated p–i–n diode with gates made from two metals with different work functions. The metal gate near to the drain is called the auxiliary gate; its work-function variation mainly controls the OFF-state current. The metal gate near the source side is called the tunnel gate; it controls the tunneling in the source–body junction. When the tunneling gate has a lower work function than the auxiliary gate, higher \(I_\mathrm{ON}\), lower \(I_\mathrm{OFF}\), and better SS are achieved. Electrons tunnel from the valence band of the source to the conduction band of the intrinsic body and then move towards the drain end through a drift–diffusion mechanism. Tunneling occurs in the region of high electric field (source–body interface), where local band bending reduces the width of the energy barrier. Band bending is achieved by applying a reverse bias at the gate, which pushes the energy band downwards and turns on the device (Fig. 2).

Fig. 2
figure 2

Band diagrams for DMDG TFET in OFF state (dotted lines; \(V_\mathrm{DS}=0\,\mathrm{V},\;V_\mathrm{GS}=0\,\mathrm{V}\)) and ON state (solid lines; \(V_\mathrm{DS}=0.5\,\mathrm{V},\;V_\mathrm{GS}=1\,\mathrm{V}\))

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The values of the metal work functions used in this work are \({\varPhi }_\mathrm{tunnel}=4\,\mathrm{eV}\) (e.g., Ni–Ti, Mo) and \({\varPhi }_\mathrm{auxiliary}=4.4\,\mathrm{eV}\) (e.g., W, Ta). The source and drain are made of highly doped p-type and n-type regions with doping levels of \(N_\mathrm{source}=10^{20}\,\mathrm{cm}^{-3}\) and \(N_\mathrm{drain}=10^{19}\,\mathrm{cm}^{-3}\), respectively. The body region is lightly n-type doped with \(N_\mathrm{channel}=10^{17}\,\mathrm{cm}^{-3}\). Other device parameters are: channel length, \(L=100\,\mathrm{nm}\) where \(L_1=50\,\mathrm{nm}\), \(L_2=50\,\mathrm{nm}\); silicon film thickness, \(t_\mathrm{Si}=10\,\mathrm{nm}\); oxide thickness, \(t_\mathrm{ox}=2\,\mathrm{nm}\). The dielectrics used here are \(\mathrm{SiO}_2\) (\(\epsilon _\mathrm{ox}=3.9\)), \(\mathrm{Si}_3\mathrm{N}_4\) (\(\epsilon _\mathrm{ox}=7.5\)), \(\mathrm{HfO}_2\) (\(\epsilon _\mathrm{ox}=21\)), and \(\mathrm{La}_2\mathrm{O}_3\) (\(\epsilon _\mathrm{ox}=27\)). Electron affinity of \(\chi _\mathrm{Si}=4.17\,\mathrm{eV}\) and silicon bandgap of \(E_\mathrm{g}=1.1\,\mathrm{eV}\) are used.

3 Model for gate threshold voltage (\(V_\mathrm{TG}\)) of DMDG TFET

3.1 Tunnel FET \(V_\mathrm{TG}\)

DMDG TFETs have outstanding \(I_\mathrm{D}\)–\(V_\mathrm{GS}\) characteristics, which are controlled by the width of the energy barrier. Figure 3 depicts how the energy barrier narrowing is controlled by the applied gate voltage in DMDG TFETs. Here, values of barrier width have been extracted by taking the energy bands across the length of the TFET and then measuring the narrowest barrier width for these bands. This technique works well at applied voltages above several hundred mV, due to the exponential dependence of the tunneling probability on the barrier width. This can be realized from Fig. 4, which shows the dependence of the drain tunneling current on the barrier width.

Fig. 3
figure 3

Energy barrier width versus \(V_\mathrm{GS}\) for \(\epsilon _\mathrm{ox}=3.9\), 21 at \(V_\mathrm{DS}=1\,\mathrm{V}\)

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Fig. 4
figure 4

Drain current versus energy barrier width for \(\epsilon _\mathrm{ox}=3.9\), 21 at \(V_\mathrm{DS}=1\,\mathrm{V}\)

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For MOS transistors, the physical definition of the threshold voltage is the gate voltage at which the density of carriers in the inversion channel at the surface equals the doping level of the substrate. Since the current conduction mechanism is completely different in TFETs, many previous works [22, 23] used a constant-current method for extraction of the threshold voltage. In this method, the gate voltage at which the drain current equals \(10^{-7}\,\mathrm{A/}\upmu \mathrm{m}\) represents the threshold value. From Fig. 4, the constant-current method would suggest that the threshold voltage for the device in Fig. 1 corresponds to a barrier width of \(4.5\,\mathrm{nm}\), which is in the region of strong dependence of barrier width on gate bias. Since the constant-current method has no physical meaning, Boucart and Ionescu [24] proposed a new physical definition of the TFET threshold voltage (\(V_\mathrm{TG}\)) as the gate voltage for which the energy barrier narrowing starts to saturate with gate bias. Herein, this new definition is used to extract the DMDG TFET threshold voltage.

3.2 Model derivation

Assuming a Gaussian box in the lightly doped body region of the DMDG TFET structure of Fig. 1 and neglecting mobile-charge, source–drain depletion regions, the following equation can be derived [25]:

$$\begin{aligned}&\frac{\epsilon _\mathrm{Si} t_\mathrm{Si}}{\eta } \frac{\partial E_{\mathrm{sf}(i)}(y)}{\partial y}+\epsilon _\mathrm{ox} \frac{V'_{\mathrm{GS}(i)}-\psi _{\mathrm{sf}(i)}(y)}{t_\mathrm{ox}}\nonumber \\&\quad +\, \epsilon _\mathrm{ox} \frac{V'_{\mathrm{GS}(i)}-\psi _{\mathrm{sb}(i)}(y)}{t_\mathrm{ox}}=qN_\mathrm{channel}t_\mathrm{Si}, \end{aligned}$$
(1)

where \(i=1,2\) indicates regions under metal 1 and metal 2, respectively. \(E_{\mathrm{sf}(i)}(y)\) and \(\psi _{\mathrm{sf}(i)}(y)\) are the electric field and potential at the top oxide–semiconductor interface, respectively. \(\eta \) is the channel spreading parameter which accounts for the nonuniformity of the lateral field across the channel thickness. \(\eta \) is constant for a given technology, varying between 1 and 1.3 [25]. In this work, \(\eta \) is considered to be 1. \(V'_{\mathrm{GS}(i)}=V_{\mathrm{GS}(i)} -V_{\mathrm{FB}(i)}\), where the flatband voltage is \(V_{\mathrm{FB}(i)}=\phi _{\mathrm{m}(i)}-\phi _\mathrm{S}\). Here, \(\phi _{\mathrm{m}(i)}\) is the metal work function, and the semiconductor work function is \(\phi _\mathrm{S}=\chi _\mathrm{Si}+E_\mathrm{g}/2\).

In (1), the first term on the left-hand side represents the net lateral electric flux entering the Gaussian box, while the second and third term represent the fluxes entering from the top and bottom surface. The right-hand side is the total charge in the Gaussian box. Now, solving the one-dimensional (1-D) Poisson’s equation in the x-direction of Fig. 1, the bottom interface potential, \(\psi _\mathrm{sb}(y)\), can be found.

$$\begin{aligned} \psi _{\mathrm{sb}(i)}(y)=\psi _{\mathrm{sf}(i)}(y)-E_{\mathrm{sf}(i)}(y)t_\mathrm{Si}-\frac{qN_\mathrm{channel}t^2_\mathrm{Si}}{\epsilon _\mathrm{Si}}. \end{aligned}$$
(2)

We then apply the continuity condition for the electric displacement vector at the top oxide–semiconductor interface:

$$\begin{aligned} E_{\mathrm{sf}(i)}(y)=\epsilon _\mathrm{ox}\frac{V'_{\mathrm{GS}(i)}-\psi _{\mathrm{sf}(i)}(y)}{t_\mathrm{ox}\epsilon _\mathrm{Si}}. \end{aligned}$$
(3)

Substituting Eqs. (2) and (3) into (1) yields

$$\begin{aligned} \frac{\partial ^2\psi _{\mathrm{sf}(i)}(y)}{\partial y^2}-\lambda ^2\psi _{\mathrm{sf}(i)}(y) =\delta _{(i)}, \end{aligned}$$
(4)

where

$$\begin{aligned}&\lambda ^2=\eta \frac{C_\mathrm{ox}}{t^2_\mathrm{Si} C_\mathrm{Si}} \left( 2+\frac{C_\mathrm{ox}}{C_\mathrm{Si}}\right) ,\\&\delta _{(i)}=\eta \frac{qN_\mathrm{channel}}{2\epsilon _\mathrm{Si}}\left( 2+\frac{C_\mathrm{ox}}{C_\mathrm{Si}}\right) -\lambda ^2V'_{\mathrm{GS}(i)}. \end{aligned}$$

Here, the oxide capacitance is \(C_\mathrm{ox}=\epsilon _\mathrm{ox}/t_\mathrm{ox}\), and the silicon film capacitance is \(C_\mathrm{Si}=\epsilon _\mathrm{Si}/t_\mathrm{Si}\).

The solution of (4) for both channel regions under M1 and M2 is

$$\begin{aligned}&\psi _\mathrm{sf1}(y)=A\exp \left( \lambda y\right) + B\exp \left( -\lambda y\right) - \frac{\delta _1}{\lambda ^2} , \quad 0\le y \le L_1,\end{aligned}$$
(5)
$$\begin{aligned}&\psi _\mathrm{sf2}(y)=C\exp \left( \lambda y\right) + D\exp \left( -\lambda y\right) - \frac{\delta _2}{\lambda ^2} ,\quad L_1\le y \le L_2. \end{aligned}$$
(6)

Now, to find the values of A, B, C, and D, the following boundary conditions are applied at the source edge, drain edge of the channel, and the point where M1 and M2 contact each other:

$$\begin{aligned}&\psi _\mathrm{sf1}(0)=-\frac{kT}{q}\ln {\frac{N_\mathrm{source}}{N_\mathrm{channel}}}=-V_\mathrm{bi},\\&\psi _\mathrm{sf2}(L)=\frac{kT}{q}\ln {\frac{N_\mathrm{drain}}{N_\mathrm{channel}}}+V_\mathrm{DS}=V'_\mathrm{bi}+V_\mathrm{DS},\\&\psi _\mathrm{sf1}(L_1)=\psi _\mathrm{sf2}(L_1),\\&\frac{\partial \psi _\mathrm{sf1}(L_1)}{\partial y}=\frac{\partial \psi _\mathrm{sf2}(L_1)}{\partial y}. \end{aligned}$$

Using these boundary conditions, the constants in (5) and (6) are obtained as

$$\begin{aligned} A= & {} \frac{\gamma \exp \left( -\lambda L\right) +\theta }{2\sinh \left( \lambda L\right) }+\frac{{\Delta } V_\mathrm{FB}\exp \left( -\lambda L_1\right) }{2},\\ B= & {} \frac{-\gamma \exp \left( \lambda L\right) -\theta }{2\sinh \left( \lambda L\right) }+\frac{{\Delta } V_\mathrm{FB}\exp \left( \lambda L_1\right) }{2},\\ C= & {} \frac{\gamma \exp \left( -\lambda L\right) +\theta }{2\sinh \left( \lambda L\right) },\\ D= & {} \frac{-\gamma \exp \left( \lambda L\right) -\theta }{2\sinh \left( \lambda L\right) }, \end{aligned}$$

where \({\varDelta } V_\mathrm{FB}=V_\mathrm{FB1}-V_\mathrm{FB2}\), \(\sigma _1=\dfrac{\delta _1}{\lambda ^2}\), \(\sigma _2=\dfrac{\delta _2}{\lambda ^2}\), \(\theta =V'_\mathrm{bi}+V_\mathrm{DS}+\sigma _2\), and \(\gamma =V_\mathrm{bi}-\sigma _1+{\varDelta } V_\mathrm{FB} \cosh \left( \lambda L_1\right) \). At the gate threshold voltage, the tunneling barrier width (\(w_{\text {b}}\)) exhibits a transition from strong to weak dependence on the gate voltage. At this inflection point, \(y=w_{\text {b}}\) and \(\psi _\mathrm{sf1}(y)=V_\mathrm{DS}+\dfrac{kT}{q}\ln \dfrac{N_\mathrm{drain}}{N_\mathrm{channel}}\) [26].

Substituting these values into (5), the threshold voltage of the DMDG TFET can be modeled as

$$\begin{aligned} V_\mathrm{TG}= & {} \frac{qN_\mathrm{channel}t_\mathrm{Si}}{2C_\mathrm{ox}}+\frac{\left( \alpha -1\right) (V'_\mathrm{bi}+V_\mathrm{DS})-\beta V_\mathrm{bi}}{\alpha +\beta -1}\nonumber \\&+\, \frac{\left( \delta +\beta -1\right) V_\mathrm{FB1}+\left( \alpha -\delta \right) V_\mathrm{FB2}}{\alpha +\beta -1}, \end{aligned}$$
(7)

where

$$\begin{aligned} \alpha= & {} \frac{\sinh \left( \lambda w_\mathrm{b}\right) }{\sinh \left( \lambda L\right) },\\ \beta= & {} \exp \left( -\lambda w_\mathrm{b}\right) -\alpha \exp \left( -\lambda L\right) ,\\ \delta= & {} \alpha \exp \left( -\lambda L\right) \cosh \left( \lambda L_1\right) +\exp \left( -\lambda L_1\right) \sinh \left( \lambda w_\mathrm{b}\right) . \end{aligned}$$
Fig. 5
figure 5

a \(I_\mathrm{D}\)–\(V_\mathrm{GS}\) (log scale) for different gate dielectrics. b \(V_\mathrm{TG}\) extraction for \(\mathrm{HfO}_2\) using TC method. Given scaled values of \(g_\mathrm{m}\), \(\mathrm{d}g_\mathrm{m}/\mathrm{d}V_\mathrm{GS}\), \(\mathrm{d}^2g_\mathrm{m}/\mathrm{d}V^2_\mathrm{GS}\). \(V_\mathrm{DS}=1\,\mathrm{V}\)

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4 Results and discussion

The model was tested against simulation results for different parameter values. The n-type DMDG TFET investigated here has been simulated with Silvaco Atlas [27]. In all simulations, junctions were quasiperfectly abrupt. The models used were concentration-dependent mobility, electric-field-dependent mobility, Shockley–Read–Hall (SRH) recombination, concentration-dependent SRH lifetime, Auger recombination, bandgap narrowing, and Kane’s band-to-band tunneling. In the simulation, the transconductance change (TC) method was used to derive \(V_\mathrm{TG}\). In this method, \(V_\mathrm{TG}\) is the gate voltage corresponding to the maximum of the transconductance derivative, \({\mathrm{d}g_\mathrm{m}}/{\mathrm{dV}_\mathrm{GS}}\). In Fig. 5a, the drain currents for different gate dielectrics are plotted. Figure 5b shows the value (\(g_\mathrm{m}\)) and first (\(\mathrm{d}g_\mathrm{m}/\mathrm{dV}_\mathrm{GS}\)) and second derivatives (\(\mathrm{d}^2g_\mathrm{m}/\mathrm{d}V^2_\mathrm{GS}\)) of the drain current for \(\mathrm{HfO}_2\) at \(V_\mathrm{DS}=1\,\mathrm{V}\). At \(V_\mathrm{GS}=1.15\,\mathrm{V}\), an inflection point in the \(g_\mathrm{m}\) curve and a peak in the \({\mathrm{d}g_\mathrm{m}}/{\mathrm{dV}_\mathrm{GS}}\) curve occur, representing the transition point between quasiexponential and linear dependence of \(I_\mathrm{D}\) on \(V_\mathrm{GS}\). The extracted \(V_\mathrm{TG}\) is 1.15 V, much higher than the value obtained from the constant-current method.

Fig. 6
figure 6

\(V_\mathrm{TG}\) versus \(V_\mathrm{DS}\) for \(\epsilon _\mathrm{ox}=21\), 27

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Fig. 7
figure 7

\(g_\mathrm{m}\) versus \(V_\mathrm{GS}\). Points marked correspond to maximum of \(\mathrm{d}g_\mathrm{m}/\mathrm{d}V_\mathrm{GS}\). \(\epsilon _\mathrm{ox}=21\)

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Figure 6 plots the variation of \(V_\mathrm{TG}\) with the applied drain bias for two high-k dielectrics with \(\epsilon _\mathrm{ox}=21\), 27. It can be seen that the model shows good agreement with the simulation results. \(V_\mathrm{TG}\) is higher for higher \(V_\mathrm{DS}\). The reason for this can be understood from Fig. 7, which shows that, for higher drain voltage, the gate retains quasiexponential control of the current over a larger voltage range. The effect of length scaling on \(V_\mathrm{TG}\) is investigated in Fig. 8. It is found that \(V_\mathrm{TG}\) is independent of device length. This is due to the limiting effect of gate length on \(V_\mathrm{TG}\), as depicted in Fig. 9. The conduction mechanism in the TFET is completely different from that in a MOSFET. The maximum electric field is always at the source–body junction, and is independent of the device length. The proposed model is able to describe this effect also.

Fig. 8
figure 8

\(V_\mathrm{TG}\) versus L for \(V_\mathrm{DS}=0.6\), \(1\,\mathrm{V}\). \(\epsilon _\mathrm{ox}=21\)

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Fig. 9
figure 9

\(I_\mathrm{D}\)–\(V_\mathrm{GS}\) curves for different gate lengths. \(\epsilon _\mathrm{ox}=21\)

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\(V_\mathrm{TG}\) increases when the Si layer thickness is increased, as presented in Fig. 10. The DMDG TFET is sensitive to the body thickness; this can be understood from the shape of the \(I_\mathrm{D}\)–\(V_\mathrm{GS}\) curve, as shown in Fig. 11. As the film becomes thinner, the electric field lines change. In turn, this increases the gate control of the barrier width in the tunnel junction, which results in a decreased \(V_\mathrm{TG}\). Figure 12 shows that use of high-k dielectric lowers \(V_\mathrm{TG}\). This is due to the fact that high-k dielectric aids the gate to have better capacitive control over the barrier width at the tunnel junction. The proposed model can predict this effect too.

Fig. 10
figure 10

\(V_\mathrm{TG}\) versus \(t_\mathrm{Si}\) for \(V_\mathrm{DS}=0.8\), \(1\,\mathrm{V}\). \(\epsilon _\mathrm{ox}=7.5\)

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Fig. 11
figure 11

\(I_\mathrm{D}\)–\(V_\mathrm{GS}\) curves (linear scale) for different Si layer thicknesses. \(\epsilon _\mathrm{ox}=3.9\), \(L=50\,\mathrm{nm}\)

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Fig. 12
figure 12

\(V_\mathrm{TG}\) versus \(\epsilon _\mathrm{ox}\). \(V_\mathrm{DS}=1\,\mathrm{V}\)

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Inversion charge was not included in the model derivation. The inversion voltage \(V_\mathrm{inv}\) in a TFET can be calculated using the method described in [28]. The same approach was used here for a DMDG TFET to calculate the inversion voltage, as shown in Fig. 13. For the DMDG structure with \(\mathrm{HfO}_2\) gate dielectric, the numerical simulation shows that, at \(V_\mathrm{DS}=1\,\mathrm{V}\), inversion occurs at 1.2 V, while Fig. 3 shows that \(V_\mathrm{TG}=1.14\,\mathrm{V}\). Similarly, at \(V_\mathrm{DS}=0.7\,\mathrm{V}\), \(V_\mathrm{inv}=0.95\,\mathrm{V}\) while \(V_\mathrm{TG}=0.9\,\mathrm{V}\). Since inversion occurs after the threshold point, the effect of inversion charge is negligible. Another fact to mention is that, when the source doping is very high, the band profile of a TFET resembles that of a MOSFET [29, 30]. In this case, the conditions for deriving the threshold voltage from the surface potential will change. Therefore, this model might not predict the threshold voltage accurately in such cases.

Fig. 13
figure 13

Surface potential versus \(V_\mathrm{GS}\)

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5 Conclusions

A model for the gate threshold voltage of a DMDG TFET has been developed based on its physical definition. A numerical simulation study was carried out to verify the proposed model. The transconductance change method was employed to extract \(V_\mathrm{TG}\) from the simulation. Model results are consistent with simulation results for different drain biases and varying device physical parameters. The effect of scaling of gate length and Si layer thickness on \(V_\mathrm{TG}\) can be well predicted by the model. The proposed model shows improved device performance in terms of threshold voltage when high-k dielectric is used. Since the threshold voltage is one of the most significant parameters of a device, this model will be useful for further investigation of device performance.