1 Introduction

Quantum-dot Cellular Automata (QCA) technology, which is a candidate technology to replace CMOS technology, promises extremely dense, extra low-power and high-speed structures at Nano scale [1]. The logic state in this technology is determined based on the position of the electrons in quantum cells [1,2,3,4,5]. On the other hand, full adders have important roles in digital circuits. It is because other logical operations and mathematical functions can be constructed using full adder [1,2,3,4]. So, the main object in designed circuits is to reduce complexity (cell count) and occupation area and increase the operation speed.

Recently, several efforts have been done to improve the efficiency of the full adder implementation in the QCA technology [6,7,8,9,10,11,12]. Roohi et al. [6] have offered a QCA full adder that requires 52 cells, and 0.04 μm2 area. Sasamal et al. [7] have offered a QCA coplanar one-bit full adder that requires 49 cells, and 0.04 μm2 area. Navi et al. [8] have presented a QCA full adder using five-input majority gate that requires 61 cells, and 0.03 μm2 area. The authors of [9] have developed QCA coplanar full adder using 73 cells that has 0.04 μm2 area. Kianpour et al. [10] have presented a one-bit coplanar full adder using three three-input majority gates that requires 69 cells and 0.07 μm2 area. Hashemi and Navi [11] have developed QCA coplanar full adder using 71 cells that has 0.06 μm2 area. Angizi et al. [12] have presented a QCA one-bit full adder using XOR gate and majority gate that requires 95 cells and 0.09 μm2 area. However, these full adder architectures have advantages, but the complexity and required area of the full adder architecture in the QCA technology can be reduced as described in this paper.

In this paper, we propose a new QCA four-bit Ripple Carry Adder (RCA), which is constructed based on the developed robust QCA one-bit full adder. The developed circuits are simulated using QCADesigner tool. The results demonstrate that the developed circuits have advantages compared to other QCA circuits in terms of speed, area and complexity.

The rest of this paper is organized as follows. In Section 2, an over view of the QCA and related works are presented. A novel QCA one-bit full adder cell is developed in Section 3. In addition, we construct a new four-bit QCA RCA based on this novel full adder. Section 4 compares the developed circuits to other QCA circuits. Finally, Section 5 concludes this paper.

2 Background

This section investigates the QCA cell, QCA wire, QCA gates, QCA full adder circuits and related works.

2.1 QCA Cell

A QCA cell is a square-shape structure that has four quantum dots positioned at the four corners and two electrons. These two electrons can move between the dots [5]. Due to Coulomb repulsion, the diagonally opposite corners are considered as the position of electrons in the QCA cell. The position of the electrons in the QCA cells determines the logic state as shown in Fig. 1 [1,2,3,4].

Fig. 1
figure 1

The possible QCA logic state: logic ‘0’ and logic ‘1’ [1,2,3,4]

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2.2 QCA Wire

QCA contact wires are formed from the same QCA cells that interact with each other to transmit information. Figure 2 shows three types of wire crossing methods in the QCA technology [7].

Fig. 2
figure 2

Wire crossing methods: a single layer, b multi-layer, c logical crossing [7]

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2.3 QCA Gates

Inverter gate and majority gate are two main gates in the QCA technology. Figure 3 shows three types of the formerly presented inverters [6].

Fig. 3
figure 3

Three types of inverter [6]

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In this figure, the input polarization is inversed when it reaches the output cell.

In the majority gate, the polarization of output cell is determined by voting on the polarization of the input cells. Figure 4 shows two types of three-input majority gate [4].

Fig. 4
figure 4

Two types of three-input majority gate: a Original Majority Gate (OMG), b Rotate Majority Gate (RMG) [4]

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The logical function of three-input majority gate is shown by following equation [4]:

$$ \text{Maj3 (A, B, C) = AB + AC + BC} $$
(1)

In addition, five-input majority gate is defined according to (2) [7].

$$\begin{array}{@{}rcl@{}} \text{Maj5 (A, B, C, D, E)}&=&\text{ABC~+~ABD~+~ABE~+~ACD~+~ACE~+~ADE}\\&&\text{+~BCD~+~BCE~+~BDE~+~CDE} \end{array} $$
(2)

Figure 5 shows three types of five-input majority gate [8, 9, 13].

Fig. 5
figure 5

Three types of five-input majority gate, a in [8] b in [9] c in [13]

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2.4 QCA Full Adder

In the full adder with inputs A, B and Cin, the outputs of sum and Carryout are calculated as follows [14]:

$$ {\text{Carry~}}_{\text{out}}\text{\,=\,AB\,+\,BCin\,+\,ACin} $$
(3)
$$ \text{Sum\,=\,ABCin\,+}\,\overline{\text{A}}\,\overline{\text{B}}\text{Cin\,+}\,\overline{\text{A}}\text{B}\overline{\text{C in}}\,\text{+\,A}\overline{\text{BCin}}\,=\text{A}\oplus \text{B}\oplus \text{Cin} $$
(4)

To design the full adder in the QCA technology, Carryout can be reformulated as follows:

$$ {\text{Carry }}_{\text{out}}\text{\,=\,Maj3(A, B, Cin)} $$
(5)

In addition, sum can be reformulated as follows [15,16,17]:

$$\begin{array}{@{}rcl@{}} \text{Sum} &=& \text{Maj3} (\text{Maj3} (\text{A, B, Cin}), \text{Maj3} (\text{A, B, Cin}), \text{Maj3} (\text{A, B, Cin}))\\ &=& \text{Maj3} (\overline{\text{Carry}_{\text{out}}}, \text{Maj3} (\text{A}, \text{B}, \overline{\text{Carry}_{\text{out}}}), \text{Cin}) \\ &=& \text{Maj3} (\overline{\text{Carry}_{\text{out}}}, \text{Maj3} (\text{A, B}, \overline{\text{Carry }_{\text{out}}}), \text{B}) \\ &=& \text{Maj3} (\overline{\text{Carry}_{\text{out}}}, \text{Maj3} (\text{B}, \text{Cin}, \overline{\text{Carry }_{\text{out}}}), \text{A})\\ &=& \text{Maj5} (\overline{\text{Carry}_{\text{out}}}, \overline{\text{Carry}_{\text{out}}}, \text{Cin}, \text{A, B}) \end{array} $$
(6)

So, this output can be implemented using five-input majority gate.

2.5 Previously Reported Designs

Kianpour et al. [10] presents a one-bit coplanar full adder using only three three-input majority gates as shown in Fig. 6.

Fig. 6
figure 6

The QCA full adder in [10] a logical diagram b QCA layout

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This full adder is consists of 69 cells, which has a 0.07 μm2 area. The latency of this full adder is 1 clock cycle.

The authors of [11] have developed QCA coplanar full adder using 71 cells as shown in Fig. 7.

Fig. 7
figure 7

The QCA full adder in [11] a logical diagram b QCA layout

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In this full adder, the latency is 1.25 clock cycle, and the area is 0.06 μm2. According to Fig. 7, this full adder consists of one three-input majority gate, one five-input majority gate and two inverter gates. Sasamal et al. [7] presents a QCA coplanar one-bit full adder, which is shown in Fig. 8.

Fig. 8
figure 8

The QCA full adder in [7] a logical diagram b QCA layout

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This full adder has less complexity in comparison with two designs in [10, 11]. It is consists of 49 cells, which has a 0.04 μm2 area, the latency is 1 clock cycle as using one three-input majority gate, one five-input majority gate and two inverter gates.

In addition, Angizi et al. [12] presents a QCA coplanar four-bit Ripple Carry Adder (RCA), using 494 cells as shown in Fig. 9. The latency of this design is 4.25 clock cycles, which has a 0.68 μm2 area.

Fig. 9
figure 9

The layout of four-bit QCA RCA in [12]

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The authors of [14] have developed the QCA coplanar four-bit RCA using 262 cells as shown in Fig. 10. The latency of this design is 1.75 clock cycles, which has a 0.208 μm2 area.

Fig. 10
figure 10

The layout of four-bit QCA RCA in [14]

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Mohammadi et al. [19] have developed the QCA multilayer four-bit RCA using 237 cells as shown in Fig. 11. The latency of this design is 1.5 clock cycles, which has a 0.24 μm2 area. There are three layers of cells in this design.

Fig. 11
figure 11

The layout of four-bit QCA RCA in [19]

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3 The Developed Circuits

This section presents a novel QCA one-bit full adder. Then a novel QCA coplanar four-bit RCA circuit is presented based on this one-bit full adder.

3.1 The Developed QCA One-bit Full Adder Circuit

In this section, a robust QCA one-bit full-adder is presented. Figure 12 demonstrates the structure of the developed QCA full adder circuit.

Fig. 12
figure 12

The developed QCA full adder: a block diagram b layout

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As it is shown in this figure, the carry is produced using the three-input majority gate and the sum is produced using a three-input QCA XOR. The arrangement of inputs and outputs of cells in this full adder is such that it can be used in both single-layer design and multilayer design.

3.2 The Developed Four-bit QCA RCA Circuit

Figure 13 shows the developed four-bit QCA RCA circuit, which is utilized the developed QCA one-bit full-adder as its structured unit.

Fig. 13
figure 13

The layout of the developed four-bit QCA RCA

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The developed four-bit RCA is consists of 209 cells, which has a 0.3 μm2 area. So, the cells are also located in four clock cycles and latency of circuit is 1.25 clock cycles.

4 Simulation and Comparison Results

This section outlines the simulation results for the developed circuits and compares these results with other circuits. In this section, the cost value is computed using (7):

$$ \text{Cost} = \text{Latency} \times \text{Area} $$
(7)

Where Latency denotes the number of required clock cycle and Area is shown in terms of μm2.

4.1 The Developed QCA One-bit Full Adder Circuit

Figure 14 shows the simulation results for the developed QCA one-bit full adder.

Fig. 14
figure 14

The simulation results for the developed one-bit full adder

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As it is shown in the achieved simulation waveform in Fig. 14, the developed circuit for the QCA full adder performs correctly. Table 1 shows the extensive comparison of the developed QCA full adder with other QCA full adders in [6,7,8,9,10,11,12].

Table 1 Comparison table for the QCA full adders
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According to Table 1, our simulation results demonstrate that the developed QCA full adder provides an improvement in terms of area occupation, cell count, circuit latency and cost in comparison with other QCA full adder circuits in [6,7,8,9,10,11,12], which are implemented in single-layer. However the developed one-bit QCA full adder is also competitive with multilayer designs.

In particular, the cell count, latency and cost of the developed full adder are reduced by about 16%, 50% and 50% in comparison with QCA full adder in [7]. Despite similar area to that of the multilayer design presented in [6], our developed design surpasses it by 21%, 33%, and 33% improvements in terms of cell count, latency and cost, respectively.

4.2 The Developed High-speed Four-bit RCA

The simulation results of the developed four-bit QCA RCA are shown in Fig. 15.

Fig. 15
figure 15

The simulation results for the developed four-bit RCA

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According to Fig. 15, after 1.25 clock cycles delay, the sum of the inputs (A, B, Cin) is calculated, which is absolutely corrected. Table 2 contains a comparison between our developed four-bit QCA RCA and other four-bit QCA RCA circuits.

Table 2 Comparison table for the QCA four-bit RCA
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Based on our simulation results, which are shown in Table 2, the developed design has the lowest circuit latency and cell count compared to other QCA RCA designs in [11, 12, 14, 19,20,21,22,23]. In particular, the design in [14] has a lower area occupation than our developed design, but the developed design is able to counteract that by having a lower latency and cell count, as there are 20% and 28% improvements in cell count and circuit latency, respectively.

According to Table 2, our developed four-bit QCA RCA has the minimum value in terms of the circuit latency except the design in [24]. In comparison to [24], it is worth noting that application of the design in [24] is only in multilayer design and it cannot be used in single-layer. In other words, our developed design has highest-speed coplanar design in single-layer applications, so far.

5 Conclusion

The QCA is a suitable alternative for CMOS technology at Nano-scale level due to low-power consumption, high-speed and high-density devices. On the other hand, full adder is one of the most important circuits in logical operations and mathematical functions such as multipliers. In this paper, a novel QCA structure was developed for one-bit full adder. We also used this new one-bit full adder to design a robust, efficient and high-speed four-bit RCA in the QCA technology. Our simulation results showed that our developed designs have yielded significant improvements in term of circuit latency and speed.

According to results and tables, among the designs that are single-layer and have coplanar application, the cell count and circuit latency of the developed coplanar four-bit RCA are considerably reduced. The developed four-bit ripple carry adder in the QCA technology has high-speed and low-complexity design, so far.