A picowatt, 3.88 ppm/°C, 0.011%/V subthreshold CMOS voltage reference biased by GSCC current source

Abstract

This paper presents a picowatt-level power consumption CMOS voltage reference which is appropriate for low power applications. A gate-to-source connected cascode current source which is consisted of two transistors operating in the subthreshold region is used to generate bias current of proposed voltage reference, so resistors and MOSFETs operating in deep triode region are saved. The proposed circuit is implemented in the standard 0.18-um process. Simulation results of proposed voltage reference show that the minimum supply voltage is 0.45 V, consuming only 83pW at room temperature. The value of proposed voltage reference is 209.2 mV and temperature coefficient is 3.88 ppm/°C with a temperature range of −20–125 °C. PSR of proposed voltage reference is −65.54 dB at 100 Hz, and the LS is reduced to 0.011%/V by utilizing the cascode structure when the supply voltage changes from 0.45 to 1.8 V. In addition, the active area is only 0.0029 mm².

1 Introduction

Low-power and miniaturized integrated circuits (ICs) have gained continuous attention due to the high demand of next-generation power-aware applications such as biomedical devices [1], Internet of Things (IoT) [2] and energy harvesting systems [3]. The power supply of these applications whose energy source is micro-batteries or surrounding natural energy is not sufficient, and these applications must work for a long time. Therefore, the voltage reference circuit, as an indispensable component in any mixed-signal ICs, is required to generate a reference voltage while consuming low power. Simultaneously, the voltage reference is expected to remain robustness as the process, voltage and temperature are changed. In this research, a low-power, small-area, low-temperature coefficient (TC) and low-line sensitivity (LS) voltage reference is presented.

Conventional voltage references are generated by bandgap voltage references (BGRs). Bipolar transistors (BJTs) and resistors are essential of BGRs, and they dissipate much power and occupy large area. BGRs consist of two parts, one is complementary-to-absolute-temperature (CTAT) unit generated by the base-emitter junction voltage of the bipolar transistor, and the other is a proportional-to-absolute-temperature (PTAT) cell which is produced with the difference of two base-emitter junctions [4]. The reference voltage generated by BGRs varies very little with the variation of process. Some of them achieve very low temperature coefficients by temperature compensation, for example, second-order, high-order or curvature compensation [4,5,6,7,8,9]. Power Supply Rejection (PSR) could be reduced dramatically [10] with amplifiers. However, they hardly operate properly when the supply voltage is lower than 0.8 V because of the presence of BJTs. Thus, they are not superior in low power and low voltage applications. In order to generate reference voltages at low supply voltages, MOSFETs are required to operate in the subthreshold region. Their power consumption is much lower than conventional BGRs, so they have become a favorable alternative to conventional BGRs. Some nanowatt or picowatt reference voltages have been proposed [11,12,13,14,15,16] in recent years. In [11], Zhan et al. presented a voltage and a current reference which have an amplifier and two types of resistors. Though the MOSFETs are all operated in the subthreshold region, resistors in [11] occupy large area and dissipate a lot of power compared to the core circuit of the voltage reference. The bias current in [14] is generated by the bulk-driven current generator. The threshold voltage of an NMOS is reduced by raising its substrate voltage. And there is a designed voltage to make it operate in deep triode region. Similarly, there are transistors operating in deep triode region to act as resistors in [15, 16]. Hence, a specific gate voltage is required which needs an extra block to generate. In [17], there are two voltage references and a self-biased current generator for both voltage references. The difference of two voltage references in [17] is active load. One is compensated by the threshold voltage difference of different transistors and thermal voltage (V_T), and the other is a diode implemented through a transistor which is a CTAT unit and compensated by the voltage difference of the gate-to-source with a positive temperature coefficient. The power of voltage references implemented in [12, 13] are picowatt-level. None of them requires an additional gate voltage. The bias current is generated by self-biased in [12, 13]. Although the power of these works is low, other performances such as TC and PSR are not as attractive as power.

In this work, a picowatt CMOS subthreshold voltage reference is proposed. A new biasing which is formed with two transistors is proposed. One is gate-to-source connected (GSC) NMOS, and the other is a cascode transistor. Firstly, the gate and source of GSC NMOS are connected to flow a picoampere level bias current and resistor is replaced by GSC NMOS to reduce area of layout. Meanwhile, the gate and source of GSC NMOS are connected to GND, which is the same as the substrate. Hence, there is no need to consider the back-gate effect of GSC NMOS unlike [18] and the bias current generated in this way is more robustness. Secondly, a cascode transistor is added to increase the resistance of the bias current source and shield the variation from the supply voltage to make it more ideal. The drain-induced-barrier-lowering (DIBL) effect of GSC NMOS is also eliminated by this method. Moreover, the gate of the cascode NMOS is connected to voltage reference, the smaller variation with PVT is more beneficial for the robustness of the bias current and reference voltage than in [12] where the gate is connected at other notes in [12] though they are both self-biased. Hence, all MOSFETs operate in the subthreshold region. The specific gate voltage for MOSFETs which is operating in deep triode region is also eliminated by this method. This method decreases LS and low-frequency PSR without increasing minimum supply voltage in contrast to [12, 18]. As the results show, the voltage reference circuit proposed in this paper has a distinct reduction in power and area. Compared with subthreshold voltage references proposed in recent years, though the temperature range (−20–125 °C) is smaller than −40–125 °C which is because carrier mobility reduced too much in lower temperature, the power, area, and TC of the proposed voltage reference are more competitive.

The rest of this paper is organized as follows. Section 2 presents the circuit and operation principle of the voltage reference proposed in this paper; Sect. 3 details the primary design considerations of the circuit and presents the size of transistors; Sect. 4 shows the simulation results of the circuit and gives the comparison of obtained results with other voltage references reported recently. Finally, the paper is concluded in Sect. 5.

2 Proposed design and operation principle

2.1 MOSFET subthreshold current model

The transistors in the voltage reference circuit proposed in this paper all operate in the subthreshold region, as a result, an appropriate MOSFET current model must be required. It is obtained from the MOSFET subthreshold current model (MSCM) [19] that the drain current of a MOSFET is composed of a forward (I_F) and a reverse current (I_R), which is as the following equations:

$$I_{D} = I_{F} - I_{R} = I_{S} \left( {i_{f} - i_{r} } \right)$$

(1)

$$I_{S} { = }SI_{SQ}$$

(2)

where i_f and i_r are the forward and reverse inversion coefficients, and S is called the aspect ratio W/L of transistors. W and L are the width and length of channels, respectively. I_SQ is the process-related sheet normalization current that is described as:

$$I_{SQ} { = }\frac{1}{2}\mu \eta C_{ox} V_{T}^{2}$$

(3)

where μ is the carrier mobility, η = 1 + C_d/C_OX is the subthreshold slope factor where C_d is the depletion capacitance and C_ox is the gate capacitance per unit area that is dependent on the gate oxide thickness. C_d, which is a part of the subthreshold slope factor, is temperature-dependent. But compared with the threshold voltage of the transistor, the effect of temperature changes on it could be negligible. V_T = k_BT/q is thermal voltage which relies on Boltzmann’s constant (k_B = 1.38 × 10^-23 J/K), electron charge (q = 1.6 × 10^-19C) and the absolute temperature (T). The thermal voltage is approximately 26 mV at room temperature (T = 300 K). The correlation between normalized current (i_f(r)) and voltage is as the following equation:

$$\frac{{V_{G} - V_{TH} - \eta V_{S(D)} }}{{\eta V_{T} }} = \sqrt {1 + i_{f(r)} } - 2 + \ln \left( {\sqrt {1 + i_{f(r)} } - 1} \right)$$

(4)

where V_G, V_S and V_D are gate, source and drain voltages of the MOSFET with respect to the voltage of the substrate respectively. V_TH is the threshold voltage.

From Eq. (1) and Eq. (4), when an NMOS is operated in the weak inverse region (i_f <  < 1), the drain current (I_D) can be expressed by the following:

$$I_{D} = 2eI_{S} \exp \left( {\frac{{V_{G} - V_{TH} }}{{\eta V_{T} }}} \right)\left[ {\exp \left( {\frac{{ - V_{S} }}{{V_{T} }}} \right) - \exp \left( {\frac{{ - V_{D} }}{{V_{T} }}} \right)} \right]$$

(5)

in which, e is the Euler number (e≈2.7178), a constant in mathematics and I_D is almost independent of the drain voltage (V_D) when V_D is much larger than V_T (i.e. V_D ≥ 4V_T).

2.2 Circuit description

The complete circuit of proposed voltage reference in this paper is shown in Fig. 1, consisting of four parts: start-up circuit, CGCS bias circuit, an amplifier and the active load. Transistors M1-M5 and devices in the amplifier are standard PMOS and NMOS devices (1.8 V), and M6 is a high threshold-voltage transistor (3.3 V).

Fig. 1

The complete circuit of the proposed voltage reference

The core circuit of proposed picowatt-voltage reference is shown in Fig. 2(a). And it can be simplified to the structure shown in Fig. 2(b). M1 and M2 in Fig. 1 are the gate-to-source connected cascode (GSCC) current source to generate bias current. The active load is composed of M5 and M6.

Fig. 2

Schematic of the proposed voltage reference: a Core circuit b Simplified structure

Voltage reference proposed in this paper is generated by the branches composed of M5 and M6 that operate in the subthreshold region, and the current flowing through M5 and M6 is equal which is generated by GSCC current source. Reference voltage is generated by two branches rather than three branches in [12], one is bias current and the other is active load. There is a similar bias current proposed in [18], but DIBL effect on threshold voltage of cut-off transistor is out of consideration in [18]. Hence, its LS and PSR are poor. In proposed voltage reference, M2 in Fig. 2(a) is designed to increase resistance of the bias current and shield the variation from the supply voltage. In the meantime, there is an amplifier in proposed design. Though there are some additional power due to amplifier, the operation principle of the voltage reference is not affected by the amplifier, meanwhile, the value of voltage reference and temperature coefficient (TC) are not influenced by the amplifier. Then, because of the introduction of the amplifier, a negative feedback loop (as shown in Fig. 2(a)) is introduced in the circuit to make the circuit more robustness. Therefore, the LS and PSR of the voltage reference have been effectively improved.

2.3 Proposed voltage reference

The equivalent resistance of M1 is large (GΩ), as shown in Fig. 3, so the drain voltage is much larger than V_T. Hence, the biased current generated by GSC-NMOS is:

$$I_{D1} = 2eS_{1} I_{SQ} \exp \left( {\frac{{ - V_{TH1} }}{{\eta_{1} V_{T} }}} \right)$$

(6)

Fig. 3

The equivalent resistance of M1 with different L at V_DS = 250 mV

Since M5 and M6 operate in the weak inverse region, and their drain voltages are larger than 4V_T, the following two equations can be obtained:

$$I_{D5} = 2eS_{5} I_{SQ} \exp \left( {\frac{{V_{G5} - V_{TH5} - \eta_{5} V_{REF} }}{{\eta_{5} V_{T} }}} \right)$$

(7)

$$I_{D6} = 2eS_{6} I_{SQ} \exp \left( {\frac{{V_{G6} - V_{TH6} }}{{\eta_{6} V_{T} }}} \right)$$

(8)

For the reason that I_D5 = I_D6 = I_D1 and V_G5 = V_G6, the voltage reference (V_REF) in Fig. 1 can be expressed as:

$$V_{REF} = \frac{{V_{TH6} - V_{TH5} }}{{\eta_{5} }} + \frac{{\eta_{5} - \eta_{6} }}{{\eta_{1} \eta_{5} }}V_{TH1} + \frac{{\eta_{6} }}{{\eta_{5} }}V_{T} \ln \left(\frac{{S_{1} I_{SQ1} }}{{S_{6} I_{SQ6} }}\right) - V_{T} \ln \left(\frac{{S_{1} I_{SQ1} }}{{S_{5} I_{SQ5} }}\right)$$

(9)

Threshold voltage of MOSFETs can be approximated by an equation that has a linear negative dependence on temperature and it is expressed as [20]:

$$V_{TH} (T) = V_{TH} \left( {T_{0} } \right) + k\left( {T - T_{0} } \right)$$

(10)

where V_TH(T₀) is threshold voltage at room temperature and k, which is negative, is the first-order temperature coefficient of threshold voltage. The temperature dependencies of M1, M5 and M6 are shown in Fig. 4. It can be seen that the absolute value of the slope of M5 is smaller than that of M6 so the gap of the threshold voltages is still a CTAT voltage, but the absolute value of the slope decreases obviously.

Fig. 4

Simulation results: V_TH of M1, M5 and M6 with temperature

Since η₅ and η₆ depend on the device and vary little with temperature changes. Moreover, it is known from Eq. (5) that when transistors operate in the subthreshold region, making V_S is 0 V and V_D is much larger than the thermal voltage, V_G and ln (I_D) are linearly related with a slope of 1/ηV_T, and the result is obtained by simulation as shown in Fig. 5, the slopes are similar, so η₅ and η₆ can be regarded as equal at room temperature. Hence, Eq. (9) approximated as:

$$V_{REF} = \frac{{V_{TH6} - V_{TH5} }}{{\eta_{5} }} + V_{T} \ln \left(\frac{{S_{5} }}{{S_{6} }}\right)$$

(11)

Fig. 5

V_G vs. ln (I_D) at V_S = 0 mV

It can be seen that the source of M5 is not connected to GND, so reference voltage is affected by the back-gate effect of M5, the relationship between threshold voltage of the transistor and the substrate voltage can be approximated as [21]:

$$V_{TH} (T) = V_{TH0} + \alpha V_{SB}$$

(12)

in which α is positive and V_TH0 is threshold voltage when there is no back-gate effect. From Eq. (10) to (12), the temperature coefficient (TC) of the reference voltage can be obtained as:

$$V_{REF} = \frac{{V_{TH6} - V_{TH5} }}{{\eta_{5} + \alpha }} + \frac{{\eta_{5} }}{{\eta_{5} + \alpha }}V_{T} \ln \left(\frac{{S_{5} }}{{S_{6} }}\right)$$

(13)

Setting $\frac{{\partial V_{REF} }}{\partial T} = 0$, the optimal ratio of S5 and S6 can be expressed as:

$$\left(\frac{{S_{5} }}{{S_{6} }}\right)_{OPT} = \frac{{\eta_{5} }}{{\eta_{5} + \alpha }}\left[\frac{{k_{6} - k_{5} }}{{\eta_{5} }} + \frac{{k_{B} }}{q}\ln \left(\frac{{S_{5} }}{{S_{6} }}\right)\right]$$

(14)

However, the back-gate effect of M5 has little effect on the voltage reference proposed in this paper, for example, the point when temperature coefficient is zero remains unchanged. It is deserving to pay attention that for Eq. (14), μ₁ = μ₅ = μ₆ is assumed, so that the temperature characteristics of I_SQ are neglected during the analytical process.

3 Design considerations

The performances of voltage references are not only temperature coefficient (TC) and power, but also LS, PSR and so on. In order to get superior performances, these aspects and some trade-offs need to be considered in the design of the circuit.

3.1 Verification of MOSFET subthreshold current model (MSCM) of M1

A precise voltage reference is requested for a lot of next-generation power-aware applications, so it is crucial to use the proper model during the design of the circuit. All transistors proposed in this paper operate in the subthreshold region, so MOSFET subthreshold current model (MSCM) is employed. However, the case where the gate and source are connected to GND, which means that the gate and source are zero voltage with respect to the substrate voltage (V_G = V_S = 0 in Eq. (5)), was not taken into consideration of MSCM proposed in [19]. It is required to be verified whether M1 is suitable for MSCM, hence a set of simulation results, which is the curve of the drain current (I_D) of M1 versus V_D when V_G = V_S = 0 at T = 27 °C, is presented in Fig. 6. Simultaneously, V_G = V_S = 0 is substituted into Eq. (5), and the other parameters in Eq. (5) such as threshold voltage are accessed from the standard 0.18-um process. The drain current vs. V_D is plotted by MATLAB.

Fig. 6

the drain current of M1 vs. V_D at T = 27°C

The graph plotted by MATLAB is compared with the simulation result and it can be seen that the error is minor. Because the drain voltage of M1 increases directly during the simulation, a continuous change in threshold voltage of M1 caused by the DIBL effect. However, the threshold voltage variation is not taken into consideration in the plotted curve by MATLAB. The maximum error is 4% and is reduced to 1.3% with the cascode transistor (M2) which is illustrated in Part 3.2 of Sect. 3, so that the error is able to ignore. Therefore, the drain current equation in the MSCM, i.e., Eq. (5), remains applicable when the gate and source of the transistor are connected to GND.

3.2 Supply voltage sensitivity

The dependence of voltage references on supply voltage is expressed by the line sensitivity (LS). The LS is given by:

$${\text{LS}} = \frac{{\Delta V_{REF} }}{{\Delta V_{DD} \times V_{REFm} }} \times 100\%$$

(15)

where ΔV_DD means the range of V_DD and ΔV_REF means the variation value of the voltage reference, which is equal to V_REF,max–V_REF,min. V_REFm is the average value of V_REF within ΔV_DD. ΔV_REF plays a determinative role in Eq. (15), and it is obtained from Eq. (9) that the parameter affected by the change in V_DD is mainly the threshold voltage of the transistor because of DIBL effect. Temperature coefficient is put firstly in the derivation of Eqs. (9–14). As the supply voltage varies, the vary of V_th1 plays the most significant role for the LS results, but it is not a decisive factor in the derivation of the temperature coefficient, so V_th1 is neglected in the derivation because the coefficient is small with other factors.

The influence of the DIBL effect on threshold voltage can be expressed as [22]:

$$V_{TH} = V_{{TH{0}}} - \lambda V_{{{\text{DS}}}}$$

(16)

in which V_TH0 represents the threshold voltage when the drain-to-source voltage is zero and λ is the DIBL effect factor, which is same when the length of transistors is equal [13]. Hence, the length of M5 and M6 is equal. Accordingly, V_TH1 is the most responsible factor for the LS results. Utilizing the shielding feature of cascode, the addition of M2 shields the influence of variation of V_DD on threshold voltage of M1, and the trend of V_TH variation is significantly weakened when the circuit reaches stability, as shown in Fig. 7. As a result, LS and low-frequency PSR are decreased by this method.

Fig. 7

V_TH of M1 versus V_DD

MOSFETs are generally immune to the channel length modulation effect when they operate in the subthreshold region, but DIBL effect makes the threshold voltage shift. To reduce the impact of DIBL effect on this design, the high-impedance transistors proposed in this paper are designed with large L.

3.3 Minimum supply voltage

The minimum value of the supply voltage must be determined to ensure that all transistors of the circuit are operated in the correct region. The saturation condition in the subthreshold region is satisfied when the drain-to-source voltage of the transistor is greater than 4 times thermal voltage. Therefore, from Fig. 1, the theoretical minimum supply voltage is expressed as:

$$\begin{gathered} V_{DDMIN} = \max \{ V_{DS1} + V_{DS2} + V_{DS3} ,V_{REF} + V_{DS5} + V_{DS4} \} \\ = \max \{ 12V_{T} ,V_{REF} + 8V_{T} \} = V_{REF} + 8V_{T} \\ \end{gathered}$$

(17)

The value of V_REF is designed to exceed 200 mV that is able to calculated by Eq. (13), so V_DDMIN depends on the value of V_REF because the value of V_T is 26 mV. And it can be seen from Eq. (13) that V_REF is determined by threshold voltage and the aspect ratio of M5 and M6. Thus, the closer V_TH of M5 and M6 is expected to reduce V_DDMIN. The simulation results show that V_REF is stable when the supply voltage is larger than 0.4 V, which is consistent with the analysis results obtained from Eq. (17).

3.4 Process Variations

From Eq. (13), the value of voltage reference proposed in this paper is related to the subthreshold slope factor (η) and the threshold voltage (V_TH) of transistors. Therefore, careful layout and large size devices are applied in order to reduce the effect of process variations on the reference voltage value. Figure 8 shows the Monte Carlo simulation results of the reference voltages and TCs obtained under the assumption that the mismatch and error of the process model used satisfy a Gaussian distribution. The average value of the reference voltage obtained at the end of 1000 simulations is 209.3 mV with a standard deviation of 0.45 mV. The Monte Carlo simulation of TC is illustrated in Fig. 8(b), where the mean value is 4.53 ppm/°C of 1000 simulations, the standard deviation is 0.9 ppm/°C, and the maximum value is 8.49 ppm/°C. The results obtained by Monte Carlo simulation and simulation of different process corners show that the PVT characteristics of the voltage reference proposed in this paper are quite good.

Fig.8

Monte Carlo simulation: a Voltage reference b Temperature coefficient

3.5 Optimal aspect ratio for temperature coefficient

The aspect ratio of M5 and M6 at zero temperature coefficient is calculated from Eq. (14) to be about 1.18. Figure 9 shows the temperature coefficient of proposed voltage reference versus S5/S6. The simulation is obtained by holding the size of the transistors except M6 and altering width of M6. As a result of the simulation, it is observed that the temperature coefficient is smallest when S5/S6 is 1.14 approximately.

Fig. 9

Simulated aspect ratio of transistors for optimal TC

Taking the above design considerations into account, the size of transistors in the voltage reference circuit proposed in this paper is shown in Table 1.

4 Simulation results

The proposed voltage reference based on GSCC current source is implemented in a standard 0.18-um CMOS process. To analyze the performance parameters of the circuit, post simulations including Monte Carlo are achieved on the Cadence Virtuoso platform. The layout of the reference circuit is shown in Fig. 10 with the active area of 2943 (55.19 um * 52.33 um) um².

Fig. 10

Layout of the proposed voltage reference

The variation tendency of proposed reference voltage with temperature when the supply voltage is 0.45 V is shown in Fig. 11, where the temperature range is −20–125 °C. From Fig. 11(a), it is obtained that the temperature coefficient (TC) is 3.88 ppm/°C. In this paper, TCs of five different process corners are simulated as shown in Fig. 11(b), and the corresponding temperature coefficients are 25.09, 25.61, 11.14 and 29.04 ppm/°C for ss, sf, fs and ff, respectively. Therefore, when considering the influence of PVT, the proposed circuit can still provide a voltage reference with low temperature coefficient.

Fig. 11

Voltage reference as a function of temperature when V_DD = 0.45 V

The variation curve of the voltage reference with supply voltage at room temperature (27 °C) is shown in Fig. 12. It can be seen from Fig. 12(a), that the voltage reference reaches stability when the supply voltage exceeds 0.4 V, which is consistent with the description in Part 3.3 of Sect. 3. Meanwhile, Fig. 12(b) shows that when the supply voltage changes from 0.45 to 1.8 V in the case of no cascode transistor (M2), the reference voltage increases by 0.21 mV with the LS of 0.078%/V. In comparison, with the addition of M2, the reference voltage increases by 0.05 mV, and LS is reduced to 0.011%/V.

Fig. 12

Voltage reference variation with supply voltage at 27°C: a 0–1.8 V b 0.45–1.8 V

The PSR of the voltage reference demonstrates the extent to which it is affected by the supply voltage ripple. As analyzed, Fig. 13(a) displays the PSRs when the supply voltage is 0.45 V at 10 Hz and 100 Hz are −67.34 dB and −65.54 dB, respectively. The PSRs at different process corners is also simulated. They are −53.29 and −67.56 dB at 100 Hz, as shown in Fig. 13(b), when process corners are ss and ff.

Fig. 13

PSR simulation results at 27 °C when supply voltage is 0.45 V

The current consumption variation versus temperature when supply voltage is 0.45 V obtained from the simulation is given in Fig. 14. It can be seen that the current consumption at room temperature (27 °C) is 185 pA approximately when the supply voltage is 0.45 V. Hence, power of proposed voltage reference is 83 pW.

Fig. 14

Current consumption variation with temperature at 0.45 V

For the reason that the performance of voltage references is quantified by many parameters, a Figure of Merit (FoM) is provided to present the overall performance of a proposed circuit. A FoM which takes temperature range, TC, power and active area of voltage references into account is defined as [12]:

$$FoM = \frac{{(T_{MAX} - T_{MIN} )^{2} }}{TC \times Power \times Area}$$

(18)

Table 2 summarizes the performance of the GSCC-biased voltage reference proposed in this paper compared with other low-power subthreshold CMOS voltage references. The lower power consumption and smaller temperature coefficient of the proposed circuit in this paper are concluded, while the circuit utilizes no resistors or operational amplifiers which occupy large active area, so FoM of proposed design is excellent.

Table 1 Size of transistors for core circuit of proposed voltage reference without start-up circuit

Table 2 Summary of performance and comparison with other works

5 Conclusion

This paper presents an 83-pW subthreshold CMOS voltage reference implemented in a 0.18-um process. A GSC-NMOS is used to act as a large resistor (GΩ) and generate the bias current for the proposed circuit. Meantime, a self-biased transistor is added to make current source more ideal and eliminate DIBL effect of GSC-NMOS. Therefore, there is no need for resistors, which occupy large active area, or MOS transistors operating in deep triode region where a specific gate voltage is required to be concerned. The voltage reference proposed in this paper obtains a TC of 3.88 ppm/°C and a LS of 0.011%/V. Simulation result show that the proposed reference voltage generator is suitable for IoT and biomedical devices due to its low power feature.

Appendix

Derivation of Eqs. (4) and (5) is shown below:

Firstly, only the forward inversion coefficient related to the source voltage is considered and Eq. (19) is obtained as:

$$\frac{{V_{G} - V_{TH} - \eta V_{S} }}{{\eta V_{T} }} = \sqrt {1 + i_{f} } - 2 + \ln \left( {\sqrt {1 + i_{f} } - 1} \right)$$

(19)

For the reason that i_f $\ll$ 1, so Eq. (19) is expressed as:

$$\exp \left(\frac{{V_{G} - V_{TH} - \eta V_{S} }}{{\eta V_{T} }} + 1\right) = \sqrt {1 + i_{f} } - 1$$

(20)

The right side of Eq. (20) is expanded with Taylor series at i_f = 0 to get Eq. (21):

$$\sqrt {1 + i_{f} } - 1 = 0 + \frac{{i_{f} }}{2} - \frac{{\left( {i_{f} } \right)^{2} }}{8} - \frac{{\left( {i_{f} } \right)^{3} }}{16} + R_{3} (i_{f} )$$

(21)

where R₃(i_f) is the third-order Taylor residual term. Since i_f $\ll$ 1, higher-order terms and Taylor residual term are ignored, formula (21) can be simplified to:

$$\sqrt {1 + i_{f} } - 1 \approx \frac{1}{2}i_{f}$$

(22)

From Eqs. (20) to (22), it is obtained that:

$$i_{f} = 2e\exp \left( {\frac{{V_{G} - V_{TH} - \eta V_{S} }}{{\eta V_{T} }}} \right)$$

(23)

Similarly, it is obtained that:

$$i_{r} = 2e\exp \left( {\frac{{V_{G} - V_{TH} - \eta V_{D} }}{{\eta V_{T} }}} \right)$$

(24)

Hence, Eq. (5) can be obtained from Eqs. (1), (22) to (23):

$$I_{D} = I_{F} - I_{R} = 2eI_{S} \exp \left( {\frac{{V_{G} - V_{TH} }}{{\eta V_{T} }}} \right)\left[ {\exp \left( {\frac{{ - V_{S} }}{{V_{T} }}} \right) - \exp \left( {\frac{{ - V_{D} }}{{V_{T} }}} \right)} \right]$$

(25)